DE2813079C3 - High security multi-computer system - Google Patents

Description

Temporary storage is available. ■ _; .

In this way, the delay time IS required to produce the time offset and the time tv required for the comparison are included in the computing time only once, regardless of how many program sections are required to determine a result. One in prop. 2 specified short time tz is for entering the calculation results in the. Cache required. This entry can, however, be made while the next program section is being processed and therefore does not need to be billed in terms of time.

Is determined by comparison that a computer delivers incorrect results, the computer concerned will continue to participate in the development the results prevented. A controlled restart of this computer takes place without the computing time of the To influence the overall system is possible.

Fig. 3 shows a three- computer system Rl, RI, A3

with an output circuit AS. The computers are started by means of a start pulse which is fed directly to computer R1 at a point ST, delayed to computer R2 by tt / 2 via a delay circuit VZl and delayed to computer R3 via delay circuits KZl and VZ2um ts . All computers are connected to a buffer ZS via a bus. Each computer saves its result in the buffer memory when it reaches a point in the program at which a comparison of the calculation results is to be carried out. He then continues to calculate immediately without waiting for the result of the comparison. A comparison and majority decision circuit VMS has access to the buffer memory, carries out the comparison and, by activating a switching device DS, ensures that the stored results are switched through to an output buffer AP when the comparison or the majority decision has been completed.

2 sheets of drawings

Claims (2)

1 2 speaking results from all computers in the intermediate - ■■ '· ■ ■ · ■ _ ■' 'Patent claims: · memory are available. Since the output of the results, not directly from the computers, but from intermediate 1. High security multi-computer system in which all computers receive the same information after the comparison has been carried out and 5 and the majority decision is made, 'is processed in a safe time offset against each other and ensures that no unchecked result is output to which the results of the individual computers are used The entire loss of time in the and majority decision circuit, which can be traced back to the synchronization and Vef test for processing errors in a comparison process, was passed on to information processing, which was previously T - (ts + tv \ - η , in particular for the control of tracking ίο, where ts the time delay between the first connected means of transport, marked and the computer that was started last, tv the following features to be carried out: 'the same time required and η the number' of the a) the individual computers (Ri, R 2, A3) deliver their same in the program, so that results can be reduced to TL = ts 4- tv to at least one intermediate memory and from the number of comparison processes rather (ZS) and then run immediately which can be made independent in the program,
next program step, an embodiment of the computer system according to the b) after the existence of all or one more invention is characterized in that the intermediate unity of the results in the buffer memory is structured in several stages. Through this (ZS) are these in the comparison and it is possible also very closely to one another Majority decision circuit (VMS) to save and compare 20 interim results compared, chen, since already during the comparison c) only in the case of a result recognized as correct, new result in the first stage of the intermediate storage provides the comparison and majority decision can be entered,
divorce switching (VMS) a signal will now be described in detail with the aid of three figures, an embodiment of its through- switching device (DS) for outputting the result to an output buffer, for example of the computer system according to the invention,
fer (AP). Figs. 1 and 2 show the timing of the pro- 2. Multi-computer system according to claim 1, data processing according to the prior art, characterized in that the intermediate memory (Fig. 1) and in the computer system (ZS) according to the invention is constructed in several stages. 30 (Fig. 2). 3 shows a block diagram of the computer system according to the invention. , -.- In Figs. 1 and 2, with bold lines are the Working phases of three computers A1, R2 and R3 and 35 of a comparison and majority decision The invention relates to a multi-computer system shown towards VMS , measured the preamble of claim 1. Fig. 1 relates to a multi-computer system Such a computer system was z. B. in the old according to the prior art, FIG. 2 to a ren application P 27 25 92Z9 (DE-AS 27 25 922) before computer system according to the invention, beat. The time lag in the sequence of 40 The small program to be processed by the computers Computer programs are created here on purpose and are divided into program sections of approximately the same length, the processing time ta is required to ensure the probability of occurrence of the same type of faults, gene to push down. In order to achieve the time lag between the computers For comparison and majority decision, the start signal is first at time ST Computer outputs are synchronized. This is only fed to one computer, the other two indicates that the computers are delayed by tsll or ts at every point at which a computer receives it. Has Comparison should take place, have to wait for each other. in Fig. 1 the first computer after the time ta a These waiting times are disadvantageous and the reason for the program section processed, so he must wait for that the control points within the programs until the later started second computer after the time at which a comparison and majority decision 50 ls / 2 and the third computer started later should be carried out, not so close together - after the time ts with their program sections finished can follow how there * are in the interest of safety. Only then can a period of tv would be desirable. Comparison and, if necessary, the majority decision It is the object of the invention to synchronize the. Only after switching one through as correct Computer outputs the necessary waiting times for the computer 55 recognized calculation results to ner to be eliminated and thus there would be a possibility at the time EA , the computer system is ready, manage to process calculation results in the next program section at much shorter intervals, to compare and carry out majority decisions. In the case of the multicomputer system according to the invention in The object of the invention is achieved by the start of the computer in FIG. 2 as in the state Characteristics of claim 1 specified 60 of the art. If a calculator after the time ta with Features solved. however, when a program section is finished, it waits This means that a separation between the pro-not, but rather outputs its result to an intermediate program run in the computer system and the test memory, and immediately begins processing for processing errors. The computers enter the next section of the program. The comparison of your results in the intermediate memory and 65 results as well as the switching through of a calculation as correct immediately without waiting for the result of the incorrect result on an output buffer AP equal and the majority decision. occurs only after all results or a multiple The comparison takes place if the results of a program section in the