SE7407750L - - Google Patents
Info
- Publication number
- SE7407750L SE7407750L SE7407750A SE7407750A SE7407750L SE 7407750 L SE7407750 L SE 7407750L SE 7407750 A SE7407750 A SE 7407750A SE 7407750 A SE7407750 A SE 7407750A SE 7407750 L SE7407750 L SE 7407750L
- Authority
- SE
- Sweden
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronizing For Television (AREA)
- Dc Digital Transmission (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2331601A DE2331601C2 (de) | 1973-06-20 | 1973-06-20 | Schaltungsanordnung zur phasenregelung eines Taktsignals |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| SE7407750L true SE7407750L (fi) | 1974-12-23 |
| SE388332B SE388332B (sv) | 1976-09-27 |
Family
ID=5884648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SE7407750A SE388332B (sv) | 1973-06-20 | 1974-06-12 | Anordning for faslegesreglering av en klockpulssignal |
Country Status (13)
| Country | Link |
|---|---|
| US (1) | US4012591A (fi) |
| AT (1) | AT338878B (fi) |
| BE (1) | BE816630A (fi) |
| CH (1) | CH571294A5 (fi) |
| DE (1) | DE2331601C2 (fi) |
| DK (1) | DK144549C (fi) |
| FI (1) | FI58240C (fi) |
| FR (1) | FR2234723B1 (fi) |
| GB (1) | GB1457309A (fi) |
| IT (1) | IT1014932B (fi) |
| NL (1) | NL7408148A (fi) |
| NO (1) | NO138790C (fi) |
| SE (1) | SE388332B (fi) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4191998A (en) * | 1978-03-29 | 1980-03-04 | Honeywell Inc. | Variable symmetry multiphase clock generator |
| DE3029249C2 (de) * | 1980-08-01 | 1984-11-15 | ANT Nachrichtentechnik GmbH, 7150 Backnang | Verfahren zur Synchronisation eines gestörten Empfangssignals mit dem zugehörigen Sendesignal sowie Schaltungsanordnung zur Durchführung dieses Verfahrens |
| GB8414517D0 (en) * | 1984-06-07 | 1984-07-11 | British Telecomm | Signal timing circuits |
| JP3403849B2 (ja) | 1995-03-17 | 2003-05-06 | 富士通株式会社 | 多重無線装置の受信部に設けられるクロック位相検出回路及びクロック再生回路 |
| US10187017B2 (en) * | 2017-01-07 | 2019-01-22 | Maxlinear, Inc. | Clocking scheme in nonlinear systems for distortion improvement |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL294442A (fi) * | 1963-06-21 | |||
| US3388330A (en) * | 1965-03-19 | 1968-06-11 | Bell Telephone Labor Inc | Partial response multilevel data system |
| US3560855A (en) * | 1968-06-07 | 1971-02-02 | Bell Telephone Labor Inc | Automatic equalizer utilizing error control information |
| JPS4840649B1 (fi) * | 1969-09-12 | 1973-12-01 | ||
| US3585298A (en) * | 1969-12-30 | 1971-06-15 | Ibm | Timing recovery circuit with two speed phase correction |
| US3633115A (en) * | 1970-04-22 | 1972-01-04 | Itt | Digital voltage controlled oscillator producing an output clock which follows the phase variation of an input clock |
-
1973
- 1973-06-20 DE DE2331601A patent/DE2331601C2/de not_active Expired
-
1974
- 1974-04-30 GB GB1882074A patent/GB1457309A/en not_active Expired
- 1974-05-08 AT AT379374A patent/AT338878B/de not_active IP Right Cessation
- 1974-05-21 CH CH696274A patent/CH571294A5/xx not_active IP Right Cessation
- 1974-05-23 FI FI1583/74A patent/FI58240C/fi active
- 1974-05-28 FR FR7418435A patent/FR2234723B1/fr not_active Expired
- 1974-06-11 IT IT23823/74A patent/IT1014932B/it active
- 1974-06-12 SE SE7407750A patent/SE388332B/xx unknown
- 1974-06-18 NL NL7408148A patent/NL7408148A/xx not_active Application Discontinuation
- 1974-06-18 US US05/480,564 patent/US4012591A/en not_active Expired - Lifetime
- 1974-06-19 NO NO742227A patent/NO138790C/no unknown
- 1974-06-19 DK DK328974A patent/DK144549C/da active
- 1974-06-20 BE BE145684A patent/BE816630A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| SE388332B (sv) | 1976-09-27 |
| DK328974A (fi) | 1975-03-17 |
| FR2234723B1 (fi) | 1978-04-21 |
| DK144549B (da) | 1982-03-22 |
| DE2331601B1 (de) | 1975-01-16 |
| NL7408148A (fi) | 1974-12-24 |
| CH571294A5 (fi) | 1975-12-31 |
| US4012591A (en) | 1977-03-15 |
| ATA379374A (de) | 1977-01-15 |
| IT1014932B (it) | 1977-04-30 |
| DK144549C (da) | 1982-09-06 |
| FI158374A (fi) | 1974-12-21 |
| NO138790C (no) | 1978-11-08 |
| NO138790B (no) | 1978-07-31 |
| DE2331601C2 (de) | 1975-08-21 |
| FI58240B (fi) | 1980-08-29 |
| FR2234723A1 (fi) | 1975-01-17 |
| FI58240C (fi) | 1980-12-10 |
| NO742227L (fi) | 1975-01-13 |
| BE816630A (fr) | 1974-12-20 |
| AT338878B (de) | 1977-09-26 |
| GB1457309A (en) | 1976-12-01 |