SE537314C2 - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
SE537314C2
SE537314C2 SE1150081A SE1150081A SE537314C2 SE 537314 C2 SE537314 C2 SE 537314C2 SE 1150081 A SE1150081 A SE 1150081A SE 1150081 A SE1150081 A SE 1150081A SE 537314 C2 SE537314 C2 SE 537314C2
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region
gate region
substrate
channel layer
semiconductor device
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SE1150081A
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Swedish (sv)
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SE1150081A1 (en
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Yuuichi Takeuchi
Rajesh Kumar Malhan
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Denso Corp
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Publication of SE1150081A1 publication Critical patent/SE1150081A1/en
Publication of SE537314C2 publication Critical patent/SE537314C2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02167—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • H01L29/8083—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H01L29/8128—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate with recessed gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Abstractln a JFET of a semiconductor device, a first conductivity type channel layer (2) is disposed on a main surface of a substrate (1 ) made of a semiconductor material. A first conductivity type source region (3a) and a first conductivity type drain region (3b), each having an impurity concentration higher than that of thechannel layer (2),~ are disposed in a surface layer portion of the channel layer (2) at positions spaced from each other. A second conductivity type gate region (4) is i disposed at a surface of the channel layer (2) and at a position between the i source region (3a) and the drain region (3b) and spaced from the source region(3a) and the drain region (3b). The gate region (4) includes an expanded portionhaving a width greater than a vvidth of a portion contacting the channel layer (2),and the expanded' portion is spaced from the surface of the channel layer (2). Agate electrode (5) is disposed on the gate region (4) and electrically connected to the gate region (4). A source electrode (6) is electrically connected to the source region (3a). A drain electrode (7) is electrically connected to the drain region (3b). '-32- _

Description

. ia1s_ V25 30“ SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAMEA i g Description The present invention relates to a semiconductor device having a JFET(junction field effect transistor) to be .suitably employed to a wide band-gapsemiconductor device, for example, a SiC semiconductor device using a siliconcarbide (herein-after, referred to as the SiC), and also relates to a method ofmanufacturing the same. i USP7560325 has proposed a JFET made of a SiC, which is adaptabie tohigh frequency and high voltage." Fig. 15 is a cross-sectional view of a normally-on JFET described inUSP7560325. As shown in Fig. 15, a pltype buffer layerJ2, a nltype* channel layer J3 and a n+~type source layer J4 are layered in theorder on a substrate J1 made of a SiC, and then a recess J5 is formedäto extendfrom a surface of the nïtype source layer J4 to the n'-_type channel layer J3 by etching. Further, a p*-type gate region J7 is formed in the recess J5, through a p'- r type layer J6. Also, a source electrode J9 and a drain electrode J10 are formed on the nïtype source layer J4 through metal layers J8, at locations respectively r spaced from the pïtype gate region J7. ln this way, 'the JFET is formed.ln the normally-on JFET described in USP7560325, the pïtype gate' region J7 is surrounded by the p'-type layer JG to avoid a highly doped p*n"junction at which a concentration is largely changed due to the pïtype gate regionJ7 beingdirectly in contact with the nïtype source layer J4. Therefore, acapacitance between the pïtype gate region J7 and the nïtype source layeriJ4,that is, a gate-source capacitance and a gate-drain capacitance, is large dueto large overlapped areas. As such, there.is a problem that implementation of a high frequency is limited. Furthermore, it is necessary to design so that the n'- \ type channel layer J3 becomes in a condition of pinch-'off by a depletion layer spreading from the pïtype layer J6, which has a low concentration. Therefore, there isalso a problem that a high voltage needs to be applied to the pïtype gate _1_ _10 so region J7 in turning off the JFET.
The present invention is made in view of the foregoing matter, and it is anobject of the present invention to provide a semiconductor device having a JFET, which is capable of reducing a gate-source capacitance and a gate-drain capacitance and capabie of restricting a gate applied voltage required for turning r”' Von the JFET from being a high voltage, and also a method of manufacturing thesemiconductor device. a i Ina semiconductor device according to a first aspect, a JFET includes a i - substrate, a .first conductivity type channel layer, a first conductivity type source region, a first conductivity type drain region, a second conductivity type/gate region, g a. gate electrode, a source electrode, and a drain electrode. The substrate is~ made ofta semiconductor material. The .channelÛlayer is made of a first conductivity type semiconductor material and is disposed on the main surface of the substrate by epitaxially growing. The source region and the drain region are, disposed in a surface layer portion of the channel layer at positions spaced fromeach other. The source region and the drain region each have an impurityconcentration higher than that of the channel layer. The gate region .is disposedat a surface of the channel layer and at a position between the source region andthe drain region and spaced from the source region and the drain region. The gate region includes anexpanded portion having a width greaterthan a width of a portion contacting the channel layer, and the expanded portion is spaced from the surface of the channel layer. The gate electrode is disposed on .the gate region and electrically connected to the gate region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. ln the structure, since the expanded portion of the gate region is spaced from the surface of the channel layer, the gate-source capacitance and the gate-t drain capacitance can be reduced.
Further, the gate region is formed directly at the surface of the channel 1 _2_ 1_O *15 i layer, and hence a pïtype impuritylayer having a concentration lower than that of the gate region is not necessary between the source region and the gate regionand between the drain region and the gate region. Therefore, a width of thedepletion layer extending in the channel layer can be controlled by the gate region,which has a high concentration and directly contacts the channel layer.Accordingly, it is less likely that the gate applied voltage will be a high voltage! ln a semiconductor device according to a second aspect, a recess is formed in the surface of the channel layer, and the gate region is disposed in the i recess.. ln the structure, since the gate region is disposed in the recess, a depletion layer spreads not only from a bottom surface of the recess but also from .side walls of the recess. Therefore,"an extent' of the depletionlayer can be further increased, as .compared _ with a case without forming the recess. i Accordingly, in turning off the JFET, the inside of the channel layer can be widely in a condition of pinch-off, and hence the device can further wšthstand a high voltage. ln a semiconductor device according to a thirdaspect, a JFET of a_ depletion mode (hereinafter, referred to as the D-mode) in which the gate region isdisposed directly on the surface of the .channel layer and a JFET of anenhancement mode (hereinafter, referredto as the E-mode) in which the gateregion 'is partly disposed in the recess of the channel layer are formed on the same substrate. ln this way, the semiconductor device can be constructed such that the D- I mode and the E-mode are formed on the same substrate. The semiconductor Adevicehaving such a structure is not like a CMOS in which an n-channel MOSFET and a p-channel MOSFET are combined. Therefore, channel mobility is equal between the elements of the D-mode and the E-rnode due to electron conduction i only. Since it is not necessary to adjust an area due to a difference of the channel mobility as the CMOS, the elements of the D-mode and the E-mode can have the same area. y-3- ln a semiconductor device according to a_ fourth aspect, the semiconductor material of the substrate is a wide band-gap semiconductor. ln a semiconductor device according to a fifth aspect, the substrate is a SiC substrate, and the gate region is made of a SiC having the same crystalstructure as the SiC substrate. ln a semiconductor device according, to a sixth aspect, the SiC substrate is an off-substrate that has a main surface defining an off angle equal to or less than ' 1 degree relative to a Sifface or a C-face towards the <11-20> or <1-100>direction, and the gate region is made of a SiC having the same crystal structureas the SiC substrate. ln this case, a surface of the expanded portion of the gateregion may have a (0001) facet. I í ln a semiconductor device according to a seventh aspect, the SiC I substrate is an on-substrate that has a main surface defining an a-face, and the gate region is made of a SiC having the same crystal structure as the SiC substrate. i ln this case, the surface of the gate region is a flat surface defining the i a-face. ln a semiconductor device according to an eighth aspect, the substrate isa SiC substrate, and the gate region is made so thatthe portion contacting thechannel layer has the same crystal structure as the SiC *substrate and theexpended portion has a crystal structure different from that of the SiC substrate atleast at a part thereof., ln a semiconductor device according to a ninth aspect, the SiC substrate i is an off-substrate having a main surface defining an off angle greater than 1 degree relative to a Si-face or a C-face towards the <11-20> or <1-100> direction, and the gate region is formed so that a (0001) facet is formed in the surface of the portion made of the SiC having the same crystal structure as the .SiC substrate, and the portion made of the SiC having the different crystal structure from the SiCsubstrate is cubic (3C) SiC and is formed on the (001) facet. iln a semiconductor device according to a tenth aspect, the SiC substrate is an on-substrate having a main surface defining a-face, and the gate region is-4_ ' ' .10.
V25 formed. such that the portion Contacting the channel layer takes over a crystalstructure ofthe SiC substrate in a vertical direction, and the expanded portion ismade of 3C-SiC. _ v ln a semiconductor device according to anv eleventh aspect, the SiCsubstrate is made of a semi-insulating SiC having a specific resistance of 1 x 1010to 1 x 1011 Q - cm. ln this case, a radio wave generated when the JFET is operated can beab_sorbed,_and hence the SiC semiconductor device is further adaptable to a highfrequency. i ln a semiconductor device according to a twelfth aspect, a second conductivity type buffer layer having an impurity concentration lower than that of i the gate region is disposed between the SiC substrate and the channel layer. ln this case, a radio wave generated when the JFET is operated can befurther absorbed, and hence the SiC semiconductor device is further adaptable toa high frequency. i ln a semiconductor device according to a thirteenth aspect, the bufferlayer is provided with a second conductivity type contact region having aconcentration higher than that of the buffer layer, and the source electrode isformed also in a recess passing through the source region so that the buffer iayerand' the source electrode are electricallyiconnected to each other through thecontact region. ln this case, the buffer layer electrically connected to the source electrodethrough the contact region enables a ground connection, and thus an electrical potential can be fixed at ground potential. ln a case of having the buffer layer, the SiC substrate can be either a first' conductivity type or a second conductivity type. Therefore, the SiC substrate canbe further easily prepared. i ln a method of manufacturing the semiconductor devicesaccording to thefirst to thirteenth aspects, a carbon mask having an opening at a position where the gate region is to be formed is arranged on the surface of the channel layer,_5_ i ' ' Ûso . and the gate region is epitaxially grown on the channel layer in a lateral directionup to a position above the carbon mask using the carbon mask as a mask to forman expanded portion having a width greater than a width of a portion contactingthe channel layer. Whenthe carbon mask is removed, the laterally grown portionof the gate region, that is, the expanded portion is spaced from the surface of thechannel layer. A ln this way, the gate region can be formed by selectively? epitaxially growing using the carbon mask. Further, by removing the carbon mask, the i expanded portion can be spaced from the surface of the channel layer. i For example, a recess is formed in the surface of the channel layer at theposition where the gate regionlis to be formed, and in epitaxially growing the gateregion, the gate region is formed in the recess. ln this way, the semiconductor device according to the second aspect ismanufactured by forming the gate region in the recess, which: has been previouslyformed. i i i To form the recess, for example, a resist is placed on the surface of thechannel layer, and the carbon mask is formed by carbonizing the resist. Anetching mask is placed on the carbon mask and then is patterned to form anopening at a position.where the gate, region tis to be formed. An opening is formed in the carbon mask at a position corresponding to where the gate region is to be formed using the etching mask. Then, the recess isformed by etching the t surface of the channel layer through the openings formed in the etching mask andthe carbon mask using the etching mask and the carbon mask as masks.After the etching mask is removed, the gate region is formed in the recess of the channel layer using the carbon mask. ln this way, the recess of the channel layer is formed, and the gate region formed in the recess.
For example, in a case where a SiC substrate made of an off-substratehaving a main surface defining an off angle equal to or tess than1 degree relativetoa Si-face or a C-face is used as the substrate, in epitaxially growing the gate region, a surface of the expanded portion is formed tohave a (0001) facet. ln this_6__ - 2:10 15? u 20 '25 r3o way, the semiconductor device according to the sixth aspect is manufactured.
For example, in a case where a SiC substrate made of an off-substratehaving a main surface defining an off angle larger than 1 degree relative to a Si-face or a C-face is used as the substrate, in epitaxially growing the gate region, asurface of the expanded portion is formed to have a (0001) facet, and 3C-SiC isgrown on. the (0001) facet in the lateral direction. ln this way, the semiconductordevice according to the ninth aspect is manufactured.
For example, in a-case where a SiC substrate made of an on-substrate 'having a main surface defining an a-face without defining an off angle is used as the substrate, in epitaxially growing the gate region, the expanded portion is made of 3C-SiC. ln this way, the semiconductordevice according to the tenth aspect is. manufactured.
Other objects, features and advantages of the present invention willbecome more apparent from the following detailed description made withreference to the accompanying drawings, in which the same or equivalent partsare designated by the same reference numerals and in which: 'Fig. 1 is a cross-sectional view of one cell of a SiC semiconductor deviceprovided with a JFET according to a first embodiment of the present invention; Figs. 2(a) to 2(d), 3(a) to 3(d) and 4(a) to 4(d) are cross-sectional views __ showing a process ofmanufacturing the SiC semiconductor device provided with “ the JFET shown in Fig. 1; Fig. 5 is a cross-sectional view of one cell of a SiC semiconductor device g provided with a JFET according to asecond embodiment of the present invention; Fig. 6 is a cross-sectional view of one cell of a SiC semiconductor deviceprovided with a JFET according to a third embodiment of the present invention;Fig. 7 is a cross-sectional view of one cell of a SiC semiconductor deviceprovided with a JFET according to a fourth embodiment of the present invention;i Fig. 8 is a cross-sectional view showing a growth of 3C-SiC on a surface of (0001) facet with regard to a gate region shown in Fig. 7;g _ -7- _ .
Fig. 9 is a cross-sectional view of one cell of a SiC semiconductor deviceprovided with a JFET according to a fifth embodiment of the present invention; - Fig. 10 is a cross-sectional viewof one cell of a SiC semiconductor deviceprovided with a JFET according to a sixth embodiment of the present invention; Fig. 11 is a cross-sectional view of one cell of a SiC semiconductor device provided with a JFET according to another example of the sixth embodiment; Fig. 12 is a cross-sectional view of one cell of a SiC semiconductor device' i 'provided with a JFET according to further another example of the sixth embodiment; Fig. 13 is a cross-sectional view showing a growth of 3C-SiC in a lateral direction of 4H-SiC with regard to a gate region shown in Fig. 12; Fig. 14- is a cross-sectional view of one cell of a SiC semiconductor deviceprovided with a JFET according to a seventh embodiment of the present invention;and i i Fig. 15 is a cross-sectional view of a SiC semiconductor device provided with a conventional JFET.
Hereinafter, embodiments of the present invention will be described withreference to the drawings". lt is noted that the same or equivalent parts in theembodiments are designated with the same reference numerals.
(First Embodiment) A first embodiment of the present invention will be described. Fig. 1 is across-sectional viewof one cell of a SiC semiconductor device provided with a JFET according to the present embodiment. Hereinafter, a structure of the JFET provided in the SiC semiconductor device will be described with reference to Fig. 1.
The SiC semiconductor device shown in Fig. 1 is formed using a semi-insulating SiC substrate 1. 'A »semi-insulating property means a property having aspecific resistance (or a specific electric conductivity) similar to that-of an electrical insulating material, and* is provided by a non-doped semiconductor material or the like despite of the semiconductor material. For example, in the present " _3_ - 2.0 embodiment, as the semi-insulating SiC substrate 1, an off-substrate made of 4H- SiC and having a main surface defining an off angle equal to or lower than 1 degree relative to a (0001) Si face or a (000-1) C face is used. The off-substrate 1 has a specific resistance of 1 x 101° to 1 x 1011 Q - cm, and. has a thickness of50to 400 pm (e.g., 350 pm).
An n'-type channel layer 2 is formed on the surface of the SiC substrate 1.
The nïtype channel layer 2 provides a place where channel regions are formed.
-For example, the nïtype channel layer 2 has a nïtype impurityconcentration of 1 x 1016 cm'3 to 1 x 1018 cm'3 (e.g., 1 x 1017 cm'3), and has a thickness of 0.1 pm to i 1.0 pm (e.g., 0.2 pm).
An nïtype layer 3 is formed in a surface layer portion of the n'-typechannel layer 2. The nïtype layer 3 includes regions separated in a lateraldirection, such as a right and left direction in Fig. 1, in each cell. One of the regions, such as aleft region in Fig. 1, constitutes an nïtype source region 3a, and the other, such as a right region in Fig. 1, constitutes a nT-type drain region 3b.
The nïtype source region 3a and the nT-type drain region 3b each have an n-type impurity concentration of 5 x 1018 cm'3 to 1 x 10211 cm'3 (e.g., 2x 1019 cm'3) and a 1 thickness of10.1 pm to 1.0 pm (e.g., 0.2 pm).
A recess 2a is formed atthe surface of the nïtype channel layer 2, i between the nT-type source region 3a and the nïtype drain region 3b. Therecess 2a has a depth smaller than the thickness of the n'-type channel layer 2.Because a portion deeper than the recess» 2a in the nïtype channel layer 2, that is,a portion under the recess 2a serves asa channel region, a channel depth isdefined byadepth DG of the recess 2a. For example, the depth DG of the recess2a is 0.1 pm. 1 1 A pf-type gate region 4 is formed at the surface of the nïtype channel .layer 2, within the recess 2a. A width of the pïtype gate region 4 is made larger at a position separated from the surface of the nïtype channel layer 2 by a predetermined distance, such as 0.5 pm to 1.0 pm, than a portion formed inside the recess 2a. That is, the pT-type gate region 4 includes an expanded portion _9_ 025 having a width greater than a width of a portion Contacting the rf-type channellayer 2, at a position spaced from the surface of the nïtype channel layer 2. Thus,the pïtype gate region 4 has a typically T-shape. A SiC does not exist betweenthe expanded portion of the T-shaped pïtype gate region 4 and the surface of thenltype channel layer 2. I I The pf-type gate region 4 has ap-type impurity concentration of 5 x 1018 cm'3 to 5 x 1019 cm'3 (e.g., 1 x 1019 c_m'3) and a thickness of 0.1 um to 1.0 um (e.g., 0.4 um). lt is preferably thatthe pf-type gate region 4 typically has a flat surface.However, in a case where the main surface of the SiC substrate 1_ has the aforementioned plain orientation, a facet may be formed at an end of the surface of the pf-type gate region 4.
A location and a dimension of the pïtype gate region 4 are determinedbased on the following facts. Specifically, in the pïtype gate region 4, a length ofa portion Contacting the n'-type channel layer 2, that is, a channel length Lgh defines a cutoff frequency of the JFET. The shorter the channel length LQ, is, the V higher the cutoff frequency is. Therefore, in the present embodiment, the channel length Lgh is 0.1 um to 0.5 um (e.g., .0.4 um). A gate-source length LSG betweena gate and a source relates to a current value of the JFET. lt is necessary toreduce the length LSG so as to further increase an electriccurrent. 'Therefore, inthe present embodiment, the length LSG is, for example, 0.1 um to 0.5 um.Further, a gate-drain length LGD -betvveen the gate and a drain' relates to Voltage withstand of the JFET. The larger the gate-drain length LGD is, the more the _» JFET withstands a high voltage. Therefore, in the present embodiment, the gate- drain-length LGD is, for example, 0.5 um to 1.0 um.
A gate electrode 5 is formed on the surface of the pT-typegate region 4.
The gate electrode 5 is constructed of a multi-layer structure of multiple metal layers. For example, the gate electrode 5 is made by sequentiaily forming a first layer 5a, a second layer 5b and an Au layer or a Al wiring. The first layer Sa is a , constructed of a Ni base metal layer, such as NiSig, and is joined to the pïtype gate region 4 by an ohmic contact. The second layer 5b is constructed of a Ti_10- 25 “ '30 base metal layer. Although not illustrated, the Au layer or the Al wiring is formed _ considering an electrical connection with an external part. The first layer 5a has a thickness of 0.1 pmto 0.5 pm (e.g., 0.2 pm). The .second layer 5b has a thickness of 0.1 pm to 0.5 pm (e.g., 0.1 pm). The Al wiring or the Au layer has athickness of 1.0 pm to 5.0 pm (e.g., 3.0 pm). i i v ii A source electrode 6 is formed above the nïtypesource region 3a. A.drain electrode 7 is formed above the nïtype drain region? 3b. The sourceelectrode 6 and the drain electrode 7 are, for example, made of the samematerials as the gate electrode 5. The source electrode 6 and the drain electrode7 have Ni base metal layers 6a, 7a and Ti base metal layers 6b, 7b. Ii The JFET is constructed of theaforementioned structure. Although notillustrated, the ASIC semiconductor device of the I present embodiment is constructed by electrically insulating the electrodes from each other by interlayer 'dielectric films or protective films, which are formed of silicon oxide films or silicon nnride films. ln the JFET of the SlC semiconductor device constructed in the abovemanner, if a gate voltage is not applied to the gate electrode 5, thewnf-type channellayer 2 is in a condition of pinch-off by a depletion layer extending from the pT-typegate region 4 toward the nltype channel layer 2 (and a depletion layer extendingfrom the SiC substrate to the nltype channel layer 2). lf the gate voltage is applied to the gate electrode 5 in this condition, the depletion layer extending from _ the pïtype gate region 4 is reduced. Thus, the channel region is formed in the n' -type channel layer 2 and hence an electric current occurs between the sourceelectrode 6 and the drain electrode 7 through the channel region. ln this way, theJFET of the present embodiment can serve as a normally-off type element. ln this JFET, the pïtype gate region 4 is configured that the width of theportion contacting the nïtype channel layer 2 is small while the width of thesurface is large so as, to ease arrangement of the gate electrode 5. .With thisconfiguration, the following advantages are achieved. i (1) The expanded portion of the pïtype gate region 4 is spaced from theÅ _ _11-. .10 , surface of the nltype channel layer 2. Therefore, av gate-source capacitance anda gate-drain capacitance can be reduced.
Also, since the pïtype gate region 4 is formed directly at the surface of then'-type channel layer 2, a p'-type layer having a concentration lower than that ofthe pïtype gate region 4 is not required between the nïtype layer 3 and the p*-type gate region 4. Therefore, a width of the depletion layer extending in the n'-type channel layer 2 can be controlled by the pïtype gate region 4, which has ahigher concentration and directly in contact with the nïtype channel layer 2.
Accordingly, the gate applied voltage is restricted from being a high voltage, as i compared with a case where the pïtype layer is additionally providedflbetween the nïtype layer 3 and the pïtype gate region 4. Further, because such a" structureenables high-speed switching in the JFET, the SiC semiconductor device is further adaptable to high frequency. '(2) As described in the above, the channel length Lgh adjusts the cutoff - frequency of the JFET. The shorter the channel length Lch is, the higher thecutoff frequency is. Further, the gate-source length LSG relates to the value of the electric current of the JFET. lt 'is necessary to reduce the length LSG so as to I increase the electric current. Furthermore, the gate-dra_in iength LGD relates to the voltage withstand of the JFET. The larger the gate-drain length LGD is, the i - more the JFET withstands a high voltage. Therefore, the reduction of the width of the portion of the p* -type gate region 4, which contacts the nltype channel layer 2,as *mush as possible is advantageous to achieve a high cutoff frequency, a largeelectric current and high voltage withstand. V However, if the pïtypegate region 4 is merely reduced in width, it isdifficult to arrange the gate electrode 5 on the surface of the pïtype gate region 4.Therefore, the pïtype gate region 4 is formed so that the width of _the portion Contacting the n'-type channel layer is small while the width of the surface of the _p“'-type gate region 4 is large. With thisfformation, the arrangement of the gate electrode 5 is eased while achieving the high cutoff frequency, the large electric current and the high voltage withstand. yi _12- 150 (3), The recess 2a having the depth DG is formed in the nïtype channellayer 2, and a base portion of the pïtype gate region 4 is disposed in the recess2a. Therefore, because the depletion layer expands not only from the bottomsurface of the recess 2a but also from the side walls of the recess 2a, theexpansion of the depletion layer can be further increased, as compared with acase without forming the recess 2a. Accordingly, when the JFET 'is turned off, the nïtype channel layer 2 can be more widely in condition of pinch-off.
I _ Therefore, the JFET can further withstand a high voltage. v(4) Since the SiC substrate is made of the semi-insulating material, a , radio wave occurring when the JFET is operated can. be absorbed. Therefore, the SiC semiconductordevice is further adaptable to a highfrequency.Next, a method of manufacturing theSiC semiconductor device having theJFET with the aforementioned structure will be described. Figs.i2(a) through 4(d)are cross-sectional views showing a process of manufacturing the SiCsemiconductor device having the JFET shown in VFig. Referring to thesedrawings, the method of manufacturing the semiconductor device having the JFETshown in Fig. 1 will be described.I First, as shown in Fig. 2(a), the semi-insulating SiC substrate 1 is prepared. The semi-insulating SiC substrate 1 is made of an off-substrate that has a main surface defining an off angle equal to or less than 1 degree relative to » a (0001) Si-face or a (000-1) C-face.Next, as. shown in Fig. 2(b), the n'-type channel layer 2 is formed on the main surface of the SiC substrate 1 by epitaxially growing. For example, the n'- type channel layer 2 has the n-type impurity concentration of 1 x 1016 cm'3' to 1 x1018 cmfa (e.g., 1 x 10” cm-à), 'and the thickness of 0.1 pm to 1.0 um (e.g., 0.2 um). ln,a step shown in Fig. 2(c), a non-illustrated mask made of LTO or the ' iike is placeduon the surface of the nïtype channel layer 2, and then the mask is patterned to form openings at positions corresponding to where the nïtype source region 3a and the nïtype drain region 3b are to be formed. Then, the n-type impurity is ion-implanted to form the nïtype source region 3a' and the nïtype draini _13- i _10 20' 25~ region 3b each having the n-type impurity concentration of 5 x 1018 cm'3 to 1 x 10211cm'3 (e.g., 2 x 1019 cm'3) and the thickness of 0.1 pm to 1.0 pm (e.g., 0.4 pm).The mask is then removed. _ 1 ln a step shown in Fig. 2(d), a resist 10 is deposited on the surfaces of thenïtype channel layer 2, the nïtype source region 3a and the nïtype drain region.3b. As the resist 10, an organic solvent in which materials other than organicmaterials are carbonized as the organic materials are evaporated can be used.For example, a positive-type organic solvent, such as an i-line photolithography resist, a Deep-UV lithography resist, an ArF lithography resist, or an electric beam 1* lithography resist, can be used.
Further, in a step shown-in Fig. 3(a), the resist 10 is carbonized, such as by thermal treatment at 750 degrees Celsius in argon atmosphere, to form a' carbon mask 11. ln a step shown in Fig. 3(b), an etching mask 12 made of a silicon oxidefilm or the like is placed on the surface of the carbon mask 11. ln a step shown in Fig. 3(c), a resist 13 for patterning is formed on the surface of the etching mask 12. Then, the resist 13 is patterned-by photolithography to forman opening at a position corresponding to where the , recess 2a is to be formed.
Next, in a step shown in Fig. 3(d), the etching mask 12 is patterned by BHF or the like using the resist 12, and then the resist 13 is removed. Thereafter,the carbon mask 11 is patterned by an 012 plasma technique or the like using theetching mask 12 as a mask. 1 ln a step shown in Fig. 4(a), the surface of the nïtype channel layer 2 ispartially etched by a CF4 plasma technique or the like using the etching mask 12and the carbon mask 11 as the masks to form the recess 2a. ln a step shown in Fig. 4(b), the etching mask 12 is removed, and then thepïtype gate region 4 is formed in the recess 2a by selectively epitaxially growingusing the carbon mask 11 covering the surface of the SiC. The p1-type gate region 4 is formed to have the impurity concentration of 5 x 1018 cm'3 to 5 x 1019-14_ 1.125 cm'3 (e.g., 1 x 1019 cmß) and the thickness of 0.1 um to 1.0 um (e.g., 0.4pm). ln this case, the pïtype gate region 4 is formed inside of the recess 2a, and is further formed on the surface of the carbon mask 11 by continuously performingtheepitaxial-growing.Since the pïtype gatefregion 4 is formed by the epitaxial growth relative to the :SiC substrate 1, which is made of the off-substrate having the off angle relative to the (0001) Si-face or the (000-1)C-face, a facet with a (0001) face may be partly “ made on the surface of the pïtype gate region 4. Thus, the surface of the p*- 1 type gate region 4 may not be flat. ln fact, it is preferabie that the surface of the pïtype gate region 4 istypically a flat surface in order to ease the arrangement of the gate electrode 5thereon. However, in a case where the main surface of the SiC substrate 1 hasthe aforementioned plain orientation, a facet is formed at an end of the surface of the .pïtype gate region 4. ln such a case, it may be slightly difficult to arrange the gate electrode 5 on the surface of the pïtype gate region 4, as compared with a case of arranging the gate electrode 5 on the 'entirely flat surface. ln the presentembodiment, since the surface of the gate electrode 4 is expanded by forming theexpanded portion, the gate electrode 5 can be formed without difficulty. ln a step shown in Fig. 4(c), the carbon mask 11 is removed. Thus, :because the carbon mask 11 under the expanded portion of the pïtype gate region 4 is also removed, the T-shaped pïtype gate region4 is formed.
Thereafter, in a step shown in Fig. 4(d), a non-illustrated mask made of a metal mask, a silicon oxide film or the like is placed to cover a region other than . the regions where the gate electrode 15, the source electrode 6 and the drain electrode 7 are to be formed. iThen, the Ni-based metallayers and the Ti-based metal layers, respectively, constituting the first layers 5a, 6a, 7a and the second, layers 5b, 6b, 7b of the gate electrode 5, the source electrode 6 and the drainelectrode 7 are deposited. When the mask is then removed, the first layers 5a, 6a, 6a and the second layers 5b, 6b, 7b remain by lift-off at the regions where the gate electrode 5, the source electrode 6 and the drain electrode 7 are to be formed. _15_ Further, as necessary to reduce resistance, the first layers-Sa, 6a, 7aw ofthe gate electrode 5, the source electrode 6 and the drain electrode 7 can bethermally treated into a silicide, such Was into NiSig. Thereafter, non-illustratedinterlayer insulating films, protecting films or the like are formed. Accordingly, theSiC semiconductor device having the JFET shown in Fig. 11 can be manufactured.
(Second embodiment) A second embodiment of the present invention will be described. A SiC ~ semiconductor device according to the present embodiment has a p"-type buffer layer in addition to the structure of the first embodiment. Other structures are i similar to those of the first embodiment, and thus a different structure will be mainly described.
Fig. 5 is a cross-sectional view of the SiC semiconductor device having a JFET according to the present embodiment, As shown in Fig. 5, in the present embodiment, a pïtype buffer layer8 having an impurity concentration lower than that of the pïtype gate region 4 is formed on the surface of the SiC substrate 1.
The n'-type channel layer 2 is formed on the surface of the pltype buffer “ layer 8. The p'-type buffer layer 8 is provided to further withstand a high voltage." The p'-type buffer layer 8 has an impurity concentration of 1 x 1016 cm'3 to 1 x 1011cm'3 (e.g., 1 x 1016 cm'3) and a thickness of 0.2 pm to 2.0 pm (e.g., 0.4 pm).
The p'-type buffer layer 8' is provided with a pïtype contact region 8ahaving a high impurity concentration. A recess 9 is formed under the sourceelectrode 6. The recess 9 passes through the nïtype source region 3a to exposethe pT-type contact region 8a. The source electrode 6 is embedded in the .recess9 so that thep-type buffer layer 8 is connected to the source electrode 6 through the pïtype contact region 8a to be fixed at ground potential.
Also in such a structure, the similar advantages to the first embodimrents can be achieved. Further, the pïtype buffer layer 8 is formed in addition to the structure of the first embodiment, the JFET can further withstand a high voltage, as compared with the first embodiment. Moreover, since the pïtype buffer layer , 8Üis provided, the radio wave occurring when the JFET is operated can be' -16- absorbed" also .by the pïtype bufferlayer 8. Therefore; theiSiC semiconductordevice is further adaptable to a high frequency. ln the case of having the p'-typebuffer layer 8, the SiC substrate 1 can be either n-type or p-type. Therefore, theSiC substrate 1 can be further easily prepared.
The SiC semiconductor device having such a structure canbe typicallymanufactured by the similar method to the SiC semiconductor device of the firstembodiment. However, differently from the first embodiment, since the structurehas the p"-type buffer layer 8, a step of forming the pïtype buffer layer 8 on thesurface of the SiC substrate 1, a step of forming a pïtype contact region 8a by an ion implantation, and astep of etching the n'-type channel layer 2 to form the “ recess 9 before the step of forming the resist 10 need to be performed.
(Third embodiment)A third embodiment of the present invention will be described. ln a SiC semiconductor device of the present embodiment, the pïtype gate region 4 is formed without forming the recess 2a in the structure, of the first embodiment. _ Other structures are similar to those of 'the first embodiment, and a different . structure will be mainly described.
Fig. 6 is a cross-sectional view of the SiC semiconductor device having aJFET according to the present embodiment. i As shown in Fig. 6, in the. presentembodiment, the pïtype gate region 4 is directly formed on an outermost surfaceof the nf-type channel layer 2. Also in such a structure, the advantages similar tothe first embodi.ment can be achieved. However, since the recess 2a is» not formed,the depletion layer from the pïtype gate region 4 does not expand - through the side walls of the recess 2a, as compared with the structure of the first embodiment. Therefore, the expansion of the depletion layer is slightly reduced,as compared with the structure of the first embodiment in which the recess 2a is formed. lt is said that the structure of the first embodiment is advantageous in i vievv of the improvement of the voltage vvithstand.
Such a SiC semiconductor device can be manufactured in the similar manner to the SiC semiconductor device of the first embodiment. However,' -17-f differently from the first embodiment, it is not necessary to form the recess 2a.
Therefore, it is not necessary to place the etching mask 12 on the carbon (mask 11.
Also, it is not necessary to perform the etching step using the etching mask 12 for forming the recess 2a.(Fourth embodiment) y_A fourth embodiment of the present invention will be described. ln a SiC semiconductor device of the present embodiment, the off angle of the SiC substrate 1'is differentiated from that of the SiC substrate 1 of the first embodiment.
Other structures are similar to those of the first embodiment, and a differentstructure will be mainly described. iFig. 7 is a cross-sectional view of the SiC semiconductor device having aJFET according to the present embodiment. ln the present embodiment, the offangle of the SiC substrate 1 is larger than 1 degree and is, for example, 4 or 8degree. ySince the JFET is made using such "a SiC substrate, as shown in Fig. 7,the pïtype gate region 4 is made of 4H-SiC and 3Cz-SiC. i i~ lf the off angle of the SiC substrate 1 is increased, 3C-SiC can be grownon the surface of the (0001) facet depending on a condition of the epitaxial growthin forming the pïtype gate region 4. Fig. 8 is an enlarged cross-sectional viewfor showing such a situation. s iAs shown in Fig. 8, the nïtype channel layer 2 is formed on the surface of the SiC substrate 1, which is made. of the 4H-SiC off-substrate, to take over a crystal structure of the SiC substrate 1, and the pïtype gate region 4 is 'formed on i the surface of the nïtype channel layer 2. ln this case, the pïtype gate region 4is formed in a pattern of hexagon that inclines in the off direction, instead of acircular pattern, due to the anisotropy oftransverse direction growth and theinfluence of step flow growth. Thus, although the (0001) facet is formed, sincethe off angle is large, 3C-SiC is formedon the (0001) facet.
Also in such a structure, the similar advantages to the first embodimentcan be achieved. v Further, when the 3C-SiC is formed on the (0001) facet as in the present embodiment, the entire surface of the pïtype gate region 4 can be_13- ' formed almost flat, Therefore, the gate electrode 5 can be more easily formed on the surface of the pïtype gate region 4. The SiC semiconductor device having V such a structure can be manufactured by the similar manufacturing method to the SiC semiconductor device of the first embodiment, except using the SiC substrate t t having the off angle of equal to or greater than 1 degree.lf a PN junction is formed by 4H-SiC and 3C-Si, which have different crystal structures, a leak current occurs. However, in a case where the crystal structures differ in the same pïtype gate region 4, a leak current will not occur and no significant problem will arise. On the contrary, in the 3C-SiC, an impuritydoping level during the epitaxial growth can be increased, ascompared with the 4H-ASiC or the like. Therefore, an internal resistance of the pïtype gate region 4 can be reduced. - (Fifth embodiment) A fifth embodiment of the present invention will be described. A SiC semiconductor device of the present embodiment is provided by (a combination of i elements having the 'JFET structures of thefirst and third embodiments, which are operated in a D-mode and an E-mode. Other structures are similar to the first and third. embodiments, and structures different from the first and third" embodiments will be mainly described. 'Fig. 9 is a cross-sectional view of the SiC semiconductor device having a JFET according to the present embodiment. As shown in Fig. 9, in the SiC semiconductor device according to the present embodiment, JFETs having different structures are formed in the same substrate, one (on a right side in Fig. 9)having the JFET structure of the first embodiment and the other (on a left side inFig. 9) having the JFET structure of the third embodiment. ln the SiC semiconductor device constructed as above, the JFET on the left side in Fig. 9 operates as an element of a depletion mode (normally-on type; . hereinafter; referred to as the D-mode), and the JFET on the right side in Fig. 9operates as an element of an enhancement mode (normally-off type, hereinafter referred to as the E-mode)._19- _ '30 Specifically, in the JFET operating as the Dit-mode, even when the gatevoltage is not being applied to the gate electrode 5, the n'-type channel layer 2 isnot in entirely pinch-off condition by the depletion layer extending from the pïtype gate region 4 toward the n'-type channel layer 2 (and the depletion layer extending from the SiC substrate 1 toward the nf-type channel layer 2), and thus is under a i condition where the channel region is formed.
Therefore, when the gate vo|tage is not applied to the gate electrode 5, an i electric current passes between the source electrode 6 and the drain electrode 7 through the channel region. When a negative gate voltage is applied to the gateelectrode 5, the expansion of the depletion layer increases. Thus, the channel region in the layer disappears, and the electric current does not pass between the 'source electrode 6 and the drain electrode 7. ln this way, the JFET -of the D- i mode serves as the normally-on type element. i On the other hand, in the JFET operating as the E-mode, when the gatevoltage is not being applied to the gate electrode 5, the n'-type channel layer 2 isentirely in condition of pinch-off due to the depletion layer extending from the p*- type gate region 4 toward the rf-type channel layer 2 (and the depletion layer extending from the SiC substrate 1 toward the nïtype channel layer 2). When a . positive gate voltage is applied to the gateelectrode 5 in such a condition, thedepletion layer extending from the pïtype gate region 4 is reduced; i vThus, the channel region is formed in the nïtype channel layer* 2, andhence the electric current passes between the source electrode 6 and the drainelectrode 7 through the channel region. ln this way, the JFET of the E-mode serves as the normally-off type element.
Accordingly, the D-mode and the E-mode can be formed on the same " substrate in the SiC semiconductor device. The SiC semiconductor devicehaving the aforementioned structure is different from a structure in which an n-channel MOSFET and a p-channel MOSFET are combined as a CMOS, thechannel mobility is equal between the elements of the D-mode and the E-mode due to electron conduction only. Therefore, it is not necessary to adjust anvareai _20- i as the CMOS due to the difference of the channel mobilities, and thus theelements of the D-mode and, the E-mode can have the same area.
The SiC semiconductor device having such a structure can be manufactured by the similar manufacturing method to the first embodiment. .
However, with regard to the JFET of the D-mode, since the recess 2a is not formed, the etchingv step for forming the recess 2a is performed after the carbon mask 11 is patterned and a mask for covering the JFET of the D-mode is piaced.(Sixth embodiment)A sixth embodiment of the present invention will be described. ln a SiCsemiconductor device of the present embodiment, the SiC substrate 1 is an on- substrate without having an off angle, in place of the off-substrate »of the SiC semiconductor device of the first embodiment. _ Other structures are similar to those of the first embodiment, and a different structure will be mainly described.
Fig. 10 is a cross-sectional view of the SiC semiconductor device having a JFET according to the present embodiment. ln the present embodiment, as the SiC substrate 1, the on-substrate without having an off angle, such as an a-facesubstrate, is used. i Therefore, as shown in Fig. 10, the surface of the pïtype gateregion 4 is a flat surface defining the a-face without forming a facet. ln this way, the on-substrate can be employed as the SiC substrate 1, inplace of the off-substrate. ln such a case, the surface of the pïtype gate region 4can be a flat surface without forming a facet. The SiC semiconductor device canbe manufactured by thesimilar manufacturing method to the SiC semiconductordevice of the first embodiment, except for using the on-substrate having the a-faceas the SiC substrate 1.
Also in a case where the on-substrate is used as the present embodiment,the pïtype buffer layer 8 can be formed. e Fig.. 11 is a cross-sectional view of theSiC semiconductor device in a case where the pïtype buffer layer 8 is formed.
As shown in Fig. 11, the p'-type buffer layer 8 having an impurityconcentration lower than that of the pïtype gate region 4 is formed on the surface of the SiC substrate 1, and the n'-type channel layer 2 is formed on the surface ofI . _21- _ 10* the p'-type buffer layer 8. Also, the pïtype buffer layer 8 is provided with the p*- type contact region 8a having a high impurity concentration. The pïtype contact _ region 8a is connected to the source electrode 6 through the recess 9, which passes through the nïtype source region 3a under the source electrode 6, to befixed at ground potential._ ln this way, also in the structure of the present embodiment, the p'-type buffer layer 8 can be formed, similar to the second embodiment. Thus, the SiC i semiconductor device further withstands a high Voltage. Moreover, since the p'- type buffer layer 8 is formed, a radio wave generated when, the JFET is operated is absorbed. “Therefore, the SiC semiconductor device is further adaptable to “ high frequency. ln the case where the on-substrate having the a-face isused as the SiCsubstrate 1, the pïtype gate region 4 can be constructed to include different crystal structures. Fšg.i12 is a cross-sectional view of the SiC semiconductor , device having a JFET in a casewhere the pf-type gate region 4 is constructed of different crystal structures.
As shown in Fig. 12, in the pïtype gate region 4, a portion formed directlyabove the recess 2a is made of 4H-SiC, and expanded portions (flanged portions)at which the width of the pïtype gate region 4 is increased are made of 3C-SiC. ln a case where the SiC substrate 1 is the on-substrate having the a-face,the 3C-SiC can be grown in a lateral direction of the 4H-SiC depending on anepitaxial growth condition in forming the pïtype gate region 4. Fig. 13 is anenlarged view showing the situation.
As shown in Fig. 13, the portion contacting the n'-type channel layer 2takes over the crystal structure of the base in a vertical direction, and thus theportion contacting the nïtype channel layer 2 has the crystal structure of 4H-SiC.However, with regard to a lateral growth in the lateral direction of the 4H-SiC, 3C-SiC is grown along a <0001> direction due to anisotoropy of the lateral growth. lnthis way, the pïtype gate region 4 can be constructed of the different crystal structures.,-22- V10 2,5 As described in the above, in the case of the 3C-SiC, the impurity dopinglevel during theepitaxial growing can be increased, as comparediwith the 4H-SiC or the like. Therefore, the internal resistance of the pïtype gate region 4 can be I i reduced.
(Seventh embodiment) A seventh embodiment of the present invention will be described. ln a 5 SiC semiconductor device according to the present embodiment, the pïtype gate region 4 is formed without forming the recess 2a in a similar manner to the third embodiment, in the structure of the sixth embodiment. Other structures are similar to the sixth embodiment, and a structure different from the sixth” embodiment will be mainly described. i Fig. 14 is a cross-sectional view of the SiC semiconductor devicehaving a JFET according to the present embodiment. As shown in Fig. 14, in the present' embodiment, the pïtype gate region 4 is formed directly on the 'outermost surface - of the nïtype channel layer 2. ln this way,_also in a case where the on-substrate is used as the SiC substrate 1 in place of the off-substrate, the pïtypeflgate region 4 can be formed without 'forming the recess 2a. Also in such a structure, the' -advantagessimilar to the sixth embodiment can be achieved.
(Other embodiments) The structure having the pïtype buffer layer 8 is not limited to the SiCsemiconductor devices described in the second and sixth embodiments, but canbe employed to the SiC semiconductor devices of the third to fifth embodimentsand the seventh embodiment. Also in such a case, the p'-type buffer layer 8 is electrically connected to the source electrode 6 through the pïtype contact region 8a and the recess 9, and hence connected to the ground potential.
The n-type channel JFET, which has the nïtype channe|-- layer 2 as thechannel, is exemplified in each of the above embodiments. Alternatively, thepresent invention can be employed to a p-type channel JFET by reversing the n- type and the t-type in each of the above embodiments. i The SiC substrate 1 is made of 4H-SiC in each of the above embodiments. _23- Alternativeiy, the SiC substrate 1 can be made of any other Crystal Structures,such as 6H-SiC. ln the above description, the pïtype gate region 4 is formed to have the same crystal structure as the base by taking over the crystal structure of the SiC substrate 1 (the ni-type channel layer 2). Alternativeiy, the epitaxial - growth condition can be adjusted so that the pïtype gate region 4 has a different crystal structure' from that of the SiC substrate 1. For example, the pïtype gate _ region 4 made of 3C-SiC can be formed above the SiC substrate 1 (the nf-typechannel layer 2) made of 6H-SiC. ln such a case, the impurity doping level of thepïtype gate region 4 can be increased, and hence the resistance of the pïtypegate region 4 can be reduced. i Each of the gate electrode 5, the source electrode 6 and the drainelectrode 7 is constructed of three layer structures, which are exemplarily made ofmetal layers including the Ni-base metal layer, the Ti-base metal layer and Al- or Au-base metal layer. However, the structure is only an example. For example, each of the gate electrode 5, the source electrode 6 and the drain electrode 7 can ' be constructed of a multi layer structure, such as Ni/Ti/Mo/Au, Ti/Mo/Ni/Au,Ni/Mo/T i, Ti/Mo/Ni, TilMo, .Ni/Mo, each of which layered in this order from the v bottom, or of a single layer structure only by ,Ti or Ni. The first layer 5a, 6a, 7a is silicided into the metal silicide. Alternativeiy, the first layer 5a,_6a, 7a can-be carbided into a metal carbide so as to reduce the resistance. ln both cases, since '. .the portion contacting the pïtype gate region 4 isthe metal silicide or the metal carbide, a contact portion between the first layer 5a and the pïtype gate region 4can be silicided or carbided ina self-alignment manner.
V ln the above embodiments, the, SiC semiconductor device are exemplifiedas the semiconductor device. However, the present invention can be employedto a semiconductor device using Si. Further, .the present invention can 'beemployed to any other wide-band gap semiconductor devices, such as asemiconductor device using GaN, diamond, AlN, or the like.
Additional advantages and modifications will readily occur to those skilled in the art. The invention in its broader- term is therefore not limited to _24- the specific details, representative apparatus, and illustrative examples shownand described. lt is noted that, in representing a crystal orientation, although a bar (-)should be attached above a desired number, the bar is attached before thedesired number in this specification because there is a limitation on the expression due to the application by a personal computer. _25_

Claims (19)

1. WHAT IS CLAIMED IS:(1. A semiconductor device having a junction field effect transistor comprising:a substrate (1) made of a semiconductor material and having a mainsurface;a first conductivity type channel layer (2) made of a first conductivity typesemiconductor material and disposed on the main surface of the substrate (1) by epitaxially growing; a first conductivity type source region (3a) and a first conductivity type i drain region (3b) disposed in a surface layer portion of the channel layer (2) at positions spaced from each other, and each having an impulrity concentrationhigher than that of the channel layer (2); a second conductivity type gate region (4) disposed at a surface of the fichannel layer (2) andlat a' position between the source region (3a) and the drain t region (3b) and spaced from the source region (3a) and the drain region (3b), the gate region (4) including an expanded portion having a width greater than a 'width [of a portion contacting the channel layer (2), the expanded portion being spaced from the surface of the channel layer'(2);i a gate electrode (5) disposed on the gate region (4) and electricallyconnected to the gate region (4); i ia source electrode (6) electrically connected to the source region (3a); and a drain electrode (7) electrically connected to the drain region (3b).
2. The semiconductor device according to claim 1, wherein a recess (2a) isformed at the surface of the channel layer (2), and the gate region (4) is disposed in the recess (2a).
3. The semiconductor device according to claim 2, wherein the junction field effect transistor in which the gate region (4) is disposed inthe recess (2a) constitutes a junction field effect transistor of an enhancement mode, the semiconductor device further having a junction field effect transistor of ai -26-i depletion mode in which the gate region (4) is disposed directly on the surface ofthe channel layer (2), whereinthe junction field effect transistor of the enhancement mode and the junction field effect transistor of the depletion mode share the substrate (1).
4. The semiconductor device according to any one of claims 1 to 3, wherein the semiconductor material includes a wide-band gap semiconductor.
5. The semiconductor device according to claim 4, whereinthe wide-band gap semiconductor is a silicon carbide, the substrate (1) is a silicon carbide substrate, and the gate region (4) is made of a silicon carbide having a crystal structure - v same as that of the silicon carbide substrate.
6. The semiconductor device according to claim 5, whereinthe silicon carbide substrate (1) is an off-substrate that has a main surface defining an off angle equal to or lessthan 1 degree relative to a Si-face or a C-face,
7. I and a surface of the expanded portion of the gate region (4) has a (0001) facet. 70. i The semiconductor device according to claim 5, whereinthe silicon carbide substrate (1) is an on-substrate that has a main surfacedefining an a-face, and the gate region (4) has a flat surface defining anna-face. i
8. The semiconductor device according to claim 4,Awherein the wide-band gap semiconductor is a silicon carbide; the substrate (1) is a silicon carbide substrate, andthe gate region (4) is configured that the portion contacting the channel layer (2) is made of a silicon carbide having a crystal structure same as that of thei i _27- silicon carbide substrate (1), and at least a part of the expanded portion is made ofa silicon carbide havinga crystal structure different from that of the silicon carbide substrate (1).
9. The semiconductor device according to claim 8, whereinthe silicon carbide substrate (1) is an off-substrate that has a main surfacedefining an off angle greater than 1 degree relative to a Si-face or a C-face, andthe gate region (4) is configured that a surface of the portion having-thecrystal structure same as that of the siliconcarbide substrate (1) has a (0001)facet, and the portion made of the silicon carbide having the crystal structuredifferent from that of the silicon* carbide substrate (1) is made of 'SC-SiC and is formed on the (0001) facet.
10. The semiconductor device according to claim 8, wherein the silicon carbide substrate (1) is an on-substrate that has a main surfacedefining an a-face, and v the gate region (4) is configured that the portion contacting the channellayer (2) takes over the/ crystal structure of the silicon carbide substrate (1) in a vertical direction, and the expanded portion is made of 3C-SiC.
11. The semiconductor device according to any one of claims 5 to 10, whereinthe silicon carbide substrate (1) is made of a semi-insuiating silicon carbide having a specific resistance of 1 x 101° Q - cm to 1 x 1011 Q - cm.
12. I The semiconductor device according to any one of claims 5 to 10, whereinthe junction field effect transistor further comprising a second conductivity typebuffer layer (8) having an impurity concentration lower than that of the gate region (4) between the silicon carbide substrate (1) and the channel layer (2).
13. The semiconductor device according to claim 11, wherein_23- the buffer layer (8) is provided with a second conductivity type contactregion (8a) having a concentration higher than that of the buffer layer (8), and the source electrode (6) is also formed in a recess (9) that passes throughthe source region (3a) so that the buffer layer (8) and the source electrode (6) are electrically' connected to each other through the contact region (8a).
14. A method of manufacturing a semiconductor device having a junction field effect transistor, comprising: a step of forming. a first conductivity type channel layer (2) with a first. conductivity type semiconductor on a main surface of a substrate (1), which ismade of a semiconductormaterial, by epitaxially growing; a step of forming a first conductivity type source region (3a) and a first »conductivity type drain region (3b) in a surface layer portion of the channel layer (2) at positions spaced from each other, the source'region'(3a)^and the drainregion (3b) each having an impurity concentrationhigher than that of the channellayer (2);y i I a step of arranging a carbon mask (11) on the surface of the channel layer(2), the carbon mask (11) having an opening at a position corresponding to wherea second conductivity type gate region (4) is to be formed; a step» of forming the second conductivity type gate region (4) on the 'channel layer (2) by epitaxially growing using the carbon mask (11), so that the _ gate region (4) is grown in a lateral direction up to a position above the carbonmask (11) to form an expanded portion having a width greater than a portioncontactingthe channel layer (2), wherein the gate region (4) is formed on thechannel layer (2) at a position between the source region (3a) and the drain region(3b) and spaced from the source region (3a) and the drain region (3b), a step of removing the carbon mask (11), so that the expanded portion ofthe gate region (4) is spaced from the surface of the channel layer (2); and a step of forming agate electrode (5) on the gate region (4) electrically connected to the gate region (4),¶ a source electrode (6) electrically connected to. ' _29- . the source region (3a) and a drain electrode (7) electrically connected to the drain. region (3b).
15. The method according to claim 14, further comprising a step of forming arecess (2a) at the surface of the channel layer (2) and at a position corresponding to where the gate region (4) is to be formed, wherein in the step of forming the gate region (4) by epitaXially growing, the gate region (4) is formed in the recess (2a) of the channel layer (2). mask (12);
16. The method according to claim 15, further comprising: a step of placing a resist (10) on, the surface ofthe channel layer (2); “ i a step of carbonizing the resist (10), thereby to form the carbon mask (11); a stepof placing an etching mask (12) on the surface of the carbon mask(11): , a step of patterning the etching mask (12) to form. an opening at av positioncorresponding to where the gate region (4) is to be formed; i a step of forming the opening of the carbon mask. (11) using the etching a step of etching the surface of the channel layer (2) through the openings i of the etching mask (12) and the carbon mask (11), thereby to form the recess ä i (2a): a step of removing the etching mask (12); anda step of forming the gate (region (4) in the recess (2a) using the carbon mask (11).
17. The method according to any one of claims 14 to 16, wherein the substrate (1) is a sllicon carbide substrate (1) made of an off-substrate i that has a main surface defining an off angle equal to or less than 1 degree relative to a SiC-face or a C-face, and in the step of forming the gate region (4), the expanded portion is formed_39- _ i to have a (0001) facet on the surface by the growing in the lateral direction.
18. The method according to any one of ciaims 14 to 16, wherein the substrate (1) is a silicon carbide substrate made of an off-substratethat has aimain surface defining an off angle equal to or less than 1 degreerelative to a SiC-face or a C-face, and i _ in the step of forming the gate region (4), the expanded portion is formedto have a (0001) facet on the surface, and 3C-SiC is formed on the (0001) facet by the growing in the lateral direction. i
19. The method according to any one of ciaims 14 to 16, wherein. the substrate (1) is a silicon carbide substrate made of an on-substratethat has a main surface defining an a-face without having an off angle; andin the step of forming the gate region (4), the expanded portion is made of 3C-SiC by the growing in the lateral direction. _-31- '
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