SE522527C2 - Fabrication of integrated circuit for radio frequency applications, involves producing opening in electrically insulating layer for partly covering outer portions along circumference of active region for bipolar transistor - Google Patents

Abstract

An integrated circuit for radio frequency applications is fabricated by producing opening in an electrically insulating layer such that remaining portions of the insulating layer partly covers the active region for bipolar transistor, i.e. outer portions along a circumference of the active region. The insulating layer encapsulates and protects metal oxide semiconductor gate region. Fabrication of integrated circuit for radio frequency applications, comprises providing a silicon substrate. An active region (31) is formed for the bipolar transistor and an active region for the metal oxide semiconductor (MOS) device in the substrate. Field isolation areas (81) are formed around, in a horizontal plate, the active regions. A MOS gate region (111, 112) is formed on the active region for the MOS device. A layer (141) of an electrically insulating material is formed on the MOS gate region and on the active region for the bipolar transistor. A base region in the active region is defined for the bipolar transistor by means of producing an opening (143) in the electrically insulating layer. The opening in the insulating layer is produced such that the remaining portions of the insulating layer partly cover the active region for the bipolar transistor. The insulating layer remains on the MOS gate region to encapsulate and protect the MOS gate region during manufacturing steps, particularly including a step of oxidation, ion implantation and/or etching step.

Description

522 2522 high performance to the process constructed according to the principles described above, but such an approach is usually very costly in terms of additional mesh layers and process complexity.

However, for most circuit designs, any single p-type device is usually sufficient to meet most design needs. In a BiCMOS process, the PMOS transistor can of course be used. In a bipolar IC process for the radio frequency range, lateral PNP transistors can usually be obtained without additional process complexity.

While the active devices in the IC process are continuously improved, there is a need to follow this up with improved device isolation. For quartz micronutrients and smaller, shallow trench insulation (STI) is widely used to obtain an almost flat surface. Using STI instead of LOCOS insulation enables higher packing density, tighter design rules, lower parasites and higher manufacturing precision for both CMOS and bipolar circuits, see Nandakumar, A. Chatterjee, S. Sridhar, K. Joyner, M. Rodder, and I -C. Chen, "Shallow Trench Isolation for Advanced ULSI CMOS Technologies", 1998 IEDM Tech. Dig., Page 133. Although STI is demanding in terms of etching and backfilling process steps, it offers a significant improvement in reduced area required for insulation between circuit elements. Chemical-mechanical planarization (CMP) has been widely used in the process flow to realize STI. To further reduce parasites and crosstalk for sensitive analogue radio circuits, deep trench insulation (DT) is used to replace p / n junction isolation between devices in bipolar processes, see P. Hunt and MP Cooke, "Process HE: a highly advanced trench isolated bipolar technology for analogue and digital applications ", Proc. IEEE CICC 1988, page 816. DT isolation has also been used in CMOS, see R. D. Rung, H. Momose, Y. Nagakubo, "Deep trench isolated CMOS 522 527 devices", 1982 IEDM Tech. Dig., Page 237, although less common. For integrated radio frequency circuits with high performance, STI and DT can be used simultaneously, see the internationally published patent application WO 0120644 (inventors H. Norström, C. Björmander and T. Johansson).

However, when STI isolation is used for high performance integrated radio frequency circuits, the previously successful use of the pre-existing structure to obtain a lateral PNP transistor may not be possible. When the epi layer for the well of the structure is scaled to below 1 μm together with STI insulation (which reaches about 0.5 μm down into the epi layer from the surface), no well area is present during the STI insulation within field areas after processing. Instead, the subcollector is found directly under the field oxide. Although it is still possible to find a lateral PNP structure, the base now consists mainly of the heavily doped subcollector area and consequently the current gain (beta) will be too low to be useful. Another way to obtain a p-type device with reasonable characteristics must be found.

Furthermore, problems with current STI insulation can occur in the form of leakage currents between different device areas. In addition, it can be difficult to obtain very low base collector capacitances in the bipolar transistors and a high beta parasitic pnp device (extrinsic base / n-well / p-well), especially if the n-well has very low doping, can cause problem.

BACKGROUND OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of manufacturing integrated circuits, in particular integrated circuits for radio frequency applications, which provide for efficient production of integrated high quality circuits including bipolar 4,522,527 transistors, especially MOS transistors and MOS devices. and other p-type MOS devices, using a minimum of process steps.

In this regard, it is a particular object of the invention to provide such a method which comprises a number of multifunction process steps.

To this end, according to a first aspect, the present invention comprises a method comprising the steps of: - creating a silicon substrate, which may be a homogeneous substrate or an epi-layer on a disk, - an active region for the bipolar transistor and an active region for MOS the device is formed in the silicon substrate, preferably by doping two surface areas in the substrate and / or two substrate areas in an epi layer on the substrate, - field insulation areas are formed in a horizontal plane around the active areas, preferably by shallow ditch insulation (STI), and optionally by depth ditch insulation (DT), - a MOS board in the form of a stack is formed on the active area of the MOS device, preferably in the form of a polysilicon layer on an oxide layer, - a layer of an electrically insulating material, preferably a nitride, is formed on MOS control stack and on the active region of the bipolar transistor, - a base region is defined in the active region of the bipolar tra the resistor by creating an opening in the electrically insulating layer, preferably by etching, the opening in the electrically insulating layer being created so that the remaining parts of the electrically insulating layer partially cover the active region of the bipolar transistor, i.e. the outer portions around the periphery of the active area, and - the electrically insulating layer is left on the MOS guide stack to encapsulate and protect the MOS guide stack 522 527 during subsequent manufacturing steps, including in particular the steps of ion implantation, thermal oxidation and / or etching.

Preferably, the electrically insulating layer is also left on a collector plug area for the bipolar transistor.

Preferably, a portion of the electrically insulating layer is used as a dielectric in a parallel plate capacitor produced in the process. Yet another object of the present invention is to provide a method of manufacturing an integrated circuit, in particular an integrated circuit for radio frequency applications, to form a shallow ditch for improved isolation of a vertical bipolar transistor included in the circuit.

In this regard, it is a particular object of the invention to provide such a method which provides for the manufacture of a bipolar transistor which does not exhibit current leakage problems.

To this end, according to a second aspect, the present invention comprises a method, according to which: a semiconductor substrate of a first doping type, preferably p, is provided, - a buried collector area of a second doping type, preferably n, of the bipolar transistor is formed in the substrate, a silicon layer grows epitaxially on the substrate, an active region of the second doping type of the bipolar transistor is formed in the epitaxially grown silicon layer, the active region being located above the buried collector region, a shallow ditch is formed in the epitaxially grown silicon layer and the silicon substrate, the shallow ditch in a horizontal plane surrounds the active area and extends vertically a distance down into the substrate, and the shallow ditch is filled with an electrically insulating material.

The buried collector area and the shallow ditch are preferably formed relative to each other so that the buried collector area extends into areas located below the shallow ditch.

A further object of the present invention is to provide an integrated circuit, in particular an integrated circuit for radio frequency applications, comprising a vertical bipolar transistor, which is isolated by means of a shallow ditch in a new way, so that improved performance of the transistor and thereby the integrated circuit can obtained.

To this end, according to a third aspect, the present invention comprises an integrated circuit comprising: - a semiconductor substrate of a first doping type, preferably p, where the substrate has an upper surface, - a vertical bipolar transistor formed in the substrate, wherein the transistor comprises an active region of a second type of doping, preferably n, where an emitter and a base are formed, and a buried collector area of the second type of doping, where the buried collector area is located below the active area, - a shallow ditch for isolating the vertical bipolar transistor, wherein - the the shallow ditch surrounds, as seen along the surface of the substrate, the active area of the transistor, is filled with an electrically insulating material, and extends vertically from the upper surface of the substrate and down into the substrate to a depth where the buried collector area is located.

The buried collector area preferably extends into areas located below the shallow ditch and the buried collector is connected to a collector plug, which is also surrounded by the shallow ditch. Additional features of the invention and advantages thereof will become apparent from the detailed description of preferred embodiments of the present invention given below and the accompanying Figures 1-22, which is shown for illustrative purposes only and thus should not be limiting of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1-3, 4a, 5-19 and 20a-b are greatly enlarged cross-sectional views of a portion of a semiconductor structure during processing according to a preferred embodiment of the present invention.

Figs. 4b and 20c are secondary ion mass spectroscopy (SIMS) diagrams showing doping profiles for an n-well on a buried collector structure and an NPN transistor, respectively, as prepared according to the preferred embodiment of the present invention.

Figs. 21-22 illustrate the design of the main masks and the electrical connections to component areas of the main components made in accordance with the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS In the following description for explanatory and non-limiting purposes, particular details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced in other versions that depart from these particular details.

This specification describes a manufacturing process for an integrated bipolar silicon circuit for high frequency applications, comprising NPN transistors, nitride and MIM capacitors (MIM, metal-insulator-metal) and resistors. The present description illustrates in particular the concept of integrating, in I: 2. I. 2 '. 2 22. ' 2 '..' 8 m ... ... e- r u I c I 1100 Oc u: I U I O: I PMOS transistors in the circuit for the purpose of creating simple p-type devices necessary for circuit design.

The importance of choosing a depth for the STI insulation so that the insulation reaches down to a heavily doped subcollector layer is emphasized.

Available devices are as follows: 'NPN ° PMOS ° Quasilateral PNP device (derived from PMOS) ° Nitride capacitor' MIM capacitor ° Polysilicon resistors Referring now to Figs. 1-22, a detailed description of an embodiment according to the invention is presented in detail in twenty numbered sections. of the process flow to fabricate NPN transistors, PMOS transistors and high performance passive elements. 1. Starting material Fig. 1 shows a cross-sectional view of a silicon wafer of p-type, table top, before forming a buried nf layer (subcollector).

The silicon wafer is an epic wafer comprising a substrate 10, consisting of a heavily doped p * wafer 11 with typically a resistivity of 10 mOhmcm, on which a low doped p-type silicon layer 12 has been grown. This epi-layer is typically 5-10 μm thick and typically has a resistivity of 10-20 Ohmcm.

Alternatively, the p-type disc may be a homogeneous low-doped p-type disc (not illustrated) with a resistivity of typically 1-20 Ohmcm. 522 5279 2. Subcollector Implantation Referring closest to Fig. 2, a thin, protective layer 21 of silica is formed on the surface of the silicon substrate 10 by thermal oxidation, to a thickness of typically 20 nm. The purpose of this layer is to serve as a protection against contaminants from metals or other impurities during implantation.

The thickness of the layer is selected so that ion implantation in a subsequent step can be performed through the layer 21.

A photoresist film 22 is applied to the disk surface and patterned by photolithography. The purpose of this patterned layer, also called SUB mask, is to define a region 23 of a buried collector for a bipolar transistor and doped, buried regions for a PMOS transistor 24 and for a capacitor 25, respectively, by masking subsequent ion implantation.

Thereafter, ions are implanted for the doping of the subcollector, preferably arsenic using an energy of about 50 keV and a dose of about 6El5 cm ", the doped areas being denoted by 26 in Fig. 2. (Throughout the description, the designation XXEYY is used instead of XX * 10 “.) The energy has been selected so that the ions reach the silicon through the thin oxide layer in unprotected areas, but are prevented from penetrating the silicon in areas protected by photoresist.

After implantation, the photoresist is removed by standard wet or dry chemical procedures.

Other n-type dopants may alternatively be used to form the nï sub-collector region, for example antimony (Sb). However, a lower resistivity for a given thickness of the layer can be obtained by using arsenic, which is advantageous for the devices, for example lower collector resistance and lower side wall collector substrate capacitance. In addition, since the diffusivity of arsenic is higher than that of antimony, a shorter recovery time and a lower temperature are required to obtain the desired subcollector profile. 522 527 w 3. Sub-collector drive and oxidation as well as p- Lightning insulation swimming installation Next, a three-stage heat treatment is performed.

First, a 600 ° C heat treatment is used to recrystallize the damage in the implanted area.

Thereafter, a high temperature drive is performed at about 1100 ° C to redistribute the arsenic implanted in the subcollector, so that the doped areas 31 as shown in Fig. 3 are obtained.

The temperature is then lowered to about 900 ° C, where an oxidation is carried out in a wet atmosphere. Since heavily doped n-type regions have a higher oxidation rate, a thicker oxide (l170 nm) will form on areas implanted with arsenic than on non-implanted areas (770 nm). Since silicon atoms will be consumed during this oxidation, 40-50 nm high steps 32 remain on the silicon surface after removal of the oxide. This imprint will later serve as an alignment mark at a subsequent lithography step.

Conventionally, a single-temperature oxidation in the range of 1100 ° C is used for this step. In order to create sufficiently high steps, a thicker initial oxide must then be grown before the arsenic implantation. The oxide is patterned and etched to define the buried collector areas, after which a thin screen oxide is grown in the etched openings before implantation. The main contribution to the alignment step in the silicon comes from different oxide growth rates for the thin and thick oxide regions, respectively. Using the lower oxide rig temperature as described in Y. -B. Wang, P. Jönsson and JV Grahn, "Arsenic Enhanced Oxidation and Effective Control of Buried Collector Step", l96th Meeting of The Electrochemical Society, Honolulu, Hawaii, October 17-22, 1999, allows a simplified process flow without the need for separate layers to create the alignment marks are used.

Before the oxide is removed, a p-type ion implant is performed, consisting of boron with a typical energy of about 120 keV and a dose of 8E12 cmq, the resulting p-doped areas being designated 33 in Fig. 3. The implantation is performed without any mask. The energy and dose are selected so that the implanted boron does not substantially affect the level of doping in the arsenic-doped nf subcollector regions 31 (the number of donor atoms will be substantially unchanged). In the areas between the subcollector areas, however, moderately doped p-areas 33 are formed, which isolate the n-areas 31 from each other.

It should be noted that it is possible to dispense with the above-mentioned p-type implantation and still obtain functional devices by increasing the initial doping level of the starting material, from weak p-type doped to moderate p-type doped. However, in this case, the collector-to-substrate capacitance from the nf sub-collector region down to the pizza substrate will be higher.

The general procedure for creating the nf sub-collector regions and intermediate p-regions is also shown in U.S. Patent 5,374,845 issued to Havemann. However, this patent refers to antimony doped layers and the alignment step is created in a conventional manner using a nitride oxide bilayer. 4. Epi-deposition and n-well lanternation Oxide 21 is removed, preferably by wet chemistry (hydrofluoric acid, HF). The previously described steps 32 at the silicon surface will occur, and an undoped (intrinsic) epitaxial silicon layer 41, with a thickness of about 0.5 to 1 μm, will be grown on the surface by conventional techniques, see Fig. 4a.

Layer 41 may alternatively be n-type doped during epitaxial growth. A typical doping level would be around 1 cm. In U.S. Patent 5,374,845 issued to Havemann, the now corresponding epitaxial layer is doped weakly (to a resistivity higher than 10 Ohmcm), but is still considered to be substantially intrinsic. However, a homogeneous n-type doped epitaxial layer will later in the process flow complicate the formation of substrate surface contacts, so-called top-bottom contacts.

During epitaxial growth, high temperatures in the 1100 ° C range are used. Acceptor atoms in the p-type implanted regions 33 will diffuse into the substrate so that the buried p-regions will form below the epitaxial silicon 41 in regions where no nis sub-collectors 31 are present. Note that the previously described step is recreated at the top surface of the epitaxial silicon layer.

The epitaxial layer will, as described below, be doped within the selected range to obtain n- and p-type regions (n-wells and p-wells). In the n-type regions, located directly above the nis sub-collectors 31, bipolar transistors and capacitors are formed. Substrate contacts from the surface down to the substrate are formed in the p-type regions between n-type regions.

The formation of a hardworm for a shallow ditch is performed next.

The mesh layer for the shallow ditch is formed by oxidizing the silica surface to form a layer 42 of thermal silica typically having a thickness of about 10 nm. Thereafter, an approximately 200 nm thick silicon nitride layer 43 is deposited by chemical vapor deposition (CVD). Other combinations of thicknesses and / or mesh materials are possible.

An ion implantation through the hardworm follows, which forms the previously mentioned n-wells in the epitaxial layer. Phosphorus is preferably used for this n-type implantation, typically at an energy of 650 keV and with a dose of 9E1l cm ”.

The implantation is performed without any lithographic mask layer. 522 527 13 - | u | Depending on the electrical requirements and the thickness of the n-well, the energy and dose can be selected within a wide range.

The ion implantation may alternatively comprise a plurality of implants at different energies and different doses to obtain a softer profile or a doping profile which is heavily doped away from the surface, i.e. a so-called retrograde profile. The entire surface area of the disc now consists of n-wells. p-wells within selected areas will be formed at a later stage, see section 9 below. The n-well profile can alternatively be formed by in-situ doping of the epi layer with, for example, phosphorus or arsenic.

The resulting structure is shown in Fig. 4a and the doping profile of the n-well on the buried collector structure at this stage is illustrated in the SIMS diagram in Fig. 4b.

In sections 5-8, device insulation with shallow and deep ditch insulation will be described. The insulation scheme is also described in the international publication WO 0120664. 5. Formation of a shallow ditch and active areas The formation of a shallow ditch is now considered. A photoresist (not illustrated) is applied to the nitride layer 43 and exposed using a first mask, called a STI mask, which leaves openings where the shallow ditch is to be etched. The etching, which is preferably anisotropic, is performed by reactive ion etching (RIE) through the nitride / oxide layers and into the silicon substrate to form tapered (vertical) shallow trenches 51 as shown in Fig. 5a. The preferred depth for the ditches is 0.2-0.7 μm or more typically 0.3-0.5 μm from the upper surface of the silicon layer 41.

After etching the shallow ditches, the photoresist is removed. vara, ..¿, n .¿ .. .... 5n2 E97 14:; LwE :: nÅ: WLHÜü Ä. d f ... I 1 1 '.' '.' Alternatively, the oxide / nitride bilayer 42, 43 is etched, after which the resist is stripped. Then the STI grooves are etched in one step using the bilayer 42, 43 as a hard mask.

An alternative preferred design of the shallow ditches 51 will be briefly described with reference to Fig. 5b.

The shallow ditches 51 can be formed so that they extend vertically from the silicon surface, i.e. the surface of the silicon layer 41 on top of the substrate 10, and down to the buried collector area 31 and preferably further down to a depth deeper than the depth of the buried collector layer 31, the overlap distance being denoted by z in Fig. 5b.

Furthermore, the buried collector area 31 and the shallow ditch 51 can be formed relative to each other so that the buried collector area 31 extends into areas located below said shallow ditch, such areas being denoted by x in Fig. Sb.

Such a construction has a number of advantages. Problems with leakage currents between different device areas are avoided and thus an improved device insulation is obtained.

The construction enables a weakly doped n-well (especially suitable for bipolar transistors) thanks to the deeper shallow ditch. Low values of the base-collector capacitance Cm can be realized. A parasitic p / n / p device, which may result from other processes, consisting of extrinsic base / n-well / p-well, is avoided because the buried collector areas also extend below the shallow ditch corners (to a distance X illustrated in Fig. 5b). In a p / n transition insulated process, this parasitic device may have a beta greater than 10. A lowering of the n-well doping would increase the beta as well as the risk of structure breakthrough if this shallow ditch structure according to the invention were not used. By using such STI insulation according to the invention, deep ditch insulation, as described in the following two sections, can be dispensed with and still obtain an insulation free from problems with so-called latch-up. 6. Formation of a deep ditch for deep ditch and deep ditch setting With reference to Fig. 6, the formation of a deep ditch for a deep ditch is described. A silica layer 61, typically with a thickness of 0.1-0.5 μm, is deposited, preferably conformally, for example by means of CVD, on the structure (ie remaining parts of the nitride layer and in the shallow ditch). It is preferred that the oxide layer be deposited conformally as margins for subsequent masking and etching will otherwise decrease.

Photoresist is applied and exposed using a second mask, so-called deep ditch mask (not illustrated). The opening (s) of the ditch mask can be placed anywhere within the shallow ditch areas. The width of the deep trench can be selected by using different mesh dimensions. It is usually preferred to use ditches with fixed lateral dimensions (thicknesses), preferably about 1 μm or less, as otherwise problems arise when a non-uniform etch is used and difficulties in filling and planarizing the deep ditch.

The oxide layer is etched by reactive ion etching (RIE) to define the ditch openings, which extend to the bottom surface of the shallow ditch. On the nitride layer, the oxide layer is protected by the photoresist mask, and this oxide will later serve as a hard mask for these areas during the subsequent etching step.

The oxide layer is retained at portions 62 of the shallow ditch area where no deep ditches are to be formed. After etching, the photoresist is removed.

The international publication WO 0120664 mentioned above describes how the deposited silica layer is to be selected and I o. n n n o. a o ø u - | o now 522 527 16 how the ditch mask is to be aligned so that the deep ditch will be self-aligned to the edge of the shallow ditch.

Then the deep ditches 63 are formed by etching, using the oxide 61 as a hard mask. If an oxide spacer is created, this defines the distance from the deep ditch to the active area.

The depth of the deep ditches is at least a few microns and more preferably at least five microns. The resulting structure is shown in Fig. 6. The ditch profile can be made straight and / or tapered, with bottom roundings.

The oxide hard mask for patterning the deep ditches is subsequently removed in, for example, HF. 7. Filling and planarization of deep ditch Subsequent filling and planarization of the ditch areas 51, 63 can be achieved in a number of ways known in the art.

As an illustrative example, the processing is continued by performing an interlayer oxidation (liner oxidation), the purpose of which is to create corner roundings at the sharp edge of the ditches, in order to reduce voltages and undesired electrical effects. This is achieved by growing a thin (20-30 nm) thermal oxide 71 at high temperature (> 10 0 ° C), see Fig. 7. The ditch is filled in a conventional manner with a 200 nm thick layer of TEOS and with 1500 nm polysilicon 72. The polysilicon is then etched back to remove all polysilicon from the shallow ditch areas.

Alternatively, the polysilicon is planarized by chemical-mechanical polishing before the polysilicon is etched back into the shallow ditch areas. This reduces the cavity of the polysilicon filling in the deep trench and consequently a thinner oxide can be deposited in the subsequent step to fill the shallow trench.

The resulting structure is shown in Fig. 7. n ø u o u c | u u o ø a n ø n | o u »522 527 17 v o I Q u a u o o n I a | v n. 8. Filling and dlanarization of shallow ditch; double layer stripping Next, the remaining shallow ditch is filled with, for example, CVD oxide or an HDP oxide (HDP, high density plasma) 81 and planarized, either by dry etching methods or by chemical-mechanical polishing, see Fig. 8.

As a final step for this sub-process, the nitride 43 and the oxide 42 (which can be seen, inter alia, in Fig. 7) are removed from the device areas, preferably by wet methods. The remaining structure now consists of oxide 81 on insulation areas and exposed silicon 41 on device areas. 9. Formation of p-wells Within selected areas (not illustrated in the figures), the nearest p-wells will be formed. In a BiCMOS process, the p-wells are mainly used for NMOS transistors and p-type substrate connectors. In a pure bipolar process, the p-well areas are mainly used for substrate contacts. Later in the process flow, a strongly pf-doped contact at the surface can be formed. The p-well areas are designed so that there will be no n * sub-collector areas under the p-well areas and thus the p-well areas can directly contact the p-type substrate.

The P-wells are formed by first growing a protective oxide 91, see Fig. 9. The oxide 91 will later in the process flow also serve as a "pad" oxide between the silicon substrate and deposited silicon nitride. The thickness of the oxide 91 is typically 10 nm.

A photomask (not illustrated), called p-well mask, is then deposited and patterned. Boron ion implanted in silicon. The energy and doses are chosen so that the ions penetrate through the oxide into the silicon, but not through the photomask. A double implant can be used to obtain a smoother doping profile or retrograde type doping profile. In a particular example, a double implantation of boron at an energy of 100 kev and a dose of 8El2 cmd was used, together with another implantation at an energy of 200 keV and a dose of 1El3 cm cm * within the selected areas.

After implantation, the photomask is removed by conventional wet or dry procedures.

In sections 10-12, further steps for creating a PMOS device in the process flow will be described. The reason for adding the PMOS device to the IC process flow has been discussed earlier in the text. The additional steps, as described herein, can be completely omitted without affecting any other devices on the disc.

Aspects of the integration of a simple PMOS transistor with nf gate and a lithographic length of the gate of about 0.8 μm will now be described, see for example pages 392-397 in S.

Wolf, "Silicon Processing for the VLSI Era, Volume 2 - Process Integration", Lattice Press, Sunset Beach, 1990. In conventional CMOS / BiCMOS processes with 0.5-2 μm lengths for the handlebars, the most common choice is the material strongly n -doped polysilicon. In a double polysilicon-based bipolar process, both heavily doped reach and p * polysilicon are available. An nf control-based PMOS transistor was chosen for process integration reasons. The working function of the rf polysilicon in the handlebar is ideally suited for the n-device and for the p-device a device with a buried channel will be formed. To adjust the threshold voltage to the desired range -0.5 to -1 V, a p-type implant (boron) is used. This overcompensates for the n-surface so that a p-area depleted in holes is formed. The exact bordose depends on several parameters, e.g. oxide thickness of the handlebars and well doping. 522 527 19 10. Addition of PMOS device: threshold voltage adjustment In this step, the disk surface consists of thick oxide field oxide regions 81 (STI) and thin oxide device regions 91 (10 nm p-well oxide) as illustrated in Fig. 9.

A photomask 101 is now applied, see Fig. 10, which is open in the areas which are to serve as device areas for the PMOS device. The disc is then implanted with p-type dopant, boron. The energy is selected so that the dopant penetrates the areas that are not covered by the photomask, but which are covered by thin oxide. Typically, an energy of 20-50 kev was used. The dose is selected to adjust the threshold voltage (VTP) so that it will be in the range -0.5 to -1 V. A typical dose of IEl2-IEl3 cm * was used. The exact dose, or combination of doses and elements, depends on the oxide thickness and background doping of the substrate under the PMOS guide, which in this process flow is set by the implants described in sections 4 and 17, i.e. the n-well implantation and the implantation of the second collector.

Subsequently, the photomask 101. 11 is added. Addition of a PMOS device: formation of oxide and first material of the styrene P-well oxide (also known as Kooi oxide 91 in Figs. 9-10) is removed by wet etching in HF and replaced by an oxide lll for the PMOS transistor using thermal oxidation, see Fig. ll.

This oxide renewal is due to high MOS requirements because the quality of the β-well oxide is normally not sufficient as it has withstood several ion implants.

Typically, a thickness of 15 nm or less is selected on the oxide thickness of the handlebar. In this particular example, which is to support operation at 5 V, a thickness of 12 nm is used. 522 527 20 v u ø | o I n n Q »u». o u This is followed directly by the deposition of a first undoped silicon layer 112, using LPCVD, on the oxide 111.

The deposition parameters are selected to form a non-crystalline layer (alpha silicon). This is obtained when the deposition temperature is below about 550 ° C. The thickness of this layer is quite thin, typically in the 100 nm range, preferably 70 nm. Polysilicon, which is formed at a deposition temperature of about 625 ° C, can alternatively be used to protect the oxide from the styrene. By using a polysilicon material, a wetting agent can penetrate the grain boundaries, but if an almost homogeneous alpha silicon material is used instead, this effect is greatly reduced.

The resulting structure is shown in Fig. 11.

If the process integration so requires, a thin oxide layer (not illustrated) can be formed on top of the polysilicon in this step. The thin oxide may consist of thermally grown oxide, deposited oxide, or thick natural oxide. 12. PMOS Device Addition: MOSBLK Etching The deposited silicon layer 112 required to form the PMOS guide must now be removed from other areas of the disk.

A photomask 121 covering the PMOS device areas (MOSBLK mask, a reverse mask version compared to the PMOS / VTP mask 101) is applied to the disk, see Fig. 12. Using the mask 121, silicon is removed by dry etching, with the field oxide / oxide 81/111 such as etching stops. The resulting structure is shown in Fig. 12.

The photomask is then removed using conventional methods. 522 527 21 13. Collector contact For the formation of active areas (eg a transistor) a low-resistance path is required from the surface of the disc to the sub-collector (eg a collector plug). Furthermore, other types of low-resistance paths may also be needed. Such paths are defined lithographically, by depositing and patterning photoresist to obtain a DNCAP mask 131, so that open areas 132, 133, 134, 135 are created where the paths are to be formed as collector plugs, see Fig. 13. In the illustrated circuit example it is open the area 134 located where a plug together with a subcollector will form an electrode in a capacitor with parallel plates. Accordingly, the photomask also defines the capacitor region 135.

After the photoresist layer has been patterned, doping is performed in the open areas. This is preferably carried out by ion implantation, for example phosphorus at an energy of 50 keV and a dose of 5E15 cm 2, but other dopants, such as arsenic, can alternatively be used, either alone or in combination with phosphorus. Special care must be taken when ditch insulation is used. Details regarding the choice of energy and doses are discussed in the international patent application published as WO 9853489 (inventors: H. Norström, A. Lindgren, T. Larsson and S.-H. Hong).

After the implantation when the photomask 131 is still present on the disc, the thin protective silica layer III is removed in the open areas, preferably by using dry etching. Note that the oxide layer 111 is still present in other regions still covered by photoresist, for example, parts of the device regions where the base region of the bipolar NPN transistor will later be created (between the regions designated 132 and 133).

The resulting structure is shown in Fig. 13. 5 2 2 5 2 7 22 Éïï * ÉÃÉÉ ~ šf? ~ Lzf ïji? The photoresist is then removed by conventional methods, after which the silicon wafer is given a two-step heat treatment, typically at 600 ° C for 30 minutes, followed by treatment at 900 ° C for 30 minutes in a non-oxidizing atmosphere, for example containing N, or Ar. When a thin epi is used, as in the present process flow, the heat treatment can be omitted without increasing the collector resistance. 14. Formation of nitride capacitor and emitter / base openings After the heat treatment, a thin silicon nitride layer, designated 141 in Fig. 14, is deposited, preferably using LPCVD technology and typically to a thickness of the order of 20 nm. The purpose of this layer is threefold: (i) The part of the nitride layer in direct contact with the silicon wafer in the capacitor region will serve as the dielectric in the capacitor to be formed. Since the silicon nitride has a dielectric constant (g) which is approximately twice as high as the dielectric constant of silica, a higher capacitance per unit area is obtained when nitride is used instead of oxide. (ii) The part of the nitride layer deposited on the oxide in the active region, where the base connection is to be made, gives an additional thickness to this insulating dielectric layer, resulting in lower parasitic capacitance for the base collector junction. (iii) A portion of the nitride layer encapsulates the first material 112 for the gate of the PMOS transistor during subsequent processing.

The nitride serves its purpose as an oxidation-resistant mask. In the absence of a protective nitride film, the heavily doped collector plug would oxidize strongly, which would eventually 1 r¿, ¿: ¿.u¿¿ ¿¿¿¿¿ï¿} 502 F27 23: .. '' cause defect generation. It is therefore necessary that the nitride layer remains in the collector plug area. Furthermore, the nitride also protects the first polysilicon layer in the MOS control stack from unwanted oxidation.

Before depositing the silicon nitride layer, the disk can be washed briefly in dilute HF to remove any silicon dioxide that may have formed on the heavily nf-doped areas.

Another concept for realizing a reduced emitter base capacitance of a single poly, bipolar transistor in a BiCMOS flux is described in the following patents: US 5,171, 702 issued to S.H. Prengle and R.H. Eklund and the aforementioned U.S. 5,374,845 issued to R.H. Havemann.

After depositing the nitride layer 141, the disk is lithographically patterned by depositing a photoresist layer 142, after which the resistor is opened for the NPN transistor to be formed, via a so-called E / B mask as well as for each substrate contact in p-type regions (not illustrated). The opening 143 of the NPN transistor is placed in an area where no field oxide 81 is present below the nitride 141, and at a suitable distance from the field oxide edge. openings for substrate contacts are placed in p-well areas, on buried p-type areas (not illustrated).

The nitride layer 141 and the oxide layer III are removed in the openings by conventional etching, preferably by dry methods, and preferably in a procedure in which the nitride and oxide are etched sequentially. The etching is complete when the surface of the silicon layer 41 is exposed. For the NPN transistor, the described method reduces the base area to the area set by the pattern, instead of the larger area defined by the field oxide openings.

In this way, the base of the NPN transistor can be separated from the edges of the field oxide regions, where a higher voltage possibly exists. Such a method of creating a well-defined smaller opening reduces the collector-base capacitance. 5:22 5:27 24 The resulting structure is shown in Fig. 14.

After the etching of the nitride 141 and the oxide III down to the silicon layer 41, the photomask 142 is removed by conventional methods. 15. Formation of extrinsic base layer A thin silicon layer 151, in the range of 200 nm, is next deposited on the structure using CVD technology, see Fig. 15.

The deposition conditions are chosen so that the layer 151 will be amorphous, but microcrystalline or polycrystalline silicon can alternatively be used. The purpose of the layer is to serve as extrinsic base contact for the NPN transistor and upper electrode for the nitride capacitor.

After this deposition, an ion implantation is performed. The purpose is to strongly dop the amorphous silicon layer to p-type. The selected substance for the ion implantation is preferably BF: at an energy of about 50 keV and a dose of about 2E15 cm 2. Alternatively, implanted boron at a lower energy. The energy is selected so that the implanted boron atoms will not reach through the deposited silicon layer 151. If a non-crystalline silicon layer is used, the control of the implanted doping profile is improved.

On top of the silicon layer 151, a silica layer 152 is deposited to a typical thickness of 150 nm using PECVD technology. Other types of low temperature oxide, such as LTO, may alternatively be used. The purpose of using PECVD technology is to keep the temperature so low that the amorphous silicon will not recrystallize during the oxide deposition. The advantages of having an amorphous silica layer implanted with BF2 under a layer of silica deposited by PECVD in forming extrinsic base contacts for the NPN transistor are further described in U.S. Patent 6,077,752 issued to H. Norström.

The resulting structure is shown in Fig. 15. 522 527 25 Pattern of emitter opening Next, a photomask 161, called an RFEMIT mask, is applied to the structure, see Fig. 16. The resistor protects the upper electrode of the nitride capacitor, the p-type substrate contacts and the areas which will form the extrinsic base regions of the NPN transistor. Using the photoresist as a mask, the silica 152 and the amorphous silicon 151 deposited in the previous step are now removed by dry etching.

The etching is completed when the silicon nitride layer 141 is completely exposed in open field areas, where it protects the collector areas and MOS devices.

The etching is preferably performed in a multi-chamber system (cluster system). In this case, a supernatant is removed which removes 20 nm of the silicon within the area 162 with exposed silicon, i.e. the latter defined intrinsic base region of the NPN transistor.

Correspondingly, on top of the PMOS transistor, the silicon nitride 141 is present and the etching will remain on this nitride, leaving the nitride almost intact.

The resulting structure is shown in Fig. 16. 17. Selectively implanted collector The next step is a further doping of what is to become the collector for the NPN transistor, a so-called secondary implanted collector (SIC, indicated by 171 in fig. 16 and 17. The purpose is to minimize the base width and thereby improve the high frequency characteristics of the transistor. In this particular case, it is performed as a double phosphorus implant. In the first stage, phosphorus is implanted at an energy of 200 kev and a dose of 5E12 cm "and in the second stage, phosphorus is implanted at an energy of 420 keV and a dose of 4E12 cm". The order of these steps may be reversed and the exact energy and dose may need to be adjusted to III III I 0 II. .III .UP. .ÖÜ-. '.. ..'. 502 507 26 Mnw :::: JLW.:& i: Å.- 2: 6 n '' -. J., 'n' in '1st! v 'fit current process parameters, such as epi-thickness, temperature collection, etc. during the process.

Note that since the photoresist 161 from step 16 protects part of the NPN transistor so that the implantation is performed only in the emitter base opening, as a consequence no increased collector doping is obtained during the extrinsic base contact 151.

This maintains a low collector-base capacitance of the NPN transistor.

The PMOS transistor is not covered by a photomask during implantation and is completely penetrated by the implanted substance, which sets the background doping for the n-well of the PMOS transistor. The implantation parameters will therefore affect the threshold voltage of the transistor, but this can be compensated for by changing the dose for the threshold voltage implantation.

After implantation, the resist is removed using conventional methods, and a thin silica 172, in the range of 10-20 nm, is grown thermally on the disk surface where bare silicon is exposed, i.e. in the intrinsic base opening 162 (Fig. 17). The growing is done in a wet atmosphere at a comparatively low temperature of 800 ° C. During this step, the remaining PECVD-deposited oxide layer 152 on top of the extrinsic base electrode 151 will consequently be densified. On the side wall of the structure, thermal oxide will grow on the exposed silicon. During the heat treatment, the amorphous silicon 151 is converted to polycrystalline silicon while the previously implanted drill is redistributed inside the polysilicon to form contact paths 173 for the β-base. 18. Intrinsic Base Formation In the next step, boron will be implanted in the structure to create the intrinsic base region 174 of the NPN transistor. In this particular example, boron is implanted at a dose of about 1.5 cm / cm at an energy of about 6 keV. If the thickness of the thin oxide formed in previous steps changes, a change of the implantation parameters may be required. The implantation only penetrates the silicon in the base area, since the other silicon areas are protected by the nitride layer 141.

After implantation, the structure is further oxidized, preferably in a wet atmosphere at 800 ° C, which reduces the boron atom concentration at the silica / silica surface.

Then, with reference to Fig. 18a, an approximately 120 nm thick layer of silicon nitride is deposited conformally by LPCVD technology.

The nitride layer is etched by a special anisotropic until sidewall spacers 181 of silicon nitride remain where large steps are present in the surface, such as in the intrinsic base port 162 of the NPN transistor (insides spacers). Following this spacer formation, the opening of the intrinsic base is referred to as the emitter port 162. Not only is the newly deposited nitride removed, but the thin nitride 141 (deposited in step 13) present at field 81 and collector contact areas 41 and on top of the PMOS control structure 112 is removed. simultaneously in this etS.

In the middle of the emitter opening 162 remains the thermal oxide, which must also be removed. The oxide can be removed by wet or dry etching. In this particular example, a two-stage dryer was used. The first etching step refers to oxide removal using RIE (Reactive Ion Etching) in an Ar / CHF 3 / CF 3 plasma and the second etching step is a mild isotropic in situ silicon in Ar / NF 3 to remove residues and radiation damage from the previous RIE etch. . The second etching step removes about 10 nm of silicon from the exposed surface of the emitter orifice.

Since this etching affects the intrinsic base profile, the etching depth can be controlled depending on the current gain requirements (beta or hm) of the NPN transistor to be manufactured. 522 527 28 This second etching step will also remove part of the silicon which is now used as the first material 112 for the control of the PMOS transistor. The initial thickness of the material for the gate has been chosen by such a margin so as not to cause any problems for the PMOS transistor.

The resulting structure is shown in Fig. 18a.

After etching, a polysilicon layer 182, typically 220 nm thick, is deposited using LPCVD technology, see Fig. 18b.

Layer 182 is subsequently doped by ion implantation, preferably by arsenic and / or phosphorus.

In the preferred embodiment, the doping is performed in three separate steps.

First, the entire surface of the disc is implanted with arsenic at an energy of about 50 keV and with a dose of 3El5 cm ”.

As a second step, a patterned photoresist mask (not illustrated) is used, which leaves resist in areas of resistors with low values (RW) and high values (RM), an arsenic implant at an energy of about 150 keV and a dose of 1,2El6 cnfzutförs. The resist mask is then removed.

The third step involves patterning another mask layer 183, see Fig. 18c, which defines areas for low value resistors (Rw) and for contact plug areas 132, 133, 134, after which phosphorus at an energy of about 25 keV and with a dose of 4El5cm “implanted. The resist mask 183 is then removed.

The resistors with high values (RM) thus obtained will have a surface resistivity of about 500 Ohm / square, while the resistors with lower values (Rm) will have a surface resistivity of about 100 Ohm / square. These resistance values can be changed by adjusting the doses and energies. 1 .. .n ~. u n n n I-: I f v. u.. n. a. o. o u n. u f) r f ', .. ... . -. . - ... .- fl. n u n ~ v v I II II I 'I' 'i, f g I I I I x I l 0 II I 1 I I' - I-I. . n. o u .. f »n I I v ø I» An important feature is that the polysilicon in contact with the emitter window receives two consecutive arsenic implants at different energies. No phosphorus is allowed to enter the emitter polysilicon 182, see Fig. 18c.

However, the polysilicon in contact with the collector is typically implanted using a combination of arsenic and phosphorus. By using two different dopants of the same doping type, but which have different diffusivities, a low-resistivity and deeper collector contact is obtained. 19. The emitter's The doped polysilicon 182 (in Fig. 18c) will most likely be patterned using lithography and dry etching, see Fig. 19a. In this step, contact areas are defined for the emitter 191 and the collector 192 for the NPN transistor, the deeper electrode 193 of the nitride capacitor, the gate 194 for the PMOS transistor and the substrate contact 195 for the PMOS transistor, and resistors with low and high values l9a).

Where the polysilicon is in direct contact with the monocrystalline silicon surface in the emitter port 162, at a later process step the polysilicon will act as a doping source during collection of the emitter in the intrinsic base region 174. By using a photoresist mask 196, called EMI POLY mask, parts of the doped the polysilicon until the field oxide regions 81 are exposed.

This etching is preferably performed using RIE with a Cl, / HBr / O 2 plasma.

The resulting structure is shown in Fig. 19a.

After etching, the resist is removed by conventional methods.

The oxide layer 152 of the p-type polysilicon layer 151 must now be removed (not illustrated). This can be done by dry etching, either globally over the entire disc, or locally using a photomask 197, called a BASE OXREM mask, see Fig. 52 2 5 7 30 23.3 - ä fi fíë - .lä f * l9b, which is the preferred approach in this embodiment. The photomask is patterned so that apertures are created over the p * polysilicon layer. The oxide is then removed by RIE using an Ar / CHF 3 / CF 3 plasma. The etching is stopped when the polysilicon is exposed in the resist openings. The advantage of using a photomask, instead of a global etch, is that the field oxide regions 81 will be protected by the photoresist; otherwise they would erode.

After etching, still with resist in place, an additional drill implant is performed to dope the respective emitter and collector regions 198 of the PMOS device, see Fig. 19b. The extrinsic base 151 of the bipolar transistor, the upper plate 151 of the capacitor and the polysilicon for the p-type substrate contacts (not shown) will be implanted simultaneously. After complete etching and implantation, the photoresist is removed. 20. Emitter Activation and Recovery A thin, approximately 30 nm thick, oxide layer 200 is deposited on the wafer. Preferably TEOS is used, but other oxides such as LTO or PECVD may alternatively be used.

On top of the oxide 200 is deposited a silicon nitride layer 201 of about 100 nm thickness in conformity using LPCVD technology. The resulting structure is shown in Fig. 20a.

After deposition, the disc is exposed to high temperature to activate and drive in the previously implanted dopants.

According to the preferred embodiment, the heat treatment is performed in a two-step procedure. The disk is first subjected to an oven heating to 850 ° C for about 30 minutes, the purpose of which is to redistribute the dopants more evenly in the implanted layers. The first step can actually be dispensed with in the present process flow, since the semiconductor wafer already has .nu v n nu un 00 502 RÖ? 31 ffzf:: z: '. 7.§ Éf "f ._.' ¿" ¿: _ V L.; :: °, ''. '.: ..' .. ".. '.... .. received sufficient heat treatment during the deposition of the silica / nitride 200/201, which is typically carried out at about 790 ° C for more than three hours.

A second heating in a nitrogen atmosphere at about 1075 ° C for 16 seconds, using RTA (Rapid Thermal Anneal) equipment. The purpose of this heating is to electrically activate the implanted substances and set the final doping profiles for the emitter-base junction of the NPN transistor and the profile for the PMOS device.

Note that the previously deposited silicon oxide layer 200 and the silicon nitride layer 201 remain on the disk. Their purpose is to prevent the diffusion of implanted substances into the environment during the heat treatment.

During the heat treatment, arsenic implanted in the upper polymer layer 191 will penetrate the intrinsic base by diffusion and form the emitter-base junction. According to this embodiment, the depth of the emitter 202 is about 50 nm and the remaining thickness of the intrinsic base 174 below the emitter is about 50 nm. The concentration of arsenic in the emitter orifice at the transition between the surface of the monocrystalline silicon layer and the polycrystalline layer is typically SE20 atoms / cm The corresponding boron concentration in the intrinsic base at the emitter-base junction is typically 1E18 atoms / cnfï. In the manufacturing process described, the extrinsic base depth is about 200 nm and the corresponding boron concentration at the interface between the extrinsic base polysilicon and the monocrystalline silicon is typically IE20 atoms / cm 2 ”. This heavily doped p-type region is called extrinsic base. a o 5 2 2 5 2 7 32 íïli - ¥ :: = - Li åxå The substrate contact is formed in a corresponding manner by diffusion of boron from the p-type polysilicon layer.

The gate 194 of the PMOS transistor structure consists of the n-poly layer (182 in Fig. 18b), i.e. emitter polyethylene, and the remainder of the first material (112 in Fig. 11) for the handlebar, which was undoped polysilicon. During the heat treatment, nf type dopants have been redistributed in the control layers by diffusion, so that the control is now homogeneously doped with nf material and thus the nf control 194 of the PMOS transistor has been formed.

The emitter / collector areas of the PMOS transistor are also activated by the heat treatment.

The resulting structure is shown in Fig. 20a.

After the heat treatment, the resistor is defined lithographically, so that a protective layer of photoresist will only remain over the resistor bodies (not shown). End portions of the resistors will be exposed. After patterning, the silicon nitride layer 201 and the silicon oxide layer 200 are etched away within surface portions not covered by the photoresist layer. The etching is anisotropic, so that spacers 203 are formed along the edges of the nf-type polysilicon layer 194, see Fig. 20b.

The process described herein in the manufacture of so-called silicon nitride spacers on top of a thin silicon oxide layer is substantially similar to the manufacturing process described in U.S. Patent 4,740,484 issued to H. Norström et al. Then the photoresist layer is removed.

After removal of the photoresist layer, the nf-type polysilicon layer 194 and the p * -type polysilicon layer 151 can be provided with a thin silicide layer to reduce the resistance of conductors to the various electrode regions of the components manufactured - these conductors will then be shorted with such a silicide layer. The silicide layer can consist of, for example, PtSi, 5:22 m 33 a «o I o see CoSi2 or TiSi2. According to a preferred embodiment, titanium disilicide TiSi2 is used, which is formed by using a so-called "self-aligning method" on top of exposed silicon surfaces.

Since the resistor bodies are not exposed, but are protected by remaining parts of the silicon nitride layer 201, no silicide is obtained thereon.

In such a self-aligning silicidation ("SALICIDE"), see U.S. Patent 4,789,995 issued to Brighton et al. And U.S. Patent 4,622,735 issued to Shibata depositing a thin metal layer, in this case a layer of titanium having a thickness of about 50 nm, preferably by sputtering over the surface of the disc. The metal layer is then allowed to react for a short period of time, about 20 seconds, with exposed silicon at an elevated temperature of about 715 ° C in a nitrogen atmosphere in an RTA equipment. In some cases a mixture of oxygen and ammonia can also be used. Then the titanium is dissolved, which has not reacted with silicon, ie. at those parts which had no exposed silicon surface before the metal deposition, removed by wet chemical methods. This etching step, which selectively removes unreacted titanium, affects the titanium silicide only to a lesser extent. After the wet chemical etching process, the plate is heated to about 875 ° C for about 30 seconds to form a low resistance form of titanium disilicide.

The silicide layer thus formed, which has a surface resistance of about 2-5 ohms / square, will then only be present on the previously exposed silicon surfaces of the plate, i.e. be self-aligned with these surfaces.

The structure after formation of external spacer 203 and SALICIDE (self-aligned silicide) 204 is shown in Fig. 20b and in Fig. 20c a SIMS profile for an NPN transistor produced according to the described process flow is shown. 5 2 5 7 34 gt:. gr:. j; gf, 21. Mask designs, contact holes for the first metal layer Figs. 21a-c show views of mesh designs for the three main devices (NPN transistor, quasilateral PNP device (ie PMOS device) and nitride capacitor) described in previous sections. The contact holes (checkerboard patterned) for the first metal layer are also shown.

Fig. 21a shows masks for an NPN transistor, where 22 is the SUB mask, 211 the STI mask (see section 5), 212 the deep ditch mask (see section 6), 213 the p-well mask (see section 9) , 142 E / B mask, 161 REFEMIT mask, 196 EMI POLY mask and 197 BASE OXREM mask.

Furthermore, contact holes for the base 214, the emitter 215 and the respective collector 216 are illustrated.

Fig. 21b shows masks for the quasilateral PNP transistor, where 22 is the SUB mask, 211 the STI mask (see section 5), 212 the deep ditch mask (see section 6), 213 the p-well mask (see section 9 ), 121 MOSBLK mask, 131 DNCAP mask, 196 EMI POLY mask and 197 BASE OXREM mask. Note that the design of this component differs from the cross-sectional views because the substrate contact is also annular.

Furthermore, contact holes are illustrated for the guide 217 (grounded), for the collector 218 (collector) and the emitter 219 (emitter) and for the substrate contact 220 (base).

Fig. 21c shows masks for the nitride capacitor, where 22 is the SUB mask, 211 is the STI mask (see section 5), 212 the deep ditch mask (see section 6), 213 the p-well mask (see section 9), 131 DNCAP mask, 161 REFEMIT mask, 196 EMI POLY mask and 197 BASE OXREM mask.

Furthermore, contact holes for the upper 222 and lower 221 electrodes are illustrated. . 'an. n. 'a' * ° f.): -o'šs "z:. = .I: 'I" °° °.'. 'ES 2; 22 få 22 3 5; :: ° -.- '.:.: ..' .. ".. °.: .. '.' 22. Connection to the first metal layer Fig. 22 ab shows a further characteristic of the NPN transistor when the transistor is connected to it first metal layer.

To obtain the lowest bass resistance (corresponding to the best frequency performance), bass contacts 221 are placed on both sides of the emitter E, as shown in Fig. 22a. Thanks to the strict design rules, this can be done without changing the size of the transistor (which is usually not the case according to process methods described in the prior art).

However, some transistors in a circuit design may need to be used to output higher currents. The design in Fig. 22a can then be limited by the width of the metal contacting the emitter E (the current density in the emitter connection).

Since the extrinsic base completely surrounds the emitter and is covered with TiSi 2 to further reduce the base resistance, the metal compounds would then be placed as shown in Fig. 22b, with only a very small increase in the base resistance.

Furthermore, the same transistor design can be used for double and single base contacts (only the contact holes and the metal layers must be designed differently).

The continued process flow mainly follows the process flow described in the international patent application published as WO 9903151 (inventors: H. Norström, S. Nygren and O.

Tylstedt).

If an NMOS device is to be manufactured in this process, typically four additional process steps must be added: masking and ion implantation of the NMOS control area and masking and ion implantation of NMOS emitter and collector areas, respectively. Furthermore, a MIM capacitor can be added to the flux as described in U.S. Patents 6,100, 133 (inventors H. Norström and S. Nygren).

It is to be understood that the invention may be practiced in a number of ways. Such variations should not be construed as a departure from the scope of the present invention. All such modifications as will be apparent to those skilled in the art are intended to be included within the scope of the appended claims.

Claims (30)

37 PATENT REQUIREMENTS A method of manufacturing an integrated circuit, in particular an integrated circuit for radio frequency applications, comprising at least one bipolar transistor and at least one MOS device, characterized - a silicon substrate (10, 41) is provided, by the steps of: - an active region (41) for the bipolar transistor and an active region (41) of the MOS device is formed in said silicon substrate (10), - field regions (81) are formed around said active regions in a horizontal plane, - a region (111, 112) for a MOS control is formed on said active area of the MOS device, - a layer (141) of an electrically insulating material is formed on said area of the MOS control and on said active area (41) of the bipolar transistor and - a base area is defined in said active region of the bipolar transistor by forming an opening (143) in said electrically insulating layer (141), said opening (143) in said electrically insulating layer being created so that remaining parts a the electrically insulating layer (141) partially covers said active region of the bipolar transistor and - said electrically insulating layer (141) remains on said region of the MOS control to encapsulate and protect the region of the MOS control during subsequent manufacturing steps, in particular comprising an oxidation step, an ion implantation and / or an etching step. The method of claim 1, wherein said electrically insulating layer is a nitride layer (141). The method of claim 1 or 2, further comprising forming a capacitor (41, 141, 151), wherein a portion of ø v; now said electrically insulating layer (141) is used as a dielectric in said capacitor. A method according to any one of claims 1-3, wherein said area of the MOS guide is formed as a silicon layer (112) on top of an oxide layer (III). The method of claim 4, wherein an oxide is formed on top of the silicon layer (112) prior to forming said electrically insulating layer (141). The method of claim 4 or 5, further comprising the step of forming an oxide layer (111) on top of said active region (41) of the bipolar transistor prior to forming said electrically insulating layer (141). The method of claim 6, further comprising the step of also forming said aperture (143) through said oxide layer (111) on top of said active region (31) to expose a portion of said active region (41) of the bipolar transistor. A method according to claim 6 or 7, wherein said oxide layer (III), on top of which said polysilicon layer (112) for the gate is formed, and said oxide layer (111) formed on said active region of the bipolar transistor is created, preferably grown, simultaneously. A method according to any one of claims 1-8, wherein said active region (41) of the MOS device is ion implanted prior to forming said region (111, 112) of the MOS guide. A method according to any one of claims 1-9, wherein a secondary implanted collector (SIC) (171) in said active region (41) of the bipolar transistor and a background doping of said active region (41) of the MOS device are formed simultaneously in an ion implantation step. f:: __ The method of claim 10, wherein an extrinsic base (151) 577 ... 39 for the bipolar transistor is formed on said electrically insulating layer (141) and partially on said active region (41) of the bipolar transistor in said aperture ( 143) to thereby define an emitter orifice (162), wherein said extrinsic base is formed before said ion implantation step and is protected by photoresist (161) during said ion implantation step. The method of claim 11, wherein said extrinsic base (151) is doped and an emitter and a collector region (198) are simultaneously formed in said active region (41) of the MOS device in an ion implantation step. The method of claim 12, wherein also an electrode (151) of a capacitor (41, 141, 151) and / or a contact layer for a substrate contact is doped in the ion implantation step, in which said extrinsic base is doped. The method of claim 12 or 13, wherein a bilayer of silica (200) and silicon nitride (201) is formed on said doped emitter and collector regions (198), thereby preventing implanted substances from diffusing out of said active region (41). . A method according to any one of claims 1-14, wherein said active regions (41) of the bipolar transistor and the MOS device are formed by ion implantation through an oxide nitride bilayer. A method according to any one of claims 1-15, wherein a collector (31, 41, 171, 192) comprising a collector plug (192, 41) for said bipolar transistor is formed and wherein said collector plug is doped by ion implantation with two different dopants (As, P) of the same doping type (s), but which have different diffusivities, in order to obtain a low-resistance and deep collector plug. u I I I O O I I. . .- 17. l7. A method according to claim 16, wherein an emitter contact (191) is formed and wherein said emitter contact is doped by means of one of said dopants used in said implantation of said collector plug. The method of claim 16 or 17, wherein said ion implantation of said collector plug is performed in three separate steps, each step comprising ion implantation of a dopant at a given energy and a given dose. The method of claim 18, wherein high resistance and low resistance (RM, Rm) resistors are formed in said three stage implant. A method according to any one of claims 1-19, wherein the bipolar transistor is an NPN transistor and the MOS device is a PMOS transistor. A method according to any one of claims 1 to 20, wherein - a buried collector region (31) of the bipolar transistor is formed in said substrate (10), said buried collector region being located below said active region (41) of the bipolar transistor, - the field isolate region formed around the active region of the bipolar transistor is formed as a shallow ditch (51) in said silicon substrate, said shallow ditch extending vertically from the substrate surface and down into (z) the buried collector region (31), and - said shallow ditch is filled with an electrically insulating material (81). The method of claim 21, wherein said buried collector area (31) and said shallow ditch (51, 81) are formed relative to each other so that said buried collector area extends into areas (x) located below said shallow ditch. 5222 527 41 The method of claim 22, wherein said buried collector region is strongly n-doped, preferably to a concentration of at least about 11E19 cnf fi, and said active region of the bipolar transistor is doped to a concentration not higher than about 1E17 cmd, preferably not higher. than about 5E16 cm ", and most preferably not higher than about 1E16 cm * and most preferably about 1E16 cnf A method according to any one of claims 21-23, wherein a deep ditch (63) is formed in said shallow ditch (51) and particularly self-aligned to said shallow ditch. A method of manufacturing an integrated circuit, in particular an integrated circuit for radio frequency fabrication, for forming a shallow ditch for isolating a vertical bipolar transistor included in said circuit, characterized by the steps of: - a semiconductor substrate (10) of a first doping type is provided, - a buried collector region (31) of a second doping type is formed for the bipolar transistor in said substrate, - a silicon layer (41) is grown epitaxially on said substrate, - an active region (41) of said second doping type is formed for the bipolar transistor in said epitaxially grown silicon layer, where the active area is located above the buried collector area (31), - a shallow ditch (51) is formed in said epitaxially grown silicon layer and said silicon substrate, said shallow ditch surrounding said active area in a horizontal plane, and extends vertically a distance (z) into said substrate, and said shallow ditch is filled with an electrically insulating ma terial (81). The method of claim 25, wherein said buried collector area (31) and said shallow ditch (51) are formed,. u f now 42 522 relative to each other so that said buried collector area 527 extends into areas (x) located below said shallow ditch. A method according to claim 25 or 26, wherein said shallow ditch is formed by masking and etching. A method according to any one of claims 25-27, wherein said substrate doping is of the p-type and said dopings of said buried collector area and said active area are of the n-type. The method of claim 28, wherein said buried collector area is heavily doped, preferably to a concentration of at least about 1E19 cm 3, and said active area is doped to a concentration not higher than about 1E17 3 cm -1, preferably not higher than about 5E16 cm , and even more preferably not higher than about lEl6 cm * and most preferably around lEl6 cm *. A method according to any one of claims 25-29, wherein a deep ditch (63) is formed in said shallow ditch (51), and in particular self-aligned to said shallow ditch. ø o n a 00