JP5563340B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a BiCMOS technology configuration in which CMOS transistors and bipolar transistors are integrated.

  The integration of bipolar transistors into CMOS technology results in BiCMOS technology, increasing the flexibility in circuit design. With BiCMOS technology, system-on-chip integration can be realized and the functionality of the chip is enhanced. Wireless communications account for a significant portion of the consumer electronics market and are greatly affected by product costs. Thus, radio frequency systems (RF systems) can benefit from integrating bipolar technology and CMOS technology.

  Bipolar transistors can be classified as vertical (vertical) or horizontal (lateral). In the vertical bipolar transistor, carriers flow in the vertical direction from the emitter to the collector. Since the collector region is formed at a deep position from the wafer surface, the resistance between the emitter and the collector increases, and such a transistor is disadvantageous for high-speed operation. Furthermore, since a high concentration buried layer, a collector / epitaxial layer, a deep trench isolation, and the like are required, the number of process steps increases and the cost increases.

On the other hand, the lateral bipolar transistor has a simpler structure than the vertical bipolar transistor. BiCMOS technology can also be constructed by adding a relatively small number of process steps to the CMOS transistor. Further, since the collector electrode can be in direct contact with the collector region, the lateral bipolar transistor is advantageous for performing high speed operation. Therefore, it is desirable to use a lateral bipolar transistor in which carriers flow laterally in BiCMOS technology.
Patent Document 1 describes a new type of lateral bipolar transistor named horizontal current bipolar transistor (HCBT).

  FIG. 8 shows a cross-sectional view of the HCBT described in Patent Document 1. The HCBT shown in FIG. 8 includes a collector electrode 101, a base electrode 102, and an emitter electrode 103. An HCBT active region 105 (referred to as n-hill in this case) is formed on the p-type substrate 104. The n-hill 105 is surrounded by shallow trench isolation (STI) 106 and the height of the entire STI 106 is indicated by “a”. A portion of the STI 106 on the side of the n-hill 105 is removed by wet etching. The thickness of the remaining insulating oxide film is indicated by “b”. An internal base 107 is formed at the side of the n-hill 105, and an external base 108 in contact with the outside is formed at the top. Emitter polysilicon 109 is formed on the remaining insulating oxide film. This is doped n-type, typically phosphorus, by in-situ doping in the deposition. The emitter diffusion region 110 is formed by diffusion from the emitter polysilicon 109 by the following thermal process essential for CMOS. The shape of the emitter polysilicon 109 is controlled by the dummy gate polysilicon 111. On the opposite side of the emitter, an n + diffusion region 112 of the collector electrode 101 is formed in the n− hill 105. The surfaces of the n + diffusion region 112, the external base 108 and the emitter polysilicon 109 are covered with silicides 113, 114 and 115, respectively. In order to avoid electrical shortage between the collector and the base, the silicide blocking oxide 116 is left by patterning the silicide blocking mask. Simultaneously with the silicide blocking etch, the side spacers 117 remain on the sides of the n-hill 105. This produces a separation effect between the base silicide 114 and the emitter silicide 115.

As described above, the base silicide 114 and the emitter silicide 115 are separated by the spacer 117 by CMOS technology. This means that the base silicide is separated from the emitter polysilicon 109 by the height of the spacer 117. Since the height “a” of the entire active transistor region in FIG. 8 is limited by the CMOS process, and the thickness of the emitter polysilicon 109 is limited by the electrical performance requirements, the thickness “b” of the insulating oxide region is The thickness must be sufficient to prevent penetration of the base into the substrate. Therefore, the height of the spacer 117 is also limited.
PCT No. WO / 2009/081867

However, the current gain of the HCBT described in Patent Document 1 is smaller than that of the vertical arrangement. The reason can be analyzed as follows.
The main components of the base-emitter current are shown in the enlarged sectional view of HCBT in FIG. Since the arrow indicates the flow of charge carriers, the actual current flow is opposite to the carrier flow in the case of negatively charged electrons (components _InE , IR, IR _{, top} ), but the actual current Is the same as the carrier flow in the case of positively charged holes (component I _pE ). The common emitter current gain (beta) is defined as the collector-base current ratio: beta = IC / IB. The collector current IC is mainly dependent on the emitter electron flow of the npn transistor: IC = I _nE . Although the base recombination current IR is ignored, the base current IB is composed of three current components. That is, hole current I _pE injected from the base to the emitter _is an electronic I _{R, top} to IR recombination current of the internal base region, at the top of the emitter are injected from the emitter into the base silicide contact direction. _{Here, IB = I pE + I R} + I R, a _top. In order to increase beta, it is necessary to increase IC and decrease IB, but it has already been optimized with existing designs of longitudinal current and lateral bipolar transistors. In a vertical current bipolar transistor, there is a sufficient distance between the base contact region and the emitter, and the external base region below the contact is highly doped, so _{that IR, top} is usually the other base. It can be ignored compared to the current component. Reducing the base current component _{IR, top} by increasing the distance between the base contact region and the emitter n + region and / or by increasing the doping concentration on the IR _{, top} current path. it can. Both techniques reduce the possibility of diffusion to the base contact by electrons injected from the emitter.

On the other hand, since the spacer 117 has a limited height in the HCBT structure, the base silicide 114 is located close to the emitter diffusion region 110. Since IR _{and top} are relatively larger than in the vertical case, beta is reduced.
In order to solve this, the following idea is also described in Patent Document 1. As shown in FIG. 10, the base contact silicide 114 can be separated from the end of the active n-hill 105 by a silicide blocking oxide 118. In this way, the distance between the base contact silicide 114 and the emitter diffusion region 110 increases and the total doping concentration on the current path increases. This is indicated by the longer arrow corresponding to _{IR, top} in FIG.
In addition, the emitter contact silicide 115 is moved away from the base-emitter junction that potentially contributes to the reduction of the I _pE component and the further reduction of IB. This structure is called a mask separation type HCBT, while the former is called a spacer separation type HCBT.

  Separating the base and emitter contact silicide from the base-emitter junction can be done using a silicide blocking mask. FIG. 11 shows some of the masks of the spacer separation type HCBT in which the emitter and base silicide are separated by the spacer 117. A similar mask for a mask-isolated HCBT having a base and emitter contact silicide separated by a portion of a silicide blocking mask is shown in FIG. These masks include a silicide blocking mask 201, an active n-hill mask 202, a collector n + implant mask 203, a contact hole mask 204, a dummy polysilicon mask 205, and an insulating oxide etch mask 206. . In the case of FIG. 12, the silicide blocking mask consists of two parts. One is for leaving an oxide film between the base and the collector contact region (silicide blocking mask 201), and the other is for the base and emitter contact region (silicide blocking mask 201b). ) To leave an oxide film.

The maximum value of the beta of the mask separation type HCBT is 25% higher than that of the spacer separation type. This occurs due to a decrease in IB, but other characteristics remain unchanged. However, beta is still small compared to vertical bipolar transistors.
The present invention has been made in consideration of the above-mentioned points. An object of the present invention is to provide a semiconductor device having a lateral bipolar transistor having a high beta, although fmax and BVCEO are similar to those of a conventional bipolar transistor. Have.

In order to achieve the above object, the present invention according to claim 1 is a semiconductor device in which a lateral bipolar transistor and a CMOS transistor are mixedly mounted, and the lateral bipolar transistor has an active region (for example, An open region (for example, FIG. 4-4) opened in an element isolation region (for example, isolation SiO ₂ 20 illustrated in FIG. 4-4 (m)) surrounding the n-hill 12 illustrated in FIG. 4-4 (m). The emitter window 19) shown in (m), the polysilicon film (for example, the emitter polysilicon 32 shown in FIG. 4-4 (m)) formed on the open region, and the active from the polysilicon film An emitter diffusion layer region (for example, an emitter diffusion region 39 shown in FIG. 4-4 (m)) formed by impurity diffusion to the side surface of the region, and the element isolation region A dummy gate polysilicon film (eg, dummy gate polysilicon 50 shown in FIG. 4-4 (m)) formed thereon and a collector diffusion layer region (eg, FIG. 4) formed in the active region. -4 (m), the collector region 37) and the base diffusion layer region (for example, the internal base region 27 and the external base region 16 shown in FIG. 4-4 (m)), and the collector diffusion layer region and the base diffusion layer region. Collector electrode (for example, collector electrode 101) and base electrode (for example, base electrode 102 shown in FIG. 4-4 (m)) directly connected to, and an emitter electrode (for example, FIG. m) an emitter electrode 103), and a silicide region in which silicide is formed in the active region and the polysilicon film, and the base diffusion layer region includes: A non-silicide region (for example, a non-silicide region 410 shown in FIG. 2 ) having an internal base formed on the side of the active region and an external base formed on the upper surface of the active region, where no silicide is formed on the active region. ) Is a boundary region between the base diffusion layer region and the collector diffusion layer region, and the external base and the element isolation region extending along a direction toward the base electrode in the external base in the base diffusion layer A peripheral region having another boundary region, and another boundary region between the element isolation region and the polysilicon film formed on the open region, and an active region above the polysilicon film it shall be the said containing portion covered by the spacer formed on the side surface of the.

Furthermore, the present invention according to claim 2, silicide is not formed in the open polysilicon film formed on the region as a non-silicide region, further, between the base diffusion regions and the emitter diffusion layer region It includes a peripheral region having another boundary region.
FIG. 13 shows a cross-sectional view along the active side surface of the spacer separation type HCBT. In FIG. 11, this sectional view is shown as AA ′, which is perpendicular to the sectional views shown in FIGS. Assuming that the constant distance between the emitter polysilicon 109 and the base silicide 114 is a constant arrow concentration corresponding to _{IR, top} as shown in FIG. 13 _{, the IR, top} component of IB Is substantially uniform along the emitter. On the other hand, the emitter polysilicon 109 is thinner toward the periphery of the transistor due to the round shape of the insulating oxide film. This is because the emitter region is reduced compared to the center of the transistor 120 (FIG. 13). This means that IC decreases in the peripheral region 119 (FIG. 13) of the transistor. Since _{IR and top} are constant, IB does not decrease in proportion to IC. Therefore, local beta in the peripheral region 119 of the transistor is reduced, and beta of the entire transistor is reduced. In addition, as shown in FIG. 14, due to the nature of the wet etching process used on the top surface of the emitter polysilicon 109, it may be closer to the base silicide 114, as shown by the high density arrows, In the region 119 _{, IR} and _top are increased. This effect increases the local beta reduction in the peripheral region 119 as well as the overall beta reduction.

The effect of reducing beta in the transistor peripheral region 319 can be minimized by reducing the base silicide 314 along the emitter length, as shown in FIG. In this manner, the path of electrons injected from the emitter toward the base silicide 314 in the peripheral region 319 increases, and as a result _{, IR and top} decrease as shown by the low density arrows in the peripheral region 319 in FIG. To do. The base silicide 314 can be moved away from the peripheral region 319 of the transistor by changing the shape of the silicide blocking mask 401 as shown in FIG.
Note that the domain of the non-silicide region 410 coincides with the domain of the silicide blocking mask 401 shown in FIG.

FIG. 3 shows a structural cross-sectional view of a base contact silicide reduced along an emitter corresponding to a B-B ′ cross section of FIG. 2 in a spacer-separated HCBT structure. Figure 2 shows some of the lithographic masks used in a spacer-isolated HCBT process with reduced base contact silicide (pan type). Figure 2 shows some lithographic masks used in a mask-isolated HCBT process with reduced base contact silicide (surround type). Fig. 2 shows an HCBT process flow. The dependence of the base (IB) and collector (IC) currents in the HCBT structure on the base-emitter voltage (Vbe), called the Gummel plot, is shown. The beta dependence with respect to the base-emitter voltage (Vbe) in a HCBT structure is shown. The cut-off frequency (fT) and maximum oscillation frequency (fmax) in the HCBT structure are compared with the collector current (IC). 2 shows an HCBT structure having a single polysilicon region cross section. FIG. 2 is an enlarged cross-sectional view of an HCBT structure called a spacer-separated HCBT in which an emitter and a base silicide contact are separated by a spacer. FIG. 2 shows an enlarged cross-sectional view of an HCBT structure called a mask isolation type HCBT in which an emitter and a base silicide contact are separated by a silicide blocking mask. Figure 2 shows a lithographic mask used in a spacer-separated HCBT process. Figure 2 shows a lithographic mask used in a mask-separated HCBT process. FIG. 12 is a cross-sectional view of the spacer-separated HCBT structure along the emitter corresponding to the A-A ′ cross section of FIG. 11. FIG. 12 is a cross-sectional view along the emitter corresponding to the A-A ′ cross section of FIG. 11 of the spacer-separated HCBT structure when the emitter polysilicon is wet etched.

  The HCBT is suitable for integration with a CMOS that realizes a low-cost and high-performance BiCMOS technology. However, HCBT can be manufactured as a bipolar-only technology as well. In this case, the CMOS process is indispensable for the HCBT structure in the BiCMOS technology, but must be used for the bipolar dedicated technology. The description of the HCBT of the present invention is based on the BiCMOS process flow. The CMOS process steps associated with the HCBT structure will be described, but will not be described because the process steps used only for CMOS technology applications are considered common.

A typical set of masks used for HCBT with reduced base silicide is shown in FIG. A significant difference from the conventional HCBT (FIGS. 11 and 12) is a silicide blocking mask 401. This shape is like a “pan” surrounding the insulating oxide etching mask 406, but is open on the emitter side. 1 is a cross-sectional view taken along the line BB ′ of FIG. This structure is referred to as “pan type” in the following description.
Note that the region of non-silicide area 410 coincides with the domain of the mask 401 shown in FIG. 2 of the activation region.

The collector n + implantation mask 403 shown in FIG. 2 coincides in the collector region. The active n-hill mask 402 coincides with the top surface of the active region. And the base area | region mentioned later of an active region is formed. Polysilicon connected in the emitter diffusion region is formed and is indicated by reference numeral 409. Reference numeral 10 denotes shallow trench isolation. The current moves from the collector region to the emitter region and drifts in the base region (drifts from the bottom to the top of the entire FIG. 2).
FIG. 3 shows one embodiment of the present invention. Silicide blocking mask 501 surrounds the entire insulating oxide etch mask 406. The effect of mask isolation and reduced base silicide hybridization can be expected with this structure. This structure is hereinafter referred to as “surround type”. Note that the domain of the non-silicide region 510 coincides with the domain of the mask 501 shown in FIG.

FIG. 4 shows cross-sectional views of the HCBT in the order of process steps. The HCBT structure is usually manufactured on the same substrate 11 as the p-type CMOS. The beginning of this process is the standard CMOS process flow required to form shallow trench isolation (STI) 10, as shown in FIG. 4-1 (a). The active region of the HCBT is used for the collector region, is formed in the silicon pillar / n-hill 12 surrounded by the STI, and is defined by the CMOS active n-hill mask 402. Thereafter, well implantation is performed to create an n-type local substrate for pMOS transistors and a p-type local substrate for nMOS transistors, both of which are necessary for CMOS technology. It is necessary to change the doping concentration for different types of transistors on the same wafer (for example, optimization for high speed, high voltage, high current, etc.). The same applies to other types of devices (eg resistors, capacitors, derivatives, etc.). Also, different doping profiles and gradients may be required to obtain the desired device performance, which is usually done by ion implantation. Depending on the CMOS technology and target HCBT characteristics, one or several combinations of ion implantation steps may be used in the CMOS device, as shown at 13 in FIG. It can be used for doping. An npn transistor requires moderate n-type doping, resulting in an n-hill collector region. In this case, a CMOS lithography mask used for n-well implantation can be used for doping the n-hill collector region of the HCBT. In the more general case, in addition to the CMOS process flow, the n-hill region can be implanted by a separate process, requiring an additional lithographic mask. This is the first additional mask required for the HCBT structure. However, the mask dimensions are the same in either case, whether a CMOS mask or an additional HCBT mask is used. The n-hill implant results in a doping profile in the n-hill region that is optimized for HCBT characteristics. Several injection steps can be used. For example, by using phosphorus, 3 × ¹⁰ 12 ^{cm -2} dose and 320keV energy, 3 × ¹⁰ 12 ^{cm -2} dose and 140keV energy, 7 × ¹⁰ 11 ^cm energy dose and 30keV ^-2 is mentioned It is done. This results in a high peak concentration in the upper active transistor region, in order to suppress the expansion effect of the base width, that is, to optimize the high frequency characteristics and obtain a more uniform electric field distribution, which is a breakdown. Means higher voltage. After the well implantation of the CMOS process flow, the photoresist 14 is removed and high temperature annealing is performed to repair the silicon crystal structure after being damaged by the implantation and to electrically activate the implanted impurities. Can do. HCBT n-hill implants can be performed immediately before or after the CMOS well implant, so the annealing process flow in the CMOS process step should be used to repair the crystal and activate the HCBT dopant as well. Can do.

  After the well implantation, the gate forming process is usually performed in the CMOS process flow. This process step is also used to form polysilicon 50, called dummy gate polysilicon 50, on the top surface of the STI 10 around the n-hill 12 as shown in FIG. The dummy gate polysilicon 50 has a role of controlling the shape of the emitter polysilicon to be flat. The HCBT characteristics depend in particular on the thickness of the emitter polysilicon, especially in the part in contact with the side surface of the n-hill 12. The dummy gate polysilicon 50 helps to improve the uniformity of emitter polysilicon thickness and HCBT characteristics. During the gate oxidation process, n-hill 12 oxidizes. During the polysilicon gate etch of the CMOS process, the HCBT area is exposed and the polysilicon on top of the n-hill should be removed except for the dummy gate polysilicon 50.

After the polysilicon etch, the gate of the MOS transistor is usually lightly oxidized and the etched polysilicon gate region including the dummy gate polysilicon 50 is confined by a thin oxide layer. Thereafter, source / drain extension regions are implanted. Different MOS transistors are also selected by different lithography masks. At this point in the CMOS process flow, the second lithography mask required for the HCBT structure can be applied. This is used for the external base implantation 15a, resulting in a p-type region as shown in FIG. 4C, and covering the CMOS portion of the chip with the photoresist 17. An example of an external base implantation condition may be a dose of 3 × 10 ¹⁵ cm ⁻² and an energy of 22 keV using BF ₂ . In a CMOS process flow, the source / drain extension layer can be annealed by a high temperature process after implantation. The same process can be used to anneal the external base region, repairing the silicon crystal structure and activating the implanted impurities. In the case of HCBT, this step helps to avoid silicon crystal defects along with the interaction of implanted impurities and impurities that are subsequently implanted for the internal base. If annealing is not used in the CMOS process flow, or if the annealing parameters are inappropriate for HCBT, the external base can be implanted before the source / drain extension and annealed by additional steps. In this case, the annealing temperature and time will usually not be significantly affected by the CMOS structure since it is lower or as short as the gate oxidation conditions. In addition, the CMOS source / drain regions are most sensitive to thermal annealing and have not yet been formed at this point in the process.

After the CMOS source / drain extension layer annealing step, the entire CMOS structure is covered with photoresist 18 using a third additional mask 406 required by the HCBT to expose the emitter window 19 of the HCBT. As shown in FIG. 4D, the insulating SiO ₂ 20 is etched with a predetermined time using this mask. Either wet etching or dry etching can be used. In the case of wet etching, the emitter window 407 is formed wider than the mask 406 due to the characteristics of the wet etching process, as shown in FIG. The etch is designed to determine the internal base portion of the transistor, exposing the active n-hill side 21. After the insulating SiO ₂ etch, a thin SiO ₂ layer 22 should be deposited as shown in FIG. 4-2 (e). It is the standard procedure for ion implantation that is used for implanted impurities, damage reduction and silicon surface protection.

Next, the internal base implant 26 is performed using the second HCBT mask used in the external base implant 15a at the tilt angle shown in FIG. 4-2 (e). A p-type internal base region 27 on the n-hill side is obtained. An example of an internal base implantation condition can be a dose of 6 × 10 ¹³ cm ⁻² and an energy of 35 keV using BF ₂ at an angle of 30 °. The internal base can be implanted in several steps to obtain optimized doping profiles for the internal and external transistor regions. The HCBT lithography mask 406 used for the insulating SiO ₂ etch is angled with respect to the active n-hill mask 402 as shown in FIG. 2 to make the insulating SiO ₂ very thin at the interface with the n-hill. Is attached. In this way, the base implant partially penetrates such thin SiO ₂ and gradually blocks the base implant around the emitter window. This method increases the base doping concentration around the emitter and ultimately prevents collector-emitter penetration. Furthermore, in order to obtain HCBT having high equal frequency characteristics, phosphorus must be injected using the same pattern as the internal base. This implantation step is referred to as “selectively implanted collector (SIC)” and locally increases the collector concentration. This has the effect of narrowing the base width and reducing the collector resistance that hardly increases the collector-base capacitance. An example of SIC implantation conditions could be a dose of 6 × 10 ¹² cm ⁻² and an energy of 320 keV with phosphorus at an angle of 40 °.

It is also possible to implant an external base at this point in the process instead of implantation before the insulating SiO ₂ etch. Since the lithography mask for the base implantation has to be applied only once in this case, the number of process steps is reduced. The outer base can be implanted at a wafer rotation angle opposite to the inner base 15b to protect the active side from additional implantation from the outer base, as shown in FIG. 4-2 (f). On the other hand, the outer base can be intentionally used to increase the doping of the inner base, resulting in a vertical implantation into the wafer surface 15c or at the same rotational angle as the inner base, but possibly Another inclination angle 15d is obtained. By varying the tilt and rotation angles, the doping profile of the inner and outer base regions can be optimized. In addition, in this way, the inner and outer base regions share the same annealing step and the process flow continues. The external base may promote diffusion of the internal base boron, resulting in a wider internal base region, which is usually not desirable for transistor current gain and high frequency characteristics. Also, the implanted ions scattered in the insulating SiO ₂ can cause the outer base to over-dope within the inner base, especially at the bottom of the base. Care must be taken with this effect in defining both implantation parameters, ie implantation 15b is preferred in order to minimize the additional doping at the bottom of the base.

After the internal and external base implants, the photoresist 25 must be removed and the screening SiO ₂ thin layer 22 is etched. Since the screening SiO ₂ is similarly deposited to cover the CMOS structure, the etching time must be determined so that the thermal oxide film grown on the polysilicon gate of the CMOS transistor is not removed. Thus, the screening SiO ₂ etch must be timed only to remove the screening SiO ₂ on the upper side of the active transistor. The active side SiO ₂ accepts internal and possibly external base implants, and its etch rate may be faster than the unimplanted SiO ₂ on top of the CMOS gate, resulting in the screening SiO ₂ being n-hill. Compared with the standard HCBT described in Patent Document 1 that needs to be removed from the collector side surface, the margin for determining the etching time is increased. Since the screening SiO ₂ is obtained by a deposition process, its etching rate is faster than that of thermally grown SiO ₂ present on the CMOS gate. Accordingly, there is no problem in leaving the thermally grown SiO ₂ above the CMOS gate after the screening oxide film etching.

After the SiO ₂ etching for screening, the silicon surface of the active transistor side surface 28 is exposed. This surface is treated by thermal annealing to form its termination layer. An example of this surface treatment is rapid thermal annealing at 800 ° C. for 20 seconds in a nitrogen atmosphere. This treatment prevents epitaxial regrowth during polysilicon deposition, and this surface serves as a protective film during the etching of the polysilicon layer. A thin oxide layer can be grown on the exposed silicon surface caused by residual oxygen in the annealing chamber, or any other non-silicon surface termination can be formed. Regardless of its chemical composition, this layer can stop the polysilicon etch that is essential for the HCBT process. However, this layer needs to be thin enough so that current can flow without substantially increasing the resistance. During this thermal annealing, the implanted base dopant diffuses and redistribution of the doping profile occurs.

  As shown in FIG. 4G, a polysilicon layer 29 is deposited next. Since the polysilicon region acts as the emitter of the transistor, it must be highly doped. A high doping level in the polysilicon region can be achieved by an in-situ doping process, i.e. doping during deposition. Although in situ-ping is considered the simplest, the polysilicon layer can be doped by other methods such as ion implantation, diffusion, etc. In-situ-ping is preferred in this case due to its uniformity and homogeneity, resulting in even diffusion of dopant from the emitter into the base region during the subsequent annealing step. In addition, in-situ ping can be used to achieve a shallower emitter-base junction or to deposit an undoped layer on top to increase the deposition rate, for example, thin undoped or near the active side It can be designed to optimize the process flow to have a lightly doped layer. The thickness of the deposited polysilicon determines the shape of the polysilicon region remaining after etch back. Since the remaining polysilicon region needs to be flat, the surface of the deposited polysilicon should be as flat as possible. Due to the conformal nature of the polysilicon deposition process, the deposited layer fills the emitter window 19. As the thickness of the polysilicon increases, it becomes more planar. In addition, dummy gate polysilicon 50 is useful for this purpose, and the thickness of the polysilicon can be thinner than in this case. Although these are probably the simplest planarization methods, other techniques known in semiconductor fabrication can be used, such as chemical mechanical planarization (CMP). The CMP stop layer may be the top of the CMOS gate, or any other structure (eg, a capacitor) present on the surface at this point in the process. In the case of a bipolar-only process, or in other BiCMOS integration schemes, the top of the STI oxide film can serve as a CMP stop layer.

After deposition, the polysilicon layer 29 is etched back, and an emitter polysilicon 32 is obtained as shown in FIG. The outer base region 16 and the inner base region 27 are already defined and need to be protected during the polysilicon etch back as well as the entire n-hill 12 region. To meet this requirement, tetramethyl ammonium hydroxide (TMAH) etching is used for polysilicon etch back because it has high sensitivity to oxide. During the predeposition surface treatment, the thin layer growing on the n-hill surface is sufficient to stop the TMAH etch and fully protect the n-hill. Other crystal dependent etchants can be used for this purpose (eg, KOH, EDP, etc.). Typically, other polysilicon etch techniques can be used, such as other wet etch chemistries or dry etch processes. However, TMAH meets the high polysilicon requirements for oxide selectivity and CMOS process compatibility, making it perfectly suitable for this process. The polysilicon etch back process is timed after the polysilicon thickness 33 defines the height of the active emitter, such as collector current, base resistance, base-emitter capacitance, ideal nature of base current, etc. Affects transistor electrical characteristic values. The polysilicon etching rate by TMAH can be adjusted by the temperature and concentration of TMAH in water. If the polysilicon planarization technique is realized by deposited ions and etch back, the surface of the polysilicon layer will not be completely planar, as shown in FIGS. 4-2 (g) and 4-2 (h). However, the post-deposition notch 31 will be transformed into the final polysilicon region shape 34. Since the shape of the polysilicon region is not very critical to the performance of the transistor, the polysilicon layer hole is no, that is, a state of being placed on top of the etched insulating SiO ₂ with n- Hill neighborhood, Even in the thinnest region 34 of the emitter polysilicon 33, it is necessary to ensure metal contact with the n-hill. The TMAH etch rate depends on the crystal orientation of the etched layer. Since polysilicon consists of grains with different orientations, its surface after TMAH etch back may become rough. In order to minimize the roughness of the polysilicon surface, smaller grains of the polysilicon structure are preferred, which implies the use of a layer having a more non-crystalline structure. This can be achieved by adjusting the deposition conditions of the polysilicon, for example, one method may be to reduce the deposition temperature.

Basically, after the TMAH etch back of polysilicon, the additional process steps required for HCBT are complete. The HCBT structure is completed by a CMOS process process. Therefore, a CMOS process that affects the HCBT structure will be described.
The next CMOS process module is usually to form gate spacers. The SiO ₂ layer is deposited, for example, from a tetraethyloxy silane (TEOS) source and is etched back by an anisotropic process. The SiO ₂ spacer is left on the side of the CMOS gate. Due to the nature of this process, similar spacers 35 are formed on the n-hill sides above the polysilicon region, as shown in FIG. 4-3 (i). Thereafter, source / drain implantation is performed on the CMOS structure. The implantation of the n + source / drain 36 region of the nMOS transistor is used for the collector region 37 of the HCBT structure as shown in FIG. 4-3 (j). The position of the end of the photoresist 38 defined by the mask 403 used for the implantation defines the distance between the n + collector and the external base region, such as the collector-base and collector-emitter breakdown voltages, and the like. It depends on the transistor characteristics. The other end of the collector n + region is defined by the n-hill sides. Annealing to activate the CMOS source / drain implants is the activation of the HCBT implant region, and from the highly doped polysilicon region (shown in FIG. 4-3 (k)) to the n-hill side. It is also used for a diffusion region 39 of dopant, usually called drive-in diffusion. The n + diffusion region 39 formed by this process is an emitter diffusion region. The doping profile of the internal transistor region is formed by this process. The depth of the base-emitter pn junction after annealing can be adjusted by changing the doping level of the deposited polysilicon, as well as changing the grain structure of the polysilicon, both being determined by the deposition situation.

The next CMOS process module is silicide formation. First, a SiO ₂ layer 40 used as a silicide protection layer is deposited. Using the lithographic mask 401, some of the CMOS devices are opened and some of the devices or areas thereof are protected by the photoresist 41. In HCBT, a portion of the SiO ₂ layer between the collector and the external base must be protected as shown in FIG. 2 and / or FIG. Further, a part of the SiO ₂ layer around the insulating oxide etching mask 406 is protected as shown by a mask 401 in FIG. 2 (pan type). In other embodiments, a portion of the SiO ₂ layer between the emitter polysilicon and the endogenous base is protected as shown by the mask 501 in FIG. 3 (surround type). Residual SiO ₂ prevents electrical shortcuts between the n + collector and the external base region. Further, as described above, the SiO ₂ remaining around the insulating oxide film etching mask 406 helps reduce IB. As shown in FIG. 4-3 (l), the silicide 42 is formed by a standard method having a process step known as silicidation in the semiconductor industry.

At the back end of the process flow, SiO ₂ 43 is deposited, contact holes 44 are etched and filled with a low resistance layer, and metallization is done in a standard way. The final HCBT structure having one metal layer is shown in FIG. 4-4 (m). In the contact hole 44 of FIG. 4-4 (m), the collector electrode 101, the base electrode 102, and the emitter electrode 103 are formed.

Dependence of base (IB) and collector (IC) current on base-emitter voltage (VBE) for spacer-separated, pan-type, mask-separated, and surround-type HCBT structures, also known as Gummel plot Is shown in FIG. “Spacer separation type” and “pan type” are drawn on one graph, and “Mask separation type” and “surround type” are drawn on the other graph. It can be seen that the IC is nearly compatible for all structures. On the other hand, IB changes depending on the mask. In the case of the surround type, since IB is the lowest, beta is the highest. The bread type is the second best. For the pan-type HCBT structure, beta is 58%, which is higher than the spacer separation type. On the other hand, the beta of the surround type HCBT structure is 61%, which is higher than that of the mask separation type. The increase in beta due to the modification of the silicide-protection pattern is shown in FIG. “Spacer separation type” and “pan type” are drawn on one graph, and “Mask separation type” and “surround type” are drawn on the other graph.
The collector-emitter breakdown voltage (BVCEO) is usually in a trade-off relationship with beta. This is because they are affected by the base width. However, the modification of the silicide protection pattern does not affect the internal base. Thus, as shown in Table 1, all transistors exhibit similar BVCEO.

FIG. 7 shows a comparison between the maximum frequency of the four types of cut-off frequency (fT) and oscillation (fmax) and the collector current (IC) of the HCBT structure. “Spacer separation type” and “pan type” are drawn on one graph, and “Mask separation type” and “surround type” are drawn on the other graph.
Regarding fmax, the non-silicided region of the active region affects the high frequency characteristics (especially fmax) of the bipolar transistor.
If this region becomes too large, fmax will deteriorate. In other words, there is a trade-off relationship between beta and fmax. For this reason, the non-silicided region of the present invention is optimized to best suit to obtain sufficient fmax and high beta compared to the conventional one.

In FIG. 7, there is no significant difference in the HCBT structure between the spacer separation type and the pan type. The same tendency can be seen between the mask separation type and the surround type.
Also, fmax and BVCEO do not decrease in the case of the lateral bipolar transistor of the present invention. Only beta can reach 200 at the maximum. Furthermore, the lateral bipolar transistor of the present invention can be realized only by changing the mask layout of the conventional lateral bipolar transistor. For this reason, the number of manufacturing processes does not increase even when compared with conventional lateral bipolar transistors.

10 Shallow Trench Isolation (STI)
11 Substrate 12 n-hill (collector area)
13 Collector implantation 14, 17, 18, 25, 38, 41 Photoresist 15a, b, c, d External base implantation 16 External base region 19 Emitter window 20 Insulating SiO ₂
21 n-hill side surface 22 SiO ₂ thin layer 26 internal base implant 27 internal base region 28 active transistor side surface 29 polysilicon layer 31 depression 32, 34 emitter polysilicon 33 polysilicon thickness 35 spacer 36 source / drain implant 37 Collector region 39 Emitter diffusion region 40, 43 SiO ₂ layer 42 Silicide 44 Contact hole 50 Dummy gate polysilicon 101 Collector electrode 102 Base electrode 103 Emitter electrode 104, 304 p-type substrate 105 n-hill (active region)
106 Shallow Trench Isolation (STI)
107 Internal base 108, 308 External base 109, 309, 409 Emitter polysilicon 110 Emitter diffusion region 111 Dummy gate polysilicon 112 n + diffusion region 113 Collector silicide 114, 314 Base silicide 115 Emitter silicide 116, 118 Silicide Blocking oxide film 117 Spacer 119, 319 Peripheral region 120, 320 Transistor central region 201, 201b, 401, 501 Silicide blocking mask 202, 402 n-hill mask 203, 403 Collector n + Implant mask 204, 404 Contact hole mask 205, 405 Dummy polysilicon mask 206, 406 Insulating oxide etching mask 207, 407 Emitter window Copper (after the wet-etching)
410, 510 Non-silicide region

Claims (2)

A semiconductor device in which a lateral bipolar transistor and a CMOS transistor are mixedly mounted,
The lateral bipolar transistor is
An open region opened in an element isolation region surrounding the active region;
A polysilicon film formed on the open region;
An emitter diffusion layer formed by impurity diffusion from the polysilicon film to the side of the active region;
A dummy gate polysilicon film formed on the element isolation region;
A collector diffusion layer region and a base diffusion layer region formed on the active region;
A collector electrode and a base electrode directly connected to the collector diffusion layer region and the base diffusion layer region;
An emitter electrode directly connected to the polysilicon film;
A silicide region formed on the active region and the polysilicon film;
With
The base diffusion layer region has an internal base formed on a side surface of the active region and an external base formed on the upper surface of the active region,
A non-silicide region in which no silicide is formed on the active region includes a boundary region between the base diffusion layer region and the collector diffusion layer region, and a direction toward the base electrode in the external base in the base diffusion layer . A peripheral region having another boundary region between the external base and the element isolation region extending, and another boundary region between the element isolation region and the polysilicon film formed on the open region, And a semiconductor device including a portion covered with a spacer formed on a side surface of the active region above the polysilicon film . As a non-silicide region which silicide is not formed in the open polysilicon film formed on a region further comprises a peripheral region having other boundary region between the base diffusion regions and the emitter diffusion layer region The semiconductor device according to claim 1.

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