CN111969061A - LDMOS structure and manufacturing method thereof - Google Patents

LDMOS structure and manufacturing method thereof Download PDF

Info

Publication number
CN111969061A
CN111969061A CN202010805199.0A CN202010805199A CN111969061A CN 111969061 A CN111969061 A CN 111969061A CN 202010805199 A CN202010805199 A CN 202010805199A CN 111969061 A CN111969061 A CN 111969061A
Authority
CN
China
Prior art keywords
dielectric layer
region
gate
ldmos
drift region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202010805199.0A
Other languages
Chinese (zh)
Other versions
CN111969061B (en
Inventor
不公告发明人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuxi Xianren Zhixin Microelectronics Technology Co ltd
Original Assignee
Wuxi Xianren Zhixin Microelectronics Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi Xianren Zhixin Microelectronics Technology Co ltd filed Critical Wuxi Xianren Zhixin Microelectronics Technology Co ltd
Priority to CN202010805199.0A priority Critical patent/CN111969061B/en
Publication of CN111969061A publication Critical patent/CN111969061A/en
Application granted granted Critical
Publication of CN111969061B publication Critical patent/CN111969061B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention relates to the technical field of semiconductor manufacturing, in particular to an LDMOS structure and a manufacturing method thereof, aiming at solving the problem of contradiction between breakdown voltage and on-resistance of an LDMOS device in the prior art, and the LDMOS structure is technically characterized by comprising a semiconductor substrate; the well region is positioned in the semiconductor substrate; the body region is positioned on one side of the well region of the semiconductor substrate; the grid structure comprises a grid dielectric layer and a polysilicon grid which are formed in an overlapping mode; the source electrode structure is positioned on the surface of the body region and is aligned with the first side face of the polysilicon gate; the drain electrode structure is positioned on the surface of the well region and is close to the second side surface of the polysilicon gate; and the drift region is positioned in the junction area of the gate structure and the drain structure, and the doping concentration of the drift region is gradually increased from the gate structure along the transverse direction. According to the scheme, the lateral gradual change of the doping concentration of the drift region is realized, so that the breakdown voltage of the LDMOS device is increased, the on-resistance is not increased too much, and the performance and the reliability of the LDMOS device are improved.

Description

LDMOS structure and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an LDMOS structure and a manufacturing method thereof.
Background
LDMOS (Laterally Diffused Metal Oxide Semiconductor) is developed for 900MHz cellular phone technology, and the continuous growth of cellular communication market ensures the application of LDMOS transistor, and also makes the technology of LDMOS continuously mature and the cost continuously reduced, so that it will replace bipolar transistor technology in most cases in the future. Compared with a bipolar transistor, the LDMOS transistor has higher gain, the gain of the LDMOS transistor can reach more than 14dB, the bipolar transistor is 5-6 dB, and the gain of a PA module adopting the LDMOS transistor can reach about 60 dB. This shows that for the same output power, a cellular phone using LDMOS transistors requires fewer devices, thereby increasing the reliability of the power amplifier.
The doping distribution of the drift region directly influences the breakdown voltage and the on-resistance of the LDMOS device. A large number of researchers have studied the doping distribution of the region, such as a stacked LDD structure, a dual-layer RESURF structure, and the like, and have a certain positive effect on the optimization of the breakdown voltage and the on-resistance, but the effect is limited. With the progress of the technology, further requirements on the performance of the LDMOS device are required, and an LDMOS device with large breakdown voltage and small on-resistance is urgently needed.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to overcome the defect that the breakdown voltage and the on-resistance of the LDMOS device in the prior art cannot be expected, thereby providing an LDMOS structure and a manufacturing method thereof.
A first aspect of the present invention provides an LDMOS structure, comprising:
a semiconductor substrate;
the well region is positioned in the semiconductor substrate;
the junction depth of the body region is smaller than that of the well region, and the body region and the well region are transversely overlapped;
the grid structure comprises a polysilicon grid and a grid dielectric layer which are formed in an overlapping mode, wherein the grid dielectric layer covers the surface of the body region, and the second side face of the grid dielectric layer extends to the surface of the well region; the surface of the body region covered by the gate dielectric layer is used for forming a channel;
the source electrode structure is positioned on the surface of the body region and aligned to the first side surface of the gate dielectric layer;
the drain electrode structure is positioned on the surface of the well region and close to the second side surface of the gate dielectric layer;
and the drift region is positioned in the junction area of the gate structure and the drain structure, and the doping concentration of the drift region is gradually increased from the gate structure along the transverse direction.
Optionally, the rate of change of the doping concentration of the drift region in the lateral direction gradually increases from the gate structure varies with the increase of the doping concentration.
The second scheme of the invention provides a manufacturing method based on the LDMOS structure, which comprises the following steps:
forming a well region in the semiconductor substrate, and forming a body region in the semiconductor substrate on one side of the well region;
forming a gate structure spanning and covering part of the body region and the well region, forming a source electrode structure on the body region on one side of the gate structure, and forming a drain electrode structure on the well region on the other side of the gate structure;
forming a drift region positioned in the well region in the junction region of the gate structure and the drain structure, and forming barrier layers positioned on the well region on two sides of the drift region;
doping the drift region;
forming a dielectric layer covering the drift region in the junction region of the gate structure and the drain structure;
performing inclined ion implantation on the dielectric layer to dope the surface layer of the dielectric layer, wherein the doping depth is deeper along with the distance from the body region, and forming a doped dielectric layer;
corroding or etching the doped dielectric layer to form a residual dielectric layer with gradually changing height;
and carrying out high-temperature annealing on the drift region to form the drift region with the doping concentration gradually increasing from the gate structure along the transverse direction, and removing the residual dielectric layer and the barrier layer.
Optionally, when the oblique ions are implanted, the oblique ions are obliquely incident downwards along a direction from the gate structure to the drain structure, and an included angle is formed between the incident direction of the oblique ions and the horizontal direction.
Optionally, the included angle is 15-60 °.
Optionally, the ion source of the tilted ion is BF2Said BF2The implantation energy is 3-30KeV, and the dose is 1e13-1e14/cm2(ii) a Or
The ion source of the tilted ions is boron, the energy of the boron implantation is 3-6KeV, and the dosage is 1e13-1e14/cm2。
Optionally, the dielectric layer is an initial dielectric layer after molding and before performing the oblique ion implantation, and the initial dielectric layer is doped.
Optionally, when a dielectric layer covering the drift region is formed in a junction region of the gate structure and the drain structure, the forming temperature of the dielectric layer is 50-150 ℃.
Optionally, the rate of change of the doping concentration of the drift region in the lateral direction gradually increases from the gate structure varies with the increase of the doping concentration.
Optionally, the change rate of the remaining dielectric layer when the height gradually changes varies with the change of the height.
The technical scheme of the invention has the following advantages:
1. the LDMOS structure provided by the invention controls the doping concentration of the drift region to change continuously along the transverse direction, and gradually increases the doping concentration from the grid structure, so that the breakdown voltage of the LDMOS device is increased, the on-resistance is not increased too much, and the performance and the reliability of the LDMOS device are improved.
2. According to the manufacturing method of the LDMOS structure, the drift region is doped, the dielectric layer covering the drift region is formed in a low-temperature state, and the dielectric layer is subjected to inclined ion implantation, so that the surface layer of the dielectric layer is doped, the doping depth is deeper along with the farther away from the grid structure, and the doped dielectric layer is finally formed; corroding or etching the doped dielectric layer to remove the doped dielectric layer, wherein in the corrosion or etching process, the corrosion or etching rate of the undoped dielectric layer is zero, and the corrosion or etching rate of the lightly doped dielectric layer is slower, so that a residual dielectric layer with gradually changing height is finally formed; and performing high-temperature annealing on the drift region, wherein the doped impurities can be activated by the high-temperature annealing, the impurities in the drift region can diffuse into the dielectric layer due to the diffusion of the impurities, and the total amount of the impurities diffused at different positions in the drift region is different due to the different thicknesses in the remaining dielectric layer, so that the drift region gradually increased along the transverse direction is finally formed, the breakdown voltage of the LDMOS device with the drift region gradually increased along the transverse direction is increased, the on-resistance is not increased too much, and the performance and the reliability of the LDMOS device are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a coordinate system diagram of an ideal doping pattern of a drift region in an LDMOS structure of the present invention;
FIG. 2 is a schematic structural diagram of an LDMOS structure according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an LDMOS structure according to yet another embodiment of the present invention;
FIG. 4 is a flow chart of a method for fabricating an LDMOS structure of the present invention;
FIG. 5 is a schematic structural diagram of step S4 in FIG. 4;
FIG. 6 is a schematic structural diagram of step S5 in FIG. 4;
FIG. 7 is a schematic structural diagram of step S6 in FIG. 4;
fig. 8 is a schematic structural diagram of step S7 in fig. 4.
Description of reference numerals:
1. a semiconductor substrate; 2. a well region; 3. a body region; 4. a gate structure; 41. a polysilicon gate; 42. a gate dielectric layer; 5. a source structure; 6. a drain structure; 7. a drift region; 8. a dielectric layer; 81. doping the dielectric layer; 82. the residual dielectric layer; 9. a barrier layer; 10. a channel.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Lateral Diffusion Metal Oxide Semiconductor (LDMOS) is a semiconductor device with better performance than bipolar transistor, so the application prospect of the lateral diffusion metal oxide semiconductor is relatively better, but the doping distribution of the drift region in the lateral diffusion metal oxide semiconductor directly influences the breakdown voltage and the on-resistance of the lateral diffusion metal oxide semiconductor device, so that the application of the lateral diffusion metal oxide semiconductor is limited. Researchers have studied and made relevant improvements to the doping profile of the drift region, such as stacked LDD structures, dual layer RESURF structures, etc., but these changes have limited effect on the optimization of breakdown voltage and on-resistance.
The applicant has found through research that as shown in fig. 1, which shows one of the ideal doping modes of the drift region in the laterally diffused metal oxide semiconductor, when the doping profile of the drift region is gradually increased from the gate structure to the lateral structure of the drain structure (i.e., the drift region), the breakdown voltage of the laterally diffused metal oxide semiconductor is large and the on-resistance is small.
Example 1:
an LDMOS structure, as shown in fig. 2, comprises a semiconductor substrate 1, preferably, the semiconductor substrate 1 is P-type doped, and the semiconductor substrate 1 is a silicon substrate. The well region 2 is a P-type well region formed by diffusion on the semiconductor substrate 1. The junction depth of the body region 3 is smaller than that of the well region 2, and the body region 3 and the well region 2 are transversely overlapped. A gate structure 4 formed by overlapping a polysilicon gate 41 and a gate dielectric layer 42, wherein the gate dielectric layer 42 covers the surface of the body region 3 and a second side surface of the gate dielectric layer 42 extends to the surface of the well region 2; the surface of the body region 3 covered by the gate dielectric layer 42 is used for forming a channel, the channel is doped in a P-type manner, when the channel is conducted, the channel can extend to the second side surface of the gate dielectric layer 42, and the well region 2 covered by the gate dielectric layer 42 is an accumulation layer region. Preferably, the gate dielectric layer 42 is a gate oxide layer. A source structure 5 comprised of a heavy N + region is formed on the surface of body region 3 and is self-aligned to the first side of gate dielectric layer 42. A drain structure 6, which is comprised of a heavy N + region, is formed on the surface of the well region 2 and near the second side of the gate dielectric layer 42. The doping concentration of the drift region 7 located at the intersection region of the gate structure 4 and the drain structure 6 gradually increases from the gate structure 4 along the lateral direction.
The well region 2 in the junction region of the gate structure 4 and the drain structure 6 is internally provided with a drift region 7, the depth of the drift region 7 is smaller than that of the well region 2, the edges of two ends of the drift region 7 are respectively superposed with the corresponding edges of the gate structure 4 and the drain structure 6, the existence of the drift region 7 improves the accumulation distribution of impurity ions in the well region 2 and the drain structure 6 in the region, improves the distribution uniformity of the impurity ions, reduces the resistance of the surface region of the well region 2 and prevents the influence of a local high-resistance region on threshold voltage, when the LDMOS transistor works, the conduction resistance on a conduction path between the drain region and the source region is reduced, and therefore when the working voltage with the same size as that of the prior art is applied to the drain region, the working current of the LDMOS transistor is increased.
As an optional implementation manner of the embodiment of the present invention, as shown in fig. 3, when the well region 2 in the LDMOS structure is doped N-type, the gate dielectric layer 42 covers the channel 10 formed on the surface of the body region 3 and extends to the second side of the gate dielectric layer 42, so as to avoid the gate dielectric layer 42 overlapping the well region 2 to generate a larger gate-drain parasitic capacitance. It should be noted that, when the well region 2 is doped P-type, the gate dielectric layer 42 may not overlap with the well region 2, which is not limited in the present invention.
Specifically, the value of the rate of change of the doping concentration in the drift region 7 gradually increases in the lateral direction from the gate structure 4 may be constant or non-constant, and the rate of change shown in fig. 1 is constant. The lateral diffused metal oxide semiconductor formed has the advantages of the present invention as long as the doping concentration in the drift region 7 is continuously varied. When the value of the change rate is non-constant, the value of the change rate may be varied arbitrarily with the increase of the doping concentration, for example, the value of the change rate may be varied in a form of constant increase, constant decrease, constant increase or constant decrease.
Example 2:
a method for fabricating an LDMOS structure, as shown in fig. 4, comprises the following steps:
s1, preparing a semiconductor substrate 1, forming a well region 2 in the semiconductor substrate 1, and forming a body region 3 in the semiconductor substrate 1 on one side of the well region 2;
s2, forming a gate structure 4 spanning and covering part of the body region 3 and the well region 2, forming a source structure 5 on the body region 3 on one side of the gate structure 4, and forming a drain structure 6 on the well region 2 on the other side of the gate structure 4;
s3, forming a drift region 7 in the well region 2 in the junction region of the gate structure 4 and the drain structure 6, and forming barrier layers 9 on the well region 2 at two sides of the drift region 7;
in the above step S3, the barrier layer 9 may be a specially designed mask structure, and the mask structure may be one or more of silicon nitride (SiN), silicon oxynitride (SiON), photoresist, and the like. Meanwhile, the blocking layer 9 may be fabricated before the drift region 7, the fabrication sequence of the blocking layer 9 and the drift region 7 is not limited herein, and the blocking layer 9 is not necessarily formed after the well region 2, the body region 3, the gate structure 4, the source structure 5, the drain structure 6, and the like, that is, the sequence of the step of forming the blocking layer in the process flow of fabricating the lateral diffusion metal oxide semiconductor is not particularly limited, and can be adjusted by those skilled in the art according to public benefit requirements. The barrier layer 9 prevents subsequent steps from affecting regions outside the drift region 7.
S4, doping the drift region 7;
in the above step S4, as shown in fig. 5, fig. 5 shows a doping process perpendicular or nearly perpendicular to the drift region 7, and the doping manner used in this process may be conventional doping means such as ion implantation or diffusion.
S5, forming a dielectric layer 8 covering the drift region 7 in the junction area of the gate structure 4 and the drain structure 6;
in the above step S5, as shown in fig. 6, fig. 6 shows that the dielectric layer 8 covers the drift region 7. The dielectric layer 8 is formed at a low temperature, the forming temperature of the dielectric layer 8 can be 50-150 ℃, and the drift region 7 is not affected during low-temperature forming. The dielectric layer formed in this step is called an initial dielectric layer, the initial dielectric layer is undoped or doped, and the doped initial dielectric layer is lightly doped. In this step and subsequent steps, the barrier layer 9 may continue to use the barrier layer formed in step S4, or the barrier layer may be newly formed.
S6, performing tilted ion implantation on the dielectric layer 8 to dope the surface layer of the dielectric layer 8, wherein the doping depth is deeper as the distance from the body region 3 is farther, and forming a doped dielectric layer 81;
in step S6, as shown in fig. 7, fig. 7 shows a process of doping the dielectric layer 8 with oblique ions to form the doped dielectric layer 81. When the oblique ions are implanted, the oblique ions are injected obliquely downwards along the direction from the grid structure 4 to the drain structure 6, and the semiconductor substrate 1 does not rotate in the ion implantation process. The specific tilt angle, the energy and dose of ion implantation, etc. in this step can be determined by those skilled in the art according to the specific process. For example, the angle between the incident direction of the oblique ion and the horizontal direction is 15-60 °, and the ion source for injection is boron difluoride (BF)2) The energy of boron difluoride implantation is 3-30KeV, and the dosage is 1e13-1e14/cm2(ii) a Or the ion source of the tilted ion is boron, the energy of the boron implantation is 3-6KeV, and the dosage is 1e13-1e14/cm2。
S7, etching or etching the doped dielectric layer 81 to form a residual dielectric layer 82 with gradually changing height;
in the above steps, as shown in fig. 8, fig. 8 shows that the doped dielectric layer 81 is etched or etched and removed to form a residual dielectric layer 82. In this step, the etching or etching speed of the initial dielectric layer (undoped or lightly doped dielectric layer) is zero or slower by a wet method or a dry method, while the etching or etching speed of the doped dielectric layer is fast, so as to finally form the residual dielectric layer 82 with gradually changing height, and the height of the residual dielectric layer 82 from the gate structure 4 to the drain structure 6 is gradually reduced. The rate of change when the height of the remaining dielectric layer 82 is gradually changed is not necessarily constant, and may be non-constant as long as the height is continuously changed. When the value of the change rate is an extraordinary number, the value of the change rate may be varied arbitrarily as the altitude decreases, for example, the value of the change rate may be varied in a manner of increasing, decreasing, or increasing and decreasing.
And S8, performing high-temperature annealing on the drift region 7 to form the drift region 7 with the doping concentration gradually increasing from the gate structure 4 along the transverse direction, and removing the residual dielectric layer 82 and the barrier layer 9.
In the above step S8, performing high temperature annealing on the drift region 7 can activate the doped impurities. The high temperature annealing may cause diffusion of impurities, and during the annealing, the impurities in the drift region 7 may diffuse into the remaining dielectric layer 82, and due to the difference in thickness of the remaining dielectric layer 82, the total amount of the diffused impurities at different positions in the drift region 7 may be different, so as to form the drift region 7 with gradually changing doping concentration. The change rate of the doping concentration of the drift region 7 gradually increasing along the transverse direction is not necessarily constant, and may be non-constant, and the purpose of the present invention can be achieved as long as the doping concentration of the drift region 7 continuously changes. When the value of the change rate is non-constant, the value of the change rate may be varied arbitrarily with the increase of the doping concentration, for example, the value of the change rate may be varied in a manner of increasing, decreasing or increasing.
In the steps S1 to S8 described in the above embodiment, the manufacturing method is not limited to be performed in the exact order of the steps, and the order of the steps may be changed appropriately.
According to the scheme, the drift region 7 with the doping concentration gradually changing along the transverse direction from the gate structure 4 is formed through a series of steps, the doping concentration is gradually increased from the gate structure 4, and finally the transverse diffusion metal oxide semiconductor device with large breakdown voltage and without increasing the on-resistance too much is obtained, so that the performance and the reliability of the transverse diffusion metal oxide semiconductor device are improved. Meanwhile, when the doping concentration of the drift region 7 is gradually decreased from the gate structure 4 along the lateral direction, the object of the present invention can be achieved to a certain extent or condition.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims (10)

1. An LDMOS structure, comprising:
a semiconductor substrate (1);
a well region (2) located in the semiconductor substrate (1);
the junction depth of the body region (3) is smaller than that of the well region (2), and the body region (3) and the well region (2) are transversely overlapped;
the gate structure (4) comprises a polysilicon gate (41) and a gate dielectric layer (42) which are formed in an overlapping mode, the gate dielectric layer (42) covers the surface of the body region (3), and the second side face of the gate dielectric layer (42) extends to the surface of the well region (2);
the source electrode structure (5) is positioned on the surface of the body region (3) and aligned with the first side face of the gate dielectric layer (42);
the drain electrode structure (6) is positioned on the surface of the well region (2) and close to the second side surface of the gate dielectric layer (42);
and the drift region (7) is positioned in the junction area of the gate structure (4) and the drain structure (6), and the doping concentration of the drift region is gradually increased from the gate structure (4) along the transverse direction.
2. The LDMOS structure of claim 1, wherein a rate of change of the doping concentration of the drift region (7) in laterally increasing increments from the gate structure (4) varies with increasing doping concentration.
3. A method for manufacturing an LDMOS structure, based on the LDMOS structure of claim 1, comprising the following steps:
forming a well region (2) in the semiconductor substrate (1), and forming a body region (3) in the semiconductor substrate (1) on one side of the well region (2);
forming a gate structure (4) which spans and covers part of the body region (3) and the well region (2), forming a source structure (5) on the body region (3) on one side of the gate structure (4), and forming a drain structure (6) on the well region (2) on the other side of the gate structure (4);
forming a drift region (7) positioned in the well region (2) in the junction region of the gate structure (4) and the drain structure (6), and forming barrier layers (9) positioned on the well region (2) on two sides of the drift region (7);
-doping the drift region (7);
forming a dielectric layer (8) covering the drift region (7) in the junction area of the gate structure (4) and the drain structure (6);
performing inclined ion implantation on the dielectric layer (8) to dope the surface layer of the dielectric layer (8), wherein the doping depth is deeper along with the distance from the body region (3), and forming a doped dielectric layer (81);
etching or etching the doped dielectric layer (81) to form a residual dielectric layer (82) with gradually changing height;
and carrying out high-temperature annealing on the drift region (7) to form the drift region (7) with the doping concentration gradually increasing from the gate structure (4) along the transverse direction, and removing the residual dielectric layer (82) and the barrier layer (9).
4. A method for fabricating an LDMOS structure as claimed in claim 3 wherein during the tilted ion implantation, the tilted ions are incident obliquely downward along the direction from the gate structure (4) to the drain structure (6), the incident direction of the tilted ions having an angle with the horizontal direction.
5. The method of fabricating an LDMOS structure of claim 4, wherein the included angle is 15-60 degrees.
6. The method as claimed in any of claims 3 to 5, wherein the ion source of the tilted ions is boron difluoride implanted with an energy of 3 to 30KeV and a dose of1e13-1e14/cm2(ii) a Or
The ion source of the tilted ions is boron, the energy of the boron implantation is 3-6KeV, and the dosage is 1e13-1e14/cm2。
7. The method for fabricating the LDMOS structure of claim 3, wherein the dielectric layer (8) is an initial dielectric layer after the forming and before the tilted ion implantation, and the initial dielectric layer is doped.
8. The method for manufacturing the LDMOS structure of claim 3, wherein when a dielectric layer (8) covering the drift region (7) is formed in a junction region of the gate structure (4) and the drain structure (6), the forming temperature of the dielectric layer (8) is 50-150 degrees.
9. A method for fabricating an LDMOS structure as claimed in any one of claims 3-5 and 7-8, wherein the rate of change of the doping concentration of the drift region (7) in a lateral direction gradually increasing from the gate structure (4) varies with the increase of the doping concentration.
10. The method for fabricating the LDMOS structure of any of claims 3-5 and 7-8, wherein a rate of change of the height of the residual dielectric layer (82) varies with the height.
CN202010805199.0A 2020-08-12 2020-08-12 LDMOS structure and manufacturing method thereof Active CN111969061B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010805199.0A CN111969061B (en) 2020-08-12 2020-08-12 LDMOS structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010805199.0A CN111969061B (en) 2020-08-12 2020-08-12 LDMOS structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN111969061A true CN111969061A (en) 2020-11-20
CN111969061B CN111969061B (en) 2024-06-04

Family

ID=73364354

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010805199.0A Active CN111969061B (en) 2020-08-12 2020-08-12 LDMOS structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN111969061B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115863397A (en) * 2023-01-19 2023-03-28 北京智芯微电子科技有限公司 Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420262B1 (en) * 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
US6897525B1 (en) * 1998-11-26 2005-05-24 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US20060145250A1 (en) * 2005-01-06 2006-07-06 Infineon Technologies North America Corp. LDMOS transistor
CN101036231A (en) * 2004-09-16 2007-09-12 飞兆半导体公司 Enhanced RESURF HVPMOS device with stacked hetero-doping rim and gradual drift region
CN101399288A (en) * 2008-10-23 2009-04-01 北京时代民芯科技有限公司 LDMOS chip light doped drift region structure and forming method
CN101777582A (en) * 2010-01-12 2010-07-14 上海宏力半导体制造有限公司 LDMOS device capable of improving grid oxygen reliability and manufacture method thereof
JP2011210743A (en) * 2010-03-17 2011-10-20 Asahi Kasei Electronics Co Ltd Semiconductor device
US20110303979A1 (en) * 2010-06-10 2011-12-15 Kabushiki Kaisha Toshiba Semiconductor device
CN102365714A (en) * 2009-01-30 2012-02-29 先进微装置公司 Graded well implantation for asymmetric transistors having reduced gate electrode pitches
CN103050540A (en) * 2012-12-20 2013-04-17 电子科技大学 Low-ratio on-resistance transverse power device using high-dielectric-constant groove structure
US20140159153A1 (en) * 2012-12-07 2014-06-12 Shanghai Huahong Grace Semiconductor Manufacturing Corporation Rf ldmos device and method of forming the same

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6897525B1 (en) * 1998-11-26 2005-05-24 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing the same
US6420262B1 (en) * 2000-01-18 2002-07-16 Micron Technology, Inc. Structures and methods to enhance copper metallization
CN101036231A (en) * 2004-09-16 2007-09-12 飞兆半导体公司 Enhanced RESURF HVPMOS device with stacked hetero-doping rim and gradual drift region
US20060145250A1 (en) * 2005-01-06 2006-07-06 Infineon Technologies North America Corp. LDMOS transistor
CN101399288A (en) * 2008-10-23 2009-04-01 北京时代民芯科技有限公司 LDMOS chip light doped drift region structure and forming method
CN102365714A (en) * 2009-01-30 2012-02-29 先进微装置公司 Graded well implantation for asymmetric transistors having reduced gate electrode pitches
CN101777582A (en) * 2010-01-12 2010-07-14 上海宏力半导体制造有限公司 LDMOS device capable of improving grid oxygen reliability and manufacture method thereof
JP2011210743A (en) * 2010-03-17 2011-10-20 Asahi Kasei Electronics Co Ltd Semiconductor device
US20110303979A1 (en) * 2010-06-10 2011-12-15 Kabushiki Kaisha Toshiba Semiconductor device
US20140159153A1 (en) * 2012-12-07 2014-06-12 Shanghai Huahong Grace Semiconductor Manufacturing Corporation Rf ldmos device and method of forming the same
CN103050540A (en) * 2012-12-20 2013-04-17 电子科技大学 Low-ratio on-resistance transverse power device using high-dielectric-constant groove structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115863397A (en) * 2023-01-19 2023-03-28 北京智芯微电子科技有限公司 Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit
CN115863397B (en) * 2023-01-19 2023-04-21 北京智芯微电子科技有限公司 Lateral double-diffusion field effect transistor, manufacturing method, chip and circuit

Also Published As

Publication number Publication date
CN111969061B (en) 2024-06-04

Similar Documents

Publication Publication Date Title
CN101030602B (en) MOS transistor for decreasing short channel and its production
KR101215876B1 (en) Semiconductor device having enhanced performance and method
CN111968916B (en) Manufacturing method of LDMOS structure
CN101399288B (en) LDMOS chip light doped drift region structure and forming method
KR101332590B1 (en) Power semiconductor device having improved performance and method
US9608057B2 (en) Semiconductor device and method for manufacturing semiconductor device
US9184278B2 (en) Planar vertical DMOS transistor with a conductive spacer structure as gate
CN102891180B (en) Semiconductor device comprising MOSFET device and manufacturing method
CN103378134B (en) Grid structure and formation method, semiconductor structure and formation method
US7701001B2 (en) Short channel trench power MOSFET with low threshold voltage
US7208785B2 (en) Self-aligned Schottky-barrier clamped planar DMOS transistor structure and its manufacturing methods
US20200235237A1 (en) Ldmos device and method for manufacturing same
CN103050536A (en) Radio frequency LDMOS (laterally diffused metal oxide semiconductor) device and manufacture method thereof
CN111969061B (en) LDMOS structure and manufacturing method thereof
CN104599974A (en) Semiconductor structure and forming method thereof
TW200304188A (en) Semiconductor component and manufacturing method
CN102522338B (en) Forming method of high-voltage super-junction metal oxide semiconductor field effect transistor (MOSFET) structure and P-shaped drift region
US8039330B2 (en) Method for manufacturing semiconductor device
CN104409500A (en) Radio frequency LDMOS (lateral diffused metal oxide semiconductor) and manufacturing method thereof
CN111554579B (en) Switch LDMOS device and manufacturing method thereof
CN204464292U (en) Semiconductor structure
CN102446717A (en) Method for reducing damage of semiconductor device caused during hot carrier injection
KR100900145B1 (en) Method for manufacturing a transistor
CN114361015A (en) Method for preparing silicon carbide power device based on shallow source region injection
CN118099210A (en) Manufacturing method of trench gate power device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant