KR20020006583A - Improved bicmos process with low temperature coefficient resistor(tcrl) - Google Patents

Abstract

PURPOSE: A polysilicon thin film with a low temperature coefficient of resistor is provided to reduce a temperature coefficient to resistance by implanting ions into a polysilicon layer as an insulation layer which is laminated in an integrated circuit, changing a resistance and damaging the polysilicon layer, and annealing it at a specific temperature. CONSTITUTION: When a TCRL(temperature coefficient to resistance) area is formed, a protection oxide to protect etching is laminated on an emitter polysilicon layer(132). Then, BF2 implanting substance is non-selectively implanted into the polysilicon layer. Finally, the substrate is covered with a protection oxide, a TCRL is covered with a photo resist, and then it is etched by an appropriate size. The implantation to a resistor is activated during annealing at 900 deg.C, and the final doping shape of a bipolar device(200) and a MOS device is set. Thus, an amorphous silicon film can be laminated, and its resistivity can be adjusted by adding a dopant.

Description

IMPROVED BICMOS PROCESS WITH LOW TEMPERATURE COEFFICIENT RESISTOR (TCRL)}

This application is part of US Patent Application Serial No. 09 / 345,929, filed July 1, 1999.

Advanced wireless communication products require high performance, high integration, low power, and low cost integrated circuit technologies. For wireless devices up to several gigahertz (GHZ), silicon BiCMOS technology is particularly suitable to meet these needs. Among the extreme importance for RF design is the availability of high quality passive components. In particular, it is desirable to form thin film resistors having a low temperature coefficient of resistance (TCRL).

Unfortunately, existing techniques for polysilicon thin film resistors have the problem that thin film resistors having a relatively high temperature coefficient of resistance must be produced.

1 to 19 are cross-sectional views illustrating sequential steps for forming a TCRL in a BiCMOS process.

20 to 25 are graphs showing experimental results of the TCRL, respectively.

26 is a more detailed cross-sectional view of an NpN bipolar device formed in the BiCMOS process of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: Substrate

11: epitaxial region

12.1, 12.2: N + buried layer area

20: trench photoresist mask

21: trench

22: P + channel stop

50: transition region

51: pad oxide layer

52: N + sinker

63: implant

70.1, 70.2: sidewall spacers

90: CMOS nitride protective layer

The present invention provides a polysilicon thin film low temperature coefficient resistor and a method of manufacturing the resistor that overcomes the resistance coefficient problem of the prior art, while simultaneously reducing the steps from the BiCMOS manufacturing process, optimizing the bipolar design tradeoff, and Improve device isolation. In the method of the present invention, TCRL is formed on an insulating layer, which is typically silicon dioxide or silicon nitride. The layer has relatively high concentrations of one or more kinds of dopant and a significant amount of unannealed implant damage. Polysilicon is implanted with one or more kinds of ions. However, in contrast to the prior art methods, the implanted resistors of the present invention are annealed less than conventional conventional implanted resistors, leaving some intended annealed damage in the resistors. The damage results in a higher resistance TCRL without increasing its resistance coefficient. Therefore, even when the temperature increases, the relative value of the resistance is maintained as it is. As such, the resistors of the present invention are more precise than others produced by current methods, and can be used where suitable for precision conditions for high quality RF devices. This resistor fabrication process combines several spacer oxide deposits, provides a buried layer with different diffusion coefficients, couples double dielectric trench sidewalls like a polishing stop, and precisely controls emitter-base size. It is used to supply structures and to integrate bipolar and CMOS devices with compromises that may be bushed onto either.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

All figures show the side divisions of the CMOS region 100, the bipolar NPN region 200, and the region of the substrate of the transition region 150 between the CMOS and bipolar regions. Region division is shown by dashed lines.

In FIG. 1, the top surface of the P-type substrate is covered by a suitable ion implantation mask, such as photoresist, heat-growth oxide, or deposition oxide. Openings are formed in the resist mask to form N + buried layer regions 12.1 and 12.2. The regions are implanted with N-type implants such as arsenic. The implantation mask is then removed.

The substrate is then covered with a second suitable ion implantation mask, such as deposited oxide, thermally grown oxide or photoresist. An opening is made in the mask to define another buried layer region, and a second N-type dopant having a very different diffusion coefficient than the first is implanted. Two different buried layer dopants allow the fabrication of transistors with various collector profiles and are tailored for address speed versus breakdown voltage tradeoffs in RF devices. Two different collector profiles connected by the use of an optionally implanted collector define an integrated circuit with four NPN elements.

The N + buried layers 12.1 and 12.2 are subjected to appropriate annealing treatments, and an N-type epitaxial layer is grown on top of the substrate 10. As a result, the substrate 10 is patterned into the CMOS region 100, which is separated from the bipolar NPN region 200 by the transition region 150. N-type buried layers are formed below an area that can receive P-type wells. No buried layers are needed for the N-type wells.

In Fig. 2, an initial trench formation step is shown. Isolation trenches are formed between the transition region 150 and the NPN transistor region as well as in other regions necessary for improved lateral isolation. The trench photoresist mask 20 is uniformly coated on the substrate 10 and then pattern formed. The photoresist is developed to expose the trench regions 21. By suitable wet or dry etching, the trenches 21 are etched to a height below the N + buried layer 12.1, 12.2. The bottom of the trenches is then injected with an appropriate P + channel stop 22.

As shown in FIG. 3, the next step includes removing the photoresist 20 performing thermal oxidation on the trench sidewalls and depositing and patterning a sidewall dielectric layer 23, such as a nitride layer. do. Oxide layer 23 is strengthened and provides a polishing stop for planarization. In this layer, nitride is characterized by almost matching thermal properties of silicon. The layer is formed to a thin thickness sufficient to prevent any protrusion of the trench cavity, thereby allowing for complete trench fill in subsequent deposition steps. Oxide layer 23 also provides pad oxide for LOCOS in a later step. The combination of thermal oxidation, nitride deposition, and nitride tightness allows the trench sidewalls to match the thermal expansion ratio of the silicon substrate.

Since the alternate embodiment deposits the sidewall dielectric layer in that way, sequential trench filling occurs to form a space in the trench below the surface of the silicon substrate. This feature provides stress relief and eliminates the occurrence of silicon defects in the silicon adjacent to the trench.

A polysilicon deposition step is then performed on the substrate 10 to deposit the polysilicon layer 24 on the substrate 10 and the epitaxial layer and to fill the trenches 21. Undoped polysilicon filling is a semi-insulating material, which provides desirable electrical properties for RF vortex capacitance.

4 shows completed trenches. Substrate 10 and epitaxial layer 11 are planarized by removing thermal oxide layer 23 and polysilicon layer 24 from the surface of substrate 10 in all regions except the tops of the trenches. Such planarization is achieved by conventional chemical mechanical polishing operations. Nitride under polysilicon acts as a hard stop during polishing operations, protecting it from damage to underlying oxides and silicon. The thinness of the oxides of oxides and the polished trench polysilicon surface reliably give a precise match with the original silicon surface.

During the formation of CMOS devices, it is important to cover the NPN region 200 and protect the trenches 21. Similarly, combining as many CMOS and bipolar processing steps as possible is the goal of the process. Thus, referring to FIG. 5, the trenches are initially protected from subsequent CMOS processing steps. Such protection includes forming a pad oxide layer 51 over the trenches. The pad oxide layer 51 is followed by N + sinker photoresist deposition, patterning, and implantation to form an N + sinker 52 that later becomes a collector of the NPN transistor 200. Next, a silicon nitride layer 54 is deposited over the pad oxide layer 51 on the surface of the substrate 10 and the epitaxial layer 11. Silicon nitride is initially patterned to expose local oxidation (LOCOS) region 50. Following such LOCOS patterning, LOCOS region 50 is formed by conventional LOCOS processing, which allows for lateral surface isolation of NMOS and PMOS devices 100 and also provides sinker diffusion ( 52 is separated from the remaining NPN transistor 200. Silicon nitride is removed from the remaining surfaces of the substrate 10 and the epitaxial layer 11 except for the upper region of the trench 21.

In the LOCOS operation, a skin layer of silicon dioxide forms on the surface of the nitride oxide mask. The skin layer is patterned using conventional photoresist and wet etching while remaining in trench region yarns. After photoresist removal, the nitride is removed by appropriate wet etching except for areas on the trench 21. The use of this oxide layer is thus fully positive for the pad oxide and silicon substrate regions, which underlie the protection of the trench space and removal of nitride at the same time. Protecting these regions from further stress-generated thermal oxidation is important for the successful fabrication of shallow transistor structures, which are disclosed in US Pat. No. 5,892,264.

The pad oxide layer is then removed from the surfaces of epitaxial region 11 and substrate 10 to expose the surface for subsequent formation process.

In the next step, as shown in FIG. 6, sacrificial oxidation takes place on the surface of the epitaxial layer 11. Such oxidation is a common first step in the formation of P-wells and N-wells for the CMOS device 100. Suitable photoresist masks and implants 62 provide P-wells and N-wells for a CMOS device. Heavier P-type implants provide a junction isolation that separates PMOS and NMOS devices. Following removal of the sacrificial oxide, the gate oxide layer 65 is usually a thermal oxide layer grown on the surface of the epitaxial layer 11. This step is followed by uniform deposition of the polysilicon layer 66, which is then patterned and doped to form the polysilicon gates 66.

The next step in the fabrication of CMOS transistors is shown in FIG. Next, the NMOS and PMOS drains are typically lightweight-doped drain implants 72 to be able to form N-type lightly-doped drain regions and P-type lightly-doped drain regions. N) or (74; P) (P-type implants are not shown here), respectively. In the annealing step, lightly doped drain regions are driven slightly below the sidewalls of the gates. Lightly doped drain regions use sidewalls of the gate as masks. The regions are self-aligned by conventional methods using gates as masks, followed by appropriate P- and N-type implants. Following such steps, in regions not shown in the figures, conventional P + resistors are formed in the N-type epitaxial region 11 using suitable photoresist and implant. NPN protective spacer oxide layer 78 is uniformly deposited over epitaxial layer 11. The spacer oxide layer 78 covers the NPN region 200 and the transition region 150 of the layer 11. Without this spacer oxide cover, subsequent CMOS processing steps will interfere with the formation of the NPN transistor. The spacer oxide layer over the gate 66 is patterned and then removed, leaving sidewall spacers 70.1 and 70.2 at the corners of the gate 66.

The spacer oxide layer 78 provides sidewall spacers for CMOS devices, as well as surface isolation and hard mask for the active members of the NPN transistors. By performing the deposition step early in the process, one or more deposition and masking processes are saved during later processing. As a result, spacer oxide layer 78 forms a mask for self-aligned sources and drains of CMOS devices and a mask for collector and emitter openings 126 and 127, respectively. do. After this see FIG. 12 for process effects.

Subsequent CMOS processing steps are shown in FIG. 8. A screen oxide layer 80 is deposited and patterned to cover the lightly doped source and drain regions of the CMOS device. The regions are then implanted with P + or N + ions to form the sources 81 and the drains 82. Then, each of the P-type and N-type sources and drains is subjected to an annealing process in which the diffusion time can adjust the depth of the sources and drains. While the figure only shows one MOS device, the process disclosed herein is used to form multiple transistors including multiple NMOS, PMOS, and bipolar devices.

In the process after the formation of the CMOS transistors is completed, NPN transistors are manufactured while the CMOS transistor is protected. As a first step, as shown in FIG. 9, a CMOS nitride protective layer 90 is uniformly deposited over the epitaxial layer 11. On top of the nitride protective layer, a CMOS oxide protective layer 92 is deposited. Since the two protective layers can be selectively etched with respect to each other, the combination of nitride and deposited oxide layers in two successive steps, by using the two layers as different etch stops, results in a substantial number of subsequent treatments. Save steps

A photoresist layer 94 is deposited and then patterned to cover the CMOS devices and at least a portion of the LOCOS region extending from the transition layer 150 into the CMOS region 100. The CMOS oxide protective layer 92 and the nitride protective layer 90 are removed from the exposed NPN region 200 using a suitable wet etch. As a result of the successive etching processes, the spacer oxide layer 78 is exposed as shown in FIG. 10.

Referring to FIG. 11, the photoresist layer 110 is uniformly deposited on the spacer oxide layer 78 and then patterned to form openings 112 and 114 in the NPN section 200. When the photoresist layer 110 is in place, the spacer oxides of the exposed regions 112 and 114 are removed to expose the surface of the sinker diffusion 52 and the surface of the subsequent NPN transistor 200.

In the process of forming an NPN transistor, an extrinsic base is formed first, followed by an intrinsic base, and finally an emitter. The exogenous base comprises a layer of layers deposited on the epitaxial layer 11. 12, the layers are doped polysilicon layer 120, tungsten silicide layer 121, polysilicon cap layer 122, inter-poly oxide layer oxide layer 123, and titanium nitride anti-reflective coating 124. After the polysilicon layer 120, WSi layer 121 and polysilicon cap 122 layers have been deposited, subsequent implantation of boron to form doping into the exogenous base 222 is involved. A polysilicon cap layer is included to prevent boron doping from being severely separated on top of the poly / WSi layer and from diffusing to the silicon to form an exogenous base. It also prevents accidental sputtering of the WSI layer upon boron implantation, but can potentially contaminate the implantation tool with heavy metals.

The bundle of layers stacked as above is suitably patterned to form emitter openings 127. As a result of the heat treatment, dopants from layer 120 form an exogenous base 222. Intrinsic base 220 is formed by implanting additional boron through the emitter opening. In addition, while the patterning mask for the bundle is still located, SIC (optionally injected collector) injection 224 is made through intrinsic base 220 and emitter opening 127. Bundle pattern masks help mask high energy SIC implantation and form the perfect self alignment of the SIC in the transistor. SIC implantation is in contact with the N + mem layer 12.2. The SIC implant 224 is annealed, the emitter surface is oxidized, and the P-type implant forms 220 an intrinsic base.

Referring to FIG. 13, a base spacer oxide layer 130 is deposited to mask the base region. The nitride spacer layer 131 is deposited and then etched to open the emitter region. The spacer oxide is etched with a suitable hydrofluoric acid. The structure of the composite spacer allows emitter to exogenous base spacing, and therefore the speed versus yield device tradeoff is easily diversified by converting nitride spacer deposition thickness, base spacer oxidation to etch time, or both. The emitter polysilicon layer 132 is then deposited and etched to form an emitter contact 134 and collector contact 133. In the subsequent annealing treatment (see FIG. 17), the N-type dopants from the emitter polysilicon layer 132 diffuse into the surface of the epitaxial layer 11, causing the collector surface contact and emi of the NPN transistor 200. Form the ground.

14 and 15 illustrate the process of forming a polysilicon resistor having a relatively low temperature coefficient of resistance (hereinafter referred to as TCRL) resistor 141. As a first step, a protective oxide layer 140 is deposited over the emitter polysilicon layer 132. The layer of oxide protects all exposed emitter silicon layer 132 from etching when TCRL regions are formed. Polysilicon layer 142 is deposited in opening 300. Next, a BF ₂ implant 143 is implanted into the polysilicon layer. Finally, the TCRL layer 141 is coated with photoresist and then etched to the appropriate size. Next, as shown in FIG. 15, the TCRL layer 141 is covered with a protective oxide layer 144. The oxide layer is suitably patterned and masked while exposing the contact area of the resistor to protect the portion of the TCRL layer 141 beneath it. The TCRL poly layer is later deposited in the process. As such, the resistivity can be adjusted by adding a dopant after depositing the amorphous silicon film.

The manufacturing process forms a TCRL resistor 141 having a resistance of 750 mA /? And a temperature resistance coefficient of less than 100 parts per million (ppm). The resistor uses a non-selective BF ₂ implant. By doping the polysilicon layer. In the 900 ° C. rapid thermal annealing (RTA) step, the resistor implant is activated and final doping profiles for the bipolar and MOS devices 200, 100 are established. It will be appreciated that the TCRL multilayer is deposited during subsequent processing. The process of the present invention adjusts the film's resistance by depositing an amorphous silicon film and adding dopants. Non-selective BF ₂ implants are used to dope the membrane. A mask is used to remove oxides from all contact regions, and in the 900 ° C RTA step, resistor implants are activated to perform final doping. Thus, resistor contacts are siliconized prior to final back end processing.

TCRL resistor 141 has a resistance independent of temperature sensitivity. In the prior art, it has been known that the higher the resistance, the greater the temperature sensitivity. However, we are 750 Ω /? Attempts have been made to separate these two properties by providing a relatively thin film that has been tuned to have a resistance up to. As a result, it was observed that as the BF ₂ implant approached a higher level, an increase in resistance was anticipated, which was not anticipated. This phenomenon was not observed when only boron was used to dope the film. In general, it is known that the higher the implant level, the less the resistance will increase but decrease. In the view of the inventors of the present application, heavier ions (BF ₂ ) at a high dose (injecting impurities into the semiconductor by a method such as implantation) cause a large amount of damage to the polysilicon film, Such damage appears to be relatively low temperature (900 ° C.) for activating the implants and is not cured by short thermal annealing (RTA). The implant damage clearly creates additional trapping sites for carriers that result in increased resistance at higher implant doses. A similar result is caused by the mutual implantation of different ions, which shows that the sources and drains of MOS devices or emitters for low resistance exogenous bases for NPNs or emitters for PNPs, even higher In order to be able to produce value resistors, it becomes possible to use boron implants of equally high dose. In a preferred embodiment of the present invention, the polysilicon layer 142 has a thickness of 70 nanometers (nm), which may range from 65 nm to 75 nm. The implant concentration of the boron ions 142 is 1.3 × 10 ¹⁶ and may be in the range of 9 × 10 ¹⁵ to 1.5 × 10 ¹⁶ .

At the beginning of the phenomenon of the present invention, three film thicknesses with intermediate boron doses were selected for evaluation. As shown in Table 1, the thinnest film was found to be closest to our target of 750 kW / ?. However, the TCRs of all cells were above the 100 ppm target. In the second set of experiments, ten or more implant doses were changed with the expectation that higher doses would result in lower sheet resistance and lower TCRs, while maintaining the film thickness in a thin setting.

Rs and TCR by thickness thickness Rs TCR Thin case 650 228 Middle case 532 238 Thick case 431 292

Initially, as indicated in Fig. 20, there is almost no change in flake resistance and TCR even when the dose is increased. However, as the implant level approaches the highest level, an unexpected increase in resistance is observed, during which the TCRs experience a sharp decrease until they become negative at the highest dose.

Method and Device Characteristics for a 30-Gigats Helms Feet Submicrometer Double Poly-Si Bipolar Technology Using BF2-Injection Base by Rapid Heat Treatment by Yamaguchi et al., Published by IEEE TED in August 1993. According to "Characterization for a 30-GHz ft Submicrometer Double Poly-Si Bipolar Technology Using BF2-Implanted Base with Rapid Thermal Process", Yamaguchi et al. Observed the same relationship between TCR and flakes. According to their study, the TCR of boron-doped P-type polysilicon resistors made to have a 150 nm amorphous layer approaches zero at a flake resistance of 600 to 800 mA / ?. However, within the range of doses in the cited investigation, the resistance decreases with increasing boron doses.

In parallel experiments aimed at reducing TCR, boron and boron plus other factors (BF ₂ ) are injected into the film of medium thickness. The implant factors are adjusted to compensate for different ranges of factors. Once again, the results were totally unexpected: The average resistance of boron itself was 200 mA /? When the values of BF ₂ resistors were 525 and 221, respectively, and a TCR of 445 ppm.

Based on such results, it is estimated that heavier ions and extremely high doses cause a large amount of damage in the polysilicon film so that it cannot be cured by a relatively short 900 ° C RTA. Such damage creates additional trapping regions for the carriers, resulting in increased resistance at higher implant doses. Thus, a similar result is caused by the mutual implantation of different ions, according to which the emitters for PNPs as well as emitters for sources and drains or low resistance exogenous bases for NPNs, even It is believed that it will be possible to use boron implants of the same high dose to be able to produce higher value resistors.

Table 2 shows the effect of RTA temperature on TCR and flake resistance as a function of implant dose. Once again, the higher flake resistances obtained by the lower temperature cause a reduction in TCR except at lower doses with a resistance of 763 and a TCR of 168.

It provides support for the theory that the main part of the TCR behavior observed above is damage. As the RTA temperature is lowered, the activation of the carrier is suppressed and the flakes are advanced. At the same time, annealing of implant damage is reduced. At low doses, however, there is insufficient implant damage to deteriorate the carrier behavior up to the point where it becomes less sensitive to temperature changes.

Dose Star Rs, TCR, and RTA Temperatures Dose Rs TCR RTA that 637 293 900C that 763 168 800C medium 628 271 900C medium 849 76 800C Go 726 90 900C Go 832 22 800C

CHARACTERIZATION RESULTS

21 is a scatter plot of a 30 x 30 micron resistor showing the relationship of TCR to flake resistance when 50 ° C is selected as the lowest measurement point. TCR is calculated by matching (selecting) one line to values measured in the range of 50 to 125 ° C. at 25 ° intervals. The dashed lines represent the goals set for the present manufacturing process.

The parts by two different runs are bundled and measured from -50 ° C to 150 ° C. FIG. 22 shows the average change in flake resistance for the nine parts measured in that temperature range, and FIG. 23 shows the plot of TCRs calculated for that set of measurements. The dotted line represents the polynomial fit, while the solid line represents the linear fit. The upward "hook" observed at low temperatures is common in the case of diffused resistors.

Since matching is of particular interest to analog and mixed signal designers, FIG. 24 shows the mismatch percentage as a function of the length for a fixed width of the resistor, and FIG. 25 is a function of the width for a fixed length. Represent the same variable. As expected, the data shows an improvement in matching with increasing dimensions.

The possibility of producing high value polysilicon resistors with low TCR has been demonstrated. The study uncovered a secret about the relationship between ion species, flake resistance, and TCR, which could reduce the complexity of the manufacturing process. Since 800 ° C. is a good temperature for the bipolar manufacturing process of the present invention, it is also possible if it is desirable to separate the resistor activation step from the RTA used to set the electrical parameters of the device.

As bipolar and TCRL components are processed at this point, the remaining metallization work is performed on all devices, as it is now appropriate to remove the protective layer from the CMOS portion of the pancreaper. Referring next to FIG. 16, the TCRL resistor 141 and the NPN transistor region 200 are protected by the photoresist layer 160. The photoresist is patterned to open the top region of the CMOS device 100. Next, the protective oxide layer 92 (see FIG. 15) is removed.

Referring to FIG. 17, the photoresist layer 160 is removed, followed by the protective nitride layer 90. In that case, the RTA step is applied to the emitter and resistor 141. The step is carried out at about 900 ° C. for 0.5 minutes and completes the previously prepared emitter preparation in the step already shown in FIG. 13.

The screen oxide layer 80 over the lightly doped source and drain regions of the CMOS device is then removed, and in FIG. 18, the exposed polysilicon regions, gate 66, and emitter and collector of resistor 141. Contacts 134 and 133 are silicided by platinum 180 to form a layer of platinum silicide on the exposed polysilicon. As shown in FIG. 19, sidewall spacer oxide 190 is applied to the sidewalls of emitter and collector contacts 134, 133. The remainder of the spacer oxide is etched away. Subsequently, suitable metallization layers are formed on the substrate, where the three metal layers are separated from each other by suitable insulating layers and each other by the formation of vias filled with a conductive material. Separate layers that are selectively connected to are included. After metallization is performed, the entire device is covered with a passivation layer, usually silicon nitride, and the substrate and the integrated circuits and devices formed thereon are subjected to subsequent processing for testing and assembly.

The low temperature coefficient resistor (TCRL) has an ion implantation damaged portion that is not recovered. The damage increases resistance and makes the resistor less sensitive to changes in operating temperature. The polysilicon thin film low temperature coefficient resistors and the method for their manufacture process overcome the resistance coefficient problems of the prior art while simultaneously reducing the steps from the BiCMOS fabrication process, optimizing the bipolar design tradeoff, and providing passive device isolation. Improve. In the process of the present invention, TCRL is formed on an insulating layer, which is typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of one or more kinds of dopants. With a significant amount of unannealed implant damage. The annealing process is used for implanted resistors that are shorter than conventional sidewall implanted resistors, leaving the intended unannealed damage in the resistor. The damage results in a higher resistance TCRL without increasing its resistance coefficient. Therefore, even when the temperature increases, the relative value of the resistance is maintained as it is. The resistor fabrication process combines several spacer oxide deposits, provides a buried layer with different diffusion coefficients, couples double dielectric trench sidewalls like a polishing stop, and precisely controls emitter-base size. It is used to supply structures and to integrate bipolar and CMOS devices with compromises that may be bushed onto either.

Claims (35)

In integrated circuits, polysilicon precision resistors An insulating layer covering the substrate; And And a polysilicon layer deposited on said insulating layer, said polysilicon layer having a relatively high dopant concentration and characterized by a significant amount of unannealed implant damage. 2. The integrated circuit of claim 1 wherein the thickness of the polysilicon layer is in the range from 65 nm to 75 nm. The integrated circuit of claim 1, wherein the sheet resistance of the polysilicon layer is in the range of 725 ohm / square to 850 ohm / square. The integrated circuit of claim 1, wherein the polysilicon layer has a resistance temperature coefficient (TCR) in a range of 20 to 100 parts per million (ppp). A method of manufacturing a polysilicon precision resistor in an integrated circuit, Depositing an insulating layer on the integrated circuit; Depositing a polysilicon layer on the insulating layer; Implanting ions into the polysilicon layer to change the resistance of the polysilicon layer and damage the polysilicon layer; And Adjusting the annealing of the polysilicon layer to reduce the resistive temperature coefficient of the polysilicon resistor. The method of claim 5 wherein the annealing temperature is in the range from 900 ° C. to 800 ° C. 7. 6. The method of claim 5 wherein the implantation energy of ions is in the range of 10 to 3.5 KeV. 6. The method of claim 5, wherein the thickness of the polysilicon layer is in the range from 65 nm to 75 nm. 6. The method of claim 5 wherein two or more ions are implanted into the polysilicon. 6. The method of claim 5 wherein boron is one of the ions. A method of forming an integrated circuit having MOS devices and bipolar devices in a semiconductor substrate, the method comprising: Forming a trench in the substrate separating the bipolar device from the MOS regions; Forming one or more partial oxide regions on the surface of the semiconductor to surface isolate the NMOS from PMOS devices and also to isolate the collector regions from emitter and base regions; Depositing an oxide layer on the substrate; Covering and patterning a deposited oxide layer forming the sidewall spacers at the edge of the gate of the MOS device, protecting the bipolar region from damage while the MOS device is in chemical operation; Patterning the openings for the collector contacts and the remaining spacer oxide layer that determines the base and emitter regions after the chemical operation of the MOS device is complete. 12. The method of claim 11, further comprising implanting sources and drains of MOS devices and self-aligning the sources and drains using the sidewall spacers at the corners of the gate. How to. A method of forming an integrated circuit having a MOS device region and a bipolar device region in a semiconductor substrate, the method comprising: Forming a trench in the substrate separating the bipolar device from the MOS regions; Forming one or more partial oxide regions on the surface of the semiconductor to surface isolate the NMOS from PMOS devices and also to isolate the collector regions from emitter and base regions; Substantially completing the formation of the MOS devices; Covering the substrate with a silicon nitride layer; Covering said silicon nitride layer with a deposited oxide layer; And Maintaining the integrity of the silicon nitride layer and the deposited oxide layer over the CMOS device regions, and selectively removing one or more portions of the silicon nitride layer and the deposited oxide layer over the bipolar device region, thereby forming bipolar devices. Method comprising a. In the method of forming an integrated circuit having a MOS device and a bipolar device of a single semiconductor substrate, Forming a first buried layer with a first dopant having a first diffusion coefficient below one of the MOS devices or the bipolar devices; Covering the first investment layer with a mask; Forming a second buried layer with a second dopant having a second diffusion coefficient under the other of the MOS device or the bipolar device; Selectively implanting one or more collectors of bipolar elements providing an integrated circuit of two or more bipolar elements having different doping profiles. 15. The method of claim 14, wherein the double buried layer is doped as N-type. 15. The method of claim 14, wherein the double buried layer is doped in a P-type. 15. The method of claim 14, wherein the two or more bipolar elements are made of NPN. 15. The method of claim 14, wherein the two or more bipolar elements are made of PNP. A method of forming an integrated circuit having a MOS device and a bipolar device on a single semiconductor substrate, Depositing a trench mask pattern on a surface of the semiconductor substrate; Etching the trench pattern on the surface of the semiconductor substrate; Depositing a first dielectric material on the sidewalls of the trench, the first dielectric material having a thermal expansion coefficient close to that of the semiconductor material; Depositing a second dielectric material on the first dielectric material; And Filling the trench structure with polysilicon. 20. The method of claim 19, further comprising forming a trench protection region over the trench structure. 20. The method of claim 19, wherein the semiconductor material is silicon, the first dielectric is silicon nitride, and the second dielectric is silicon oxide. 22. The method of claim 21, further comprising polishing the surface and stopping polishing when silicon nitride is exposed. 22. The method of claim 21, wherein the second dielectric material is deposited on the semiconductor wafer surface and includes an oxide pad, patterning the oxide pad and partially oxidizing the surface of the semiconductor wafer. 20. The method of claim 19, wherein one or more voids remain unfilled in the polysilicon filling the trench to reduce stress relaxation and silicon defect occurrence. 20. The method of claim 19, wherein the trench protection region is formed using a partial oxidation of silicon skin oxide as a patterned hard mask for wet nitride etching. A method of forming an integrated circuit having MOS and bipolar elements in a semiconductor substrate, the method comprising: Patterning depositing a gate layer to form a gate over each MOS device; Forming a spacer oxide layer over the entire substrate; Removing the layer from above the MOS device to protect the bipolar device during MOS device processing; Etching the exposed spacer layer to place sidewall spacers on the gate side of the MOS device; Implanting MOS device regions adjacent sidewall spacers to form self-aligned sources and drains of the MOS devices; Depositing a collector and emitter mask over the bipolar device; Etching the spacer layer to expose the collector and emitter regions; Doping the exposed collector and emitter regions to form the collector and emitter for the bipolar device, using the remaining spacer layer as a mask. 27. The method of claim 26, further comprising: forming an outer base for the bipolar device; Forming a spacer structure for the bipolar transistor to control critical emitter and base dimensions; Forming an emitter polysilicon layer to form a contact for the emitter. 27. The method of claim 26, wherein forming the outer base comprises forming a doped polysilicon layer, a tungsten silicide layer, a polysilicon cap layer, an interpoly oxide layer, and an anti-reflective coating layer. . 27. The method of claim 26, wherein the bipolar transistor is NPN. 27. The method of claim 26, wherein the bipolar transistor is a PNP. In the method of forming an integrated circuit in a semiconductor substrate, Forming a doped polysilicon layer on the substrate; Siliconizing the top surface of the doped polysilicon layer; Depositing a barrier layer over the silicide layer to prevent the dopant from separating in the doped polysilicon layer during subsequent annealing steps. 32. The method of claim 31, further comprising: forming a bipolar transistor; Depositing and patterning a spacer layer to form a collector and emitter mask on the substrate; Etching the patterned spacer layer to expose the collector and emitter regions; Doping the exposed collector and emitter regions to form the collector and emitter for the bipolar device using the spacer layer remaining as a mask; Patterning a doped polysilicon layer to form an external base for the bipolar device. 33. The method of claim 32, further comprising depositing an antireflective coating layer and an interpoly oxide layer. 33. The method of claim 32, wherein the bipolar transistor is NPN. 33. The method of claim 32, wherein the bipolar transistor is a PNP.