SE470226B - GTO thyrists as well as the procedure for producing a GTO thyristor - Google Patents

Description

15 20 25 30 35 A 4 * J 0 O 21.6 2 defective cathode fingers to the common cathode electrode of the thyristor.

It is a first object to achieve an improved cathode structure, which is suitable for reducing the resistance of the extinguishing currents from the gate electrodes in particular. A second aim is to enable the manufacture of thyristors with small linear tolerances, in particular by reducing the number of masks that must be used with a fit corresponding to the small linear tolerances.

These objects can be achieved according to the invention in that the cathode structure is constructed in the manner as stated in the characterizing part of claim 1. The invention is not limited to this structure being a cathode structure, in that the n- and p-doped regions per se equivalent can be p- and n-conducting, with complementary structure in relation to what is described here and in the following. In view of the fact that these two alternatives are equivalent, the thus alternative embodiment will not be further described.

In accordance with a preferred embodiment, the cathodes are small islands grouped in segments, where the islands are regularly distributed in a square network or in another way, for example in a quintessential distribution, with the guide arranged net-shaped between them. A plurality of such similar segments can be regularly distributed over the surface of the silicon wafer in one component. These segments can then be checked individually, and if any of them are faulty, it can be omitted to connect it to the common cathode electrode. The height of the islands can vary and is normally no more than 20 μm high, but can sometimes be fractions of a μm.

Although the islands in the following embodiment have a square shape, it is possible to give them a different shape, e.g. a polygon, circle, ring or star. It is also not necessary that they be the same size. 10 15 20 25 30 35 478 226 3 The islands can also be different, with different segment configurations over the surface of the component. For example, to further reduce the voltage drop in the gate current conduction, it may be appropriate to have a density greater outwardly at the edges when the gate electrode is fed from the center, as well as the distance between segments can be made larger inwardly of the center, for the same purpose.

It is also possible to make islands of ring shape with their own metal contacts in the middle without contact with the common gate electrode, so that the potential in these becomes liquid.

The invention also relates to a method for manufacturing GTO thyristors, which is particularly advantageous for small-patterned parts in that the number of masks is greatly reduced and in a preferred embodiment only a single fine-patterned mask needs to be used. This is achieved by the features stated in claim 9. The basic thing for this is according to the invention that an etching or equivalent after use of a finely patterned mask gives rise to raised small islands, with steep edges. Subsequent process steps will then be able to be controlled by this three-dimensional, geometric, topographical structure, especially in combination with per se known anisotropically acting treatment steps.

The invention will now be explained in more detail on the basis of an exemplary embodiment and on the basis of the drawings.

Fig. 1 shows a GTO thyristor.

Fig. 2 shows a segment of a GTO thyristor.

Fig. 3 shows a scanning electron microscope image of a part of a segment during manufacture.

Fig. 4 also shows, in scanning electron microscopy, a single cathode element in a GTO thyristor. 470 226 10 15 20 25 30 35 4 Fig. 5a shows in cross section and schematically stages during the manufacture of a GTO transistor in accordance with an exemplary embodiment.

Fig. 1 shows a plan view of a GTO thyristor of approximately life size. On the underside not shown there is an anode electrode which largely covers the underside. In the middle there is an opening 1 down to a gate layer, and the nearest circumference of the upper surface is a metallized ring zone which is in contact with the gate electrodes of the thyristor. Around the opening you see a square cell structure with segment 2, which on the upper side are covered by metal electrodes, constituting cathode electrodes. When the thyristor is mounted, these cathode electrodes have contact with a common conductor contact, while another conductor contact abuts against the underside anode and a gate contact abuts from above against the said ring zone around the opening.

Between the segments and submerged there is an isolated network of gate conductors, which further branch within the segments and are intended for switching on and off.

Fig. 2 schematically shows such a segment 2, excluding the said covering metal electrode. Each such segment 2 includes a large number of small island-like cathode elements 3 of silicon which are n-conducting and rest on a base layer which is p-conducting, which in turn rests on an n-conducting layer. The branched gate electrode network is arranged in the corridors between these cathode elements 3. Because the distances between the gate electrodes and the center of the n-β transition between the cathode elements and the base layer below the islands are small, the extinction possibility is greatly improved.

Fig. 3 shows cathode element 3 during the manufacture of the thyristor in the form of upright islands over an exposed surface of base material.

The mutual distance here is about 60 micrometers, and the islands are square with a side of about 40 pm. Fig. 4 shows a single of these islands, from which it can be seen that they have very steep edges. Figures 3 and 4 are occupied by scanning electron microscopes. 10 15 20 25 30 35 470 226 In a manufactured embodiment, the number of segments was 176, with 100 cathode islands per segment, i.e., a total of 17,600 cathode islands.

However, there is nothing to prevent the dimensions of the islands from being further reduced, and they are packed more tightly, which further improves the effect. Namely, the manufacturing method proposed according to the invention enables a reduction of the fitting and other problems, which in miniaturization otherwise quickly lead to a reduced yield.

The number of cathode islands per segment can thus vary within wide limits, eg 1-10,000, and the size of the elementary cells can be from 100 x 100 μm as in the example, down to 20 x 20 μm and smaller. This is because these can be manufactured with just a single mask. The connection of the islands of the elementary cells with a common conductor layer for each segment requires a mask that requires significantly less fitting precision. The different segments can then be tested separately and such segments that do not work well are eliminated by etching away its cathode contact.

A suitable manufacturing method will now be described, which is also suitable to illustrate the previous description of the exemplary embodiment.

Fig. 5a shows a cross section through a part of a silicon wafer, which may have a thickness of about 0.5 mm. A p-doped layer has been arranged on the underside. This layer can also contain a short-circuit pattern consisting of n-doped areas. An aluminum layer is then arranged on the underside thereof. These anode connection layers have not been shown specifically in the figures but are collectively denoted by 50. The board is initially N-doped.

From the top, a P-layer 51 has been doped in and then on top of an N + -doped layer 52.

In this layer, islands as shown in Fig. 3 and Fig. 4 are to be provided. This is done by applying a photoresist layer 53, exposing it with a mask and developing it, after which an anisotropically acting etching is carried out by the silica, down 470 10 15 20 25 30 To a bit below the boundary 54 between the layers 51 and 52. The configuration shown in Fig. 5b is then obtained in cross section.

In the manner shown in Fig. 5c, the silicon surfaces are now oxidized to an oxide layer 55, which is made relatively thin between the islands (anisotropic process).

This oxide layer is partially etched away in an anisotropic process, which means that the spaces between the islands are exposed while the islands with their steep edges remain oxide-covered. By, for example, ion implantation, a thin P + layer 56 is produced on the exposed surfaces. The oxide-coated surfaces are thereby little affected, and a configuration according to Fig. 5d is obtained. A metal layer, for example aluminum layer 57, is then applied over the entire surface, after which a layer of photoresist 58 is applied over it. In view of the fact that this layer 58 is not to be exposed and developed, it is possible to use another product such as a polymer in solution. . The result is a configuration according to Fig. See.

The applied photoresist layer 58 is then partially etched down, leaving a residual layer 59 which between the islands covers the aluminum layer 57. The configuration shown in Fig. 5f is obtained.

A metal etching is then performed, which eliminates all exposed aluminum, even that which adjoins laterally the remaining photoresist layer 59, while the aluminum layer 60 protected by the photoresist layer 59 remains. Then the photoresist is removed, and the configuration shown in Fig. 5g is obtained, with the aluminum layer 60 left, which is delimited towards the steep edges of the islands by a gap 60a.

A polyimide solution is then spun on and dried, and etched approximately as layer 58 in Fig. 5e, until only the spaces between the islands are filled with insulating polyimide 61, preferably to a level corresponding to the islands' upper surface of N-silicon 52. Next, the configuration in Fig. 5h. Now the oxide layer 55 is etched away to the extent that it covers the upper surfaces of the islands, and the whole is covered with a contact layer 62 of metal such as aluminum. The finished elementary cell construction is shown in section in Fig. 5i.

The main current of the thyristor can now flow from the contact layer 62 to the N-layer 52 of the cathode islands, via the base layer 51 down into the N-base layer to the anode connection layer 50. The surrounding gate conductors 60 are part of a conductor network structure surrounding all cathode islands and segments. from the contact layer 62 and has good contact with the P-base layer 51 via the P * layer ss. The transition between the cathode layer 52 and the P-base layer 51 is protected by what remains of the oxide layer S5 at the steep edges of the islands.

The proposed procedure is characterized, as mentioned, in order to avoid the use of more than a single small-scale mask by a self-aligning principle. The mask needed to arrange contact layer 62 has a completely different and larger scale, which is at the section level and not at the individual level of the small cathodes.

The previous description of the various etching, application and oxidation steps in the example has only been made brief, taking into account that each step does not have to differ from conventional semiconductor manufacturing, such as described in Wolf + Tauber, "Silicon Processing for the VLSI Era "(Lattice Press, Sunset Beach, Cal., 1986).

It also follows that the manufacture in relation to the example can be varied in many different ways, so that the manufacture described above is to be understood as only a presently preferred embodiment but is not intended to be limiting for the invention stated in the following claims.

Claims (10)

10 15 20 25 30 35 Patent claim A GTO thyristor composed of a silicon wafer having on its one side a first electrode of metal (50), electrically conductively connected to a first region with a first lead type (N), the opposite side of which is adjacent to a second region (51) having a second lead type, at the opposite side of which adjacent regionally located third regions (52) of the first lead type adjoin, provided with adjoining, second electrodes (62) of metal connected to each other to a common electrode, and laterally adjacent , from the located areas electrically isolated, with the second area arranged and connected to a common gate electrode (60, 56), characterized in that the third areas (52) comprise from the second area (51) with steep side edges emerging islands with a maximum extent in the surface plane of the islands of less than 200 μm, while the control electrodes (60) form a conductor network enclosing each such island on all sides. GTO thyristors according to claim 1, characterized in that the islands are grouped in segments (Fig. 1), within which the islands are regularly distributed with mutual distances of the same order of magnitude as their greatest extent, the segments being regularly distributed at equal distances or at different distances from each other. GTO thyristors according to claim 2, characterized in that the islands in each segment are located along an imaginary rectangular grid. GTO thyristors according to claim 2, characterized in that cathode islands in one and the same segment have mutually different shapes. GTO thyristors according to claim 1 or 2, characterized in that the islands are distributed from a center so that they are located radially outwards more densely. 10 15 20 25 30 35 470 226 9 6. A GTO transistor as claimed in Claim 5, characterized in that the islands are grouped in segments with intermediate control electrodes, which segments have different density distributions of islands. GTO thyristor according to one of the preceding claims, characterized in that the islands are lined at their steep side edges with insulating layers (55) of silica, which also laterally cover the boundary layer (54) between them and the second area (51). ), whereby each island in addition to the said resp. third area also comprises a portion rising from the second area, so that said boundary layer (54) is terminated at said steep side edges of the islands. A GTO transistor according to claim 1, characterized in that the first lead type is n-conducting, and the second lead type is p-conducting. A method of manufacturing a GTO thyristor having a pn junction running across substantially the entire disk between two layers, one of which extends to the bottom surface of the disk and is provided with a first metal electrode connection and the second layer constitutes a base material, the opposite side of which is opposite to the aforesaid junction being provided with a number of spaced apart, in a dimensionally limited third semiconductor layers forming pn junctions to the base layer, which third semiconductor layers are connected to a collecting electrode of metal, and between the third the semiconductor layers a gate electrode pattern of metal in contact with the base material and without direct contact with the third semiconductor layers, which gate electrode pattern is connected to a gate electrode which, by applying voltage, is able to ignite resp. extinguishing a current flowing between the first metal electrode and the collecting electrode, characterized in that the limited elongated third semiconductor layers (52) are manufactured by a semiconductor layer (52) covering the base material (51) with a conductor type in relation to this opposite provided with a photoresist layer (53), which by means of a mask is exposed and developed by means of a mask, leaving only small spots arranged in a regular pattern, that an anisotropic etching operation is carried out throughout the thickness of the semiconductor layer (52) covering the base material (51) and slightly down into the base material so that beneath the patches of photoresist (53) are formed islands with steep edges with a largest dimension in the surface plane of the islands of not more than two hundred micrometers, which cut the boundary layer (54 ) between the aforementioned two layers of different conductor types, which islands rise from an exposed substantially flat surface of base material, after which the three-dimensional topog thus obtained rafin (Fig. 3) is used to, by successive self-aligning operations between the islands and electrically isolated from them, place the said gate electrode pattern (60) in the form of a metal mesh surrounding the islands on all sides in contact with the underlying base material. Method according to claim 9, characterized in that a) a base layer (51) is doped in the silicon wafer as the first layer with a second conductor type opposite to the silicon wafer self-conduction with a first conduit type and above it a second layer (52) with the first the type of conduit, b) a photoresist layer (53) is applied on top of the second layer and exposed with a mask and developed so that small areas of less than 200 μm are distributed, to a greater extent, c) an anisotropic etching operation is performed, as there no photoresist remains is carried out to a depth exceeding the depth of the second layer and at the remaining small surfaces leaves islands with steep edges, d) an oxidation operation is carried out forming an oxide layer (55), which completely covers the exposed part of the first layer , the islands and their steep edges (Fig. 5c), e) the oxide layer (55) is partially etched away, leaving a layer covering the islands and their steep edges m an exposed base layer between the islands, after which a P + layer (56) is diffused into the thus released surface (Fig. 5d); f) an aluminum layer (57) is applied over the exposed part of the first layer, the islands and their steep edges , after which it is covered with a liquid polymer (58) such as photoresist, which is dried (Fig. Se), g) the polymer layer is etched so that the upper parts of the islands are exposed, leaving polymer layers (59) in the space between the islands (Fig. Sf), h ) an etching is performed by the aluminum layer (57), the remaining polymer layer (59) protecting a part thereof (60) in the spaces between the islands but forming empty parts (61) against their edges (Fig. 5g), i) the whole is covered with an insulating layer (61) preferably of polyimide, which is then etched so that it remains only between the islands, which partially protrude therefrom, preferably flush with the upper surfaces of the islands below their oxide layer (55) (Fig. Sh), and j) by an etching operation the surfaces of the islands are exposed from the oxide layer, followed by a metal layers (62) are applied over the islands and the insulating layer (61) (Fig. 5i).