SE464377B

SE464377B - Method of checking the functioning of an error-correction circuit

Info

Publication number: SE464377B
Application number: SE8406313A
Authority: SE
Inventors: L-Aa Aspelin; B J A Nyman
Original assignee: Ellemtel Utvecklings Ab
Priority date: 1984-12-12
Filing date: 1984-12-12
Publication date: 1991-04-15
Also published as: SE8406313D0; SE8406313L

Abstract

Method of checking the functioning of the error- correction circuit in a computer comprising a memory and an error-correction circuit. By extending the functioning of the error-correction circuit to include handling one or more parity bits belonging to a word in the same way as the bits in said word are handled, and by carrying out a parity check on the unread word before the data bus is opened for transmission of the word, a test for the functioning of the error-correction circuit is obtained. <IMAGE>

Description

464 377 1D 15 2D REDOGÖRELSE FÖR UPPFINNINGEN Uppfinningen, vars kännetecken framgår av bifogade patentkrav, utgör ett sätt att i en dator omfattande ett minne och en felkorrigeringskrets kontrollera felkorrigeringskretsens funktion på ett enkelt sätt med ett minimum av komponent- och programuppbad. 464 377 1D 15 2D DESCRIPTION OF THE INVENTION The invention, the features of which appear from the appended claims, constitutes a method to check in a computer comprising a memory and an error correction circuit the function of the error correction circuit in a simple manner with a minimum of component and software deployment.

F IGURBESKRIVNING Uppfinningen beskrivs närmare i anslutning till bifogade ritning, där fig. 1 visar ett blockschema över för uppfinningen väsentliga delar av en dator.F IGUR DESCRIPTION The invention is described in more detail in connection with the accompanying drawing, in which Fig. 1 shows a block diagram of essential parts of a computer for the invention.

F ÖREDRAGEN UTFÖRINGSFORM Fig. 1 visar en dator 1 med en centralenhet 2 och ett symboliskt antytt första paritetskontrollorgan 3 samt en databus 4. Bussen har 17 ledare; 16 för transmission av ett dataord och 1 för transmission av en paritetsbit. Till bussen är anslutet ett minne 5, en felkorrigeringskrets 6 och ett andra paritets- kontrollorgan 7. Till skillnad från den inledningsvis beskrivna felkorrigerings- kretsen behandlar felkorrigeringskretsen 6 även nämnda paritetsbit som vore det en bit i dataordet. De 17 bitarna genererar vid inskrivning i minnet 5 ett 5- bitars första checkord. I minnet lagras följaktligen per ord 16 bitar plus 1 paritetsbit plus 5 checkbitar; totalt 22 bitar. Vid utläsning till exempelvis centralenheten 2 över bussen 4 av ordet med sin paritetsbit genereras i felkorrigeringskretsen 6 ett andra checkord pa samma sätt, som det första checkordet genererades. Efter jämförelse mellan ovan nämnda checkord och eventuell felkorrigering utföres paritetskontroll i parítetskontrollorganet 7 innan databussen 4 öppnas för transmission. Skulle paritetsfel efter upprepade utläsningsförsök föreligga vid denna kontroll förutsätts felkorrigeringskretsens funktion vara felaktig, varvid felsignal avges till en larmkrets.PREFERRED EMBODIMENT Fig. 1 shows a computer 1 with a central unit 2 and a symbolically indicated first parity check body 3 and a data bus 4. The bus has 17 conductors; 16 for transmission of a data word and 1 for transmission of a parity bit. To the bus a memory 5, an error correction circuit 6 and a second parity circuit are connected. control means 7. In contrast to the error correction procedure initially described, the circuit also handles the error correction circuit 6 as said parity bit which would be it a bit in the data word. When written into the memory 5, the 17 bits generate a 5- bit first checkword. Consequently, 16 bits plus 1 are stored in the memory per word parity bit plus 5 check bits; a total of 22 bits. When reading to, for example the central unit 2 over the bus 4 of the word with its parity bit is generated in the error correction circuit 6 a second checkword in the same way as the first the checkword was generated. After comparison between the above mentioned checkword and any error correction, parity check is performed in the parity check body 7 before the data bus 4 is opened for transmission. Would parity error after repeated read attempts to be present at this check are assumed to be in the error correction circuit function be incorrect, whereby an error signal is given to an alarm circuit.

Claims

IO 15 PATENT REQUIREMENTS In a computer comprising a memory and an error correction circuit, it is checked whether a one-bit error exists in the handling of data in the error correction circuit, which error correction circuit is arranged to generate check bits for writing in the memory together with the word in connection with a word to be written in the memory. , which error correction circuit is further arranged to perform an error check in connection with reading a word from the memory by means of the check bits stored together with the word, which way is characterized in that a word to be written in the memory is designed so that it comprises a parity bit , that parity check is performed on the word including the parity bit before the entry in the memory, that with the error correction circuit check bits are generated based on partition checked words including parity bits which check bits are written in the memory together with the words, that when read from the memory an error correction is performed with the error correction circuit. read words with the aid of the check bits, that a parity check is performed on the words incorrectly corrected by the error correction circuit with the aid of the parity bits, and that one-bit errors are considered to exist in the error correction circuit if the latter parity check shows that a read and error-corrected word has the wrong parity.