SE464377B - Method of checking the functioning of an error-correction circuit - Google Patents
Method of checking the functioning of an error-correction circuitInfo
- Publication number
- SE464377B SE464377B SE8406313A SE8406313A SE464377B SE 464377 B SE464377 B SE 464377B SE 8406313 A SE8406313 A SE 8406313A SE 8406313 A SE8406313 A SE 8406313A SE 464377 B SE464377 B SE 464377B
- Authority
- SE
- Sweden
- Prior art keywords
- correction circuit
- error correction
- word
- memory
- error
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Description
464 377 1D 15 2D REDOGÖRELSE FÖR UPPFINNINGEN Uppfinningen, vars kännetecken framgår av bifogade patentkrav, utgör ett sätt att i en dator omfattande ett minne och en felkorrigeringskrets kontrollera felkorrigeringskretsens funktion på ett enkelt sätt med ett minimum av komponent- och programuppbad. 464 377 1D 15 2D DESCRIPTION OF THE INVENTION The invention, the features of which appear from the appended claims, constitutes a method to check in a computer comprising a memory and an error correction circuit the function of the error correction circuit in a simple manner with a minimum of component and software deployment.
F IGURBESKRIVNING Uppfinningen beskrivs närmare i anslutning till bifogade ritning, där fig. 1 visar ett blockschema över för uppfinningen väsentliga delar av en dator.F IGUR DESCRIPTION The invention is described in more detail in connection with the accompanying drawing, in which Fig. 1 shows a block diagram of essential parts of a computer for the invention.
F ÖREDRAGEN UTFÖRINGSFORM Fig. 1 visar en dator 1 med en centralenhet 2 och ett symboliskt antytt första paritetskontrollorgan 3 samt en databus 4. Bussen har 17 ledare; 16 för transmission av ett dataord och 1 för transmission av en paritetsbit. Till bussen är anslutet ett minne 5, en felkorrigeringskrets 6 och ett andra paritets- kontrollorgan 7. Till skillnad från den inledningsvis beskrivna felkorrigerings- kretsen behandlar felkorrigeringskretsen 6 även nämnda paritetsbit som vore det en bit i dataordet. De 17 bitarna genererar vid inskrivning i minnet 5 ett 5- bitars första checkord. I minnet lagras följaktligen per ord 16 bitar plus 1 paritetsbit plus 5 checkbitar; totalt 22 bitar. Vid utläsning till exempelvis centralenheten 2 över bussen 4 av ordet med sin paritetsbit genereras i felkorrigeringskretsen 6 ett andra checkord pa samma sätt, som det första checkordet genererades. Efter jämförelse mellan ovan nämnda checkord och eventuell felkorrigering utföres paritetskontroll i parítetskontrollorganet 7 innan databussen 4 öppnas för transmission. Skulle paritetsfel efter upprepade utläsningsförsök föreligga vid denna kontroll förutsätts felkorrigeringskretsens funktion vara felaktig, varvid felsignal avges till en larmkrets.PREFERRED EMBODIMENT Fig. 1 shows a computer 1 with a central unit 2 and a symbolically indicated first parity check body 3 and a data bus 4. The bus has 17 conductors; 16 for transmission of a data word and 1 for transmission of a parity bit. To the bus a memory 5, an error correction circuit 6 and a second parity circuit are connected. control means 7. In contrast to the error correction procedure initially described, the circuit also handles the error correction circuit 6 as said parity bit which would be it a bit in the data word. When written into the memory 5, the 17 bits generate a 5- bit first checkword. Consequently, 16 bits plus 1 are stored in the memory per word parity bit plus 5 check bits; a total of 22 bits. When reading to, for example the central unit 2 over the bus 4 of the word with its parity bit is generated in the error correction circuit 6 a second checkword in the same way as the first the checkword was generated. After comparison between the above mentioned checkword and any error correction, parity check is performed in the parity check body 7 before the data bus 4 is opened for transmission. Would parity error after repeated read attempts to be present at this check are assumed to be in the error correction circuit function be incorrect, whereby an error signal is given to an alarm circuit.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE8406313A SE464377B (en) | 1984-12-12 | 1984-12-12 | Method of checking the functioning of an error-correction circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE8406313A SE464377B (en) | 1984-12-12 | 1984-12-12 | Method of checking the functioning of an error-correction circuit |
Publications (3)
Publication Number | Publication Date |
---|---|
SE8406313D0 SE8406313D0 (en) | 1984-12-12 |
SE8406313L SE8406313L (en) | 1986-06-13 |
SE464377B true SE464377B (en) | 1991-04-15 |
Family
ID=20358136
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE8406313A SE464377B (en) | 1984-12-12 | 1984-12-12 | Method of checking the functioning of an error-correction circuit |
Country Status (1)
Country | Link |
---|---|
SE (1) | SE464377B (en) |
-
1984
- 1984-12-12 SE SE8406313A patent/SE464377B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
SE8406313D0 (en) | 1984-12-12 |
SE8406313L (en) | 1986-06-13 |
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