SE438936B - VIDEOTIDBASKORRIGERINGSANORDNING - Google Patents

Description

78Û849Û'2 2 or more horizontal lines of the video information. A sequence control unit controls the selection of each memory unit for writing and reading, so that the sampled video information is stored in series order by said plurality of memory units being cycled and by storing one or more lines of the digitized video information in series order in each selected memory device.

The sequence control unit ensures that at the same time as storing the sampled video information in a selected memory unit, the video information stored in another of the memory units is restored so that it can be retrieved from this memory in series order, whereby the memory units for reading out the information stored therein is also provided in a cyclical manner.

The arrangement described in said patent specification for preventing double clocking of a single memory unit, i.e. an attempt to write and read simultaneously in or from the same memory unit in response to an impermissibly large time base error, results in at least one incomplete or destroyed line interval signal. and possibly also in two incomplete or destroyed line interval signals, which are not synchronized in the horizontal direction with respect to each other and which are present in the output signal from the time base correction device. The known time base correction device described above cannot eliminate from its output signal the line intervals of the incoming video signals, in which failures may occur.

Swedish patent application 7605556-5 describes a time base correction device of substantially the same type as described above. In this device, the line intervals of the incoming video signals, in which loss occurs, are omitted in the output signal from the time base correction device and are exchanged for previously stored line intervals of similar video information. In such a time base correction device, the elimination of the video signals containing lapses is obtained simply by extending the recording period of a memory unit in dependence on a detected loss in the incoming video signals to store in this memory unit the next occurring line interval which is not has a dropout after which, during the reading of the stored signals, the line interval preceding the detected or omitted line interval is read out twice to replace the omitted line interval. The arrangement described above is usually satisfactory except in the case where failure occurs in two or more successive line intervals of the incoming video signals, in which case the line interval preceding the failure has been repeated three or more times in the output signal from the time base correction device and such a repetition of a single line interval can be perceived in the image reproduced by the corrected video signals. To avoid double clocking of a memory device due to unauthorized large time base errors in the incoming video signals, the writing or reading period of a memory device is extended from normally one line interval to two line intervals and this idea underlying double clocking can accentuate the above request. written problem associated with the elimination of dropouts.

In the prior art time base correcting devices of the above-mentioned types, the reading of the temporarily stored digitized video signals is performed at a fixed, standard clock rate, and it is not possible to compensate for speed or phase errors that occur within a line range of the incoming video signals.

The object of the present invention is to provide an improved time base correction device which is particularly suitable for processing video signals and which does not have the above-mentioned problems.

The invention relates to a time base correction device in which the reading of video information from the memory is effected at a standard clock rate which is modulated in accordance with speed errors which occur in such video information which is written in the memory.

The features characteristic of the invention appear from patent claim 1.

A preferred embodiment of the invention will be described in more detail below in connection with the accompanying drawings, in which Fig. 1 is a block diagram of a time base correction device in accordance with an embodiment of the present invention, Fig. 2 schematically shows a color video signal to be input to the time base correction device according to Fig. 1 in order to remove time base errors from this signal, Fig. 3 is a time diagram showing the cyclic orders in which signal information is normally entered and read out from the various memory units in the time base correction device according to Fig. 1. Fig. 1, Fig. 4 is a block diagram showing details of a write clock generator and of a speed error memory included in the time base correction device of Fig. 1, Fig. 5 is a block diagram showing details of a system control unit included in the time base correction device. according to Fig. 1, Fig. 6 is a block diagram showing details of a main memory and a main memory controller. Fig. 7 is a bioassembled visual detail included in a time base correction device of Fig. 1; Fig. 8 is a block unit showing details of a read clock generator included in Figs. the time base correction device of Fig. 1, Figs. 9A-W show waveforms which are used to explain. the function of the write clock generator and the speed error memory according to 'g. 4, and Figs. 10A-L and 11A-N show waveforms which are used to illustrate the function of the system control unit according to Fig. 5 during writing, writing, resp. the readout operations. A preferred embodiment of the invention will be described: with reference to Fig. 1, which shows a ten-base correction device 10 according to the present invention. The time base correction device 10 has an input terminal 11 for receiving periodic information signals, e.g. composite color video signals re- \ pr âuceraäe with a so-called VCRs, which composite color video signals have time base errors. If the reproduced composite audio video signals input to the terminal 11 do not already have a standard IESC shape, the signals are fed to a demo emulator 12, which may include an ITSC receiver. The obtained NTSC color video signals pass through a buffer amplifier 13 to a sample and hold circuit 14 and from there through an amplifier 15 to an analog-to-digital converter 16. As can be seen, there is a DC reset loop 17 between the amplifiers 13 and 15 so that ïTSC color video signals are sampled in DC-reset form. 78Û849Û-2 U1 Be l1¿ cut-off reset The NTSC color video signals coming from the amplifier 13 are passed on to a separator lay, which separates u * horizontal synchronizing signals, true to a separator 19 which is controlled by the output separating horizontal synchronizing of color sync pulses from the NTSC color video signals. The separated horizontal sync signals and receive signals are fed to a write clock generator 22, which generates write clock pulses which have a relatively high frequency, for example about 10.74 MHz, which is three times the color or chrominance subcarrier frequency fc for KTSC signal repeats and these clock frequencies. the speed and phase are varied according to changes in the frequency and phase, respectively, of the horizontal sync signals and subcarrier color pulses extracted from the incoming color video signals to accurately track or depend on time base errors in such incoming clock pulses from the generator 20, which have a frequency of about 10.74 MHz, is fed to an A / D converter 16 and to an on-board circuit 14 to control the rate at which the latter transmits signals.

Q saples the dezodulated or detected video signals and the rate at which the converter 16 converts the sampled signals from the original analog form to digital form. In response to a write clock pulse from the generator 20, the A / D converter 16 steps to convert it to a plurality of parallel bit signals, e.g. digital info,: aticn of eight parallel bits.

The parallel bits of the digitized signal information are fed from the converter 16 to a main memory 21 by means of a bit line 16a intended for digital information, which in the drawing is shown in double lines. As shown in Fig. 6, the main memory 21 has memory units MU-1, MU-2, KU-3 and H'-4, each of which consists of a plurality of shift registers. The number of shift registers in each memory unit is equal to the number of parallel bits that form each word in the digitized video signals. In the exemplary embodiment shown, each of the four memory units NU-1, MU-2, HC-3 and KU-4 thus consists of eight shift registers.

Each shift register in the memory units HU-1, MU-2, KU-3 and EU-4 is preferably selected to have a memory capacity which, in view of the frequency of the write clock pulses from the generator 20, is sufficient to store the digitized information corresponding to an el: \ 2 7808490-2 several, and preferably an even number, i.e. 2, 4, 6, 8 --- etc. of the line ranges of the incoming video signals. For HTSC color video signals and having a write clock pulse frequency of about 10, 7á MHz fine: the 652.5 word digital information in each line interval, which in Fig. 2 is marked with H. However, in the time base correction device shown, the horizontal sync signals and the color sync pulses are extracted. which occur during the interval of each line blanking period, preferably from the incoming video signals before their conversion to digital form, whereby e.g. only 640 words of digital information need to be stored in the registers in the memory units HU-1, Queue-3_and HU-4 for each line interval to be stored in these units.

The separated horizontal sync signals are also fed to a nu-2, write start generator 22 which generates write start pulses at pre-set intervals, e.g. at the beginning of each line interval of 1 the case when digital information each of the memory nv avad incoming video signals running against a line interval is to be stored in the write start pulses from the generator 22 and the write start pulses from the generator 20 are fed to a system control unit 23 which controls operations in a main memory controller 24 in order to perform the selective write and read operations in the ur e and HU-4, respectively. Under normal circumstances, the main memory controller 24 states that: the units EU-1, EU-2, MU-3 control the system controller 23 - generate write control signals which occur in a repetitive cyclic sequence and which are each fed to the memory units EU-1, IL -2, EU-3 and MU-4 to determine the sequences in which these memory units are selected or enabled for the writing, in the selected niznes unit, of the digitized information corresponding to the desired number of line ranges of the incoming video signals.

Furthermore, the main memory controller 24 records the write clock pulses from the generator 23 and during the writing period determined by each write control signal, the main memory controller 24 feeds the write clock pulses to the respective memory unit HU-1, KU-2, MU-3 or MH-4, which is then selected or enabled. , so that the digitized information corresponding to the desired number of line intervals of the video signals is written into the shift registers in the selected memory at a clock rate determined by the frequency of the write clock pulses, which varies according to time base errors in the 7808490 2 incoming video signals. After temporary storage in the memory units KU-1, KU-2, HU-3 and HU-4, the digitized video signals are read out from the memory units in a predetermined series order and go to an information or data bus line 25. To determine the clocking rate at which the digitized information is read out from each of the memory units, the time base correction device 10 comprises a standard sync generator 26 which outputs a carrier signal with a fixed standard frequency, for example the standard frequency subcarrier frequency fc = 3.58 EHz for NTSC color video signals. This carrier signal is fed to a read clock generator 27, which in turn emits read clock pulses with a standard frequency, for example 10.74 MHz, at at least the start and end of each read period. The standard sync generator 26 further generates load start pulses at intervals corresponding to the desired number of line intervals of the NTSC video signals stored in each memory unit. The read start pulses from the generator 26 are supplied to the system controller 23 and the read clock pulses go from the generator 27 to the system controller 23 and the main memory controller 24. Under normal circumstances the system controller 23 controls the main memory controller 24 so that it generates read control signals which occur in a sequential sequence. and which are each fed to the memory units EU-1, 2, KU-3 and H3-4 to determine the sequence in which these memory units are selected or enabled for reading out the digitized information stored therein which corresponds to the number of line entries. which were previously stored in the selected memory device. During the reading period determined by each read control signal, the main memory unit 24 outputs the read clock pulses to the selected or refurbished memory unit so that the digitized information corresponding to a lodge form. The analog output signals from the converter 25 are fed to a processing unit 30 which receives standard frequency. 7a-49o-2 signals from the generator 26 and which is operable to add to the output signal from the converter 29 the color sync pulses and the composite synchronizing signals previously separated from the incoming video signals.The composite color video signals obtained from the output 30 are then processed.

To correct for speed errors that may occur in the incoming video signals, the time base corrector 10 of the present invention detects the speed errors at the write clock generator 22 during each write period and the detected speed error is then fed to a speed error memory by means of a speed error holding circuit 33. control from the system controller 23 memorizes the speed error memory 32 the speed error detected during the enrollment period in each of the memory units KU-1, KU-2, MU-3 and HU-4 and during the reading period of each of these memory units outputs the speed error memory a corresponding speed error correction signal to the read clock generator 27 and the read clock pulses therefrom are modulated with said speed error correction signal in a suitable manner to eliminate or compensate for speed errors in a manner described in more detail below.

The read pulse pulses, from having the standard frequency at the beginning and end of each reading period, can thus vary in phase during the reading periods.

The time base correction device 10 according to the invention is further provided with a dropout detector 34, which is connected to the input terminal 11 to detect any dropouts in the incoming video signals and to form a corresponding dropout signal to the system control unit 23. Furthermore, the time base correction device is 10 provided with a failure memory 35 in which information. in the event of a loss in the incoming video signals I race to influence the loading sequences of the memory units and in order to ensure that the video equipment is entered in the memory units which does not show a loss, whereby such deletions are thus eliminated from the video base signals. as shown at the output terminal 31. In the time base correction device 10 shown, as 1 preferably in each of the memory units 7808490-2 2I% 1, EU-2, HU-3 and NM-4 can normally occur simultaneously with the cyclically occurring write control signals for serial readout. of digital information previously stored in the respective memory units KU-3, KU-4, KU-1 and M * -2, respectively.

The write clock generator Fig. 4 shows that the write clock generator 20 in the time base correction device 10 according to the invention essentially comprises an automatic frequency control circuit 40 with a variable frequency oscillator 41 (VCO) whose control voltage is determined by comparing a suitably divided output signal from oscillating signal 41. the horizontal sync signals obtained from the separator. Furthermore, the generator comprises an automatic phase control circuit 42 with a phase shifting device 43 with variable phase which receives an appropriately divided output signal from the oscillator 41 and which is controlled by a phase comparator 44 which compares a suitably divided output signal from the phase shift device 43 with the color sync pulses obtained from the separator 19.

The oscillator 41 of the write clock generator 20 shown in Fig. 4 has a center frequency which is 2N times the chrominance subcarrier frequency of the processed color video signals, for example 6 x 3.58 MHz or 21.48 Lfiz in the case of NT 3 color video signals and N is 3. The output signal at this center frequency from the oscillator 41 is fed to a counter 45, which acts as a frequency divider, which divides by 455 x N. Thus, the counter 45 emits an output signal with the line frequency 15.75 kHz and this output signal is fed to one of the inputs to a phase comparator 46. The horizontal signal (Fig. 9B) separated from the incoming video signal g. EA) with the separator 18 triggers a micro-stable flip-flop 47, which d 'LJ' serves as a time delay link, and the falling edge in out the walking pulse (Fig. 93) from the monostable rocker 47 triggers a monostable rocker 48 to form an output pulse (Fig. 9F) which has a predetermined time ratio to the horizontal sync. the signal and which is fed to another input of the phase comparator 46 for comparison therewith with the divided output signal from the counter 45. The horizontal sync signal from the separator 18 further triggers a monostable flip-flop 49 which emits an output pulse (fig. 93), which at its falling side acts on a latch 50 for locking the count contents of the counter 45 at this moment. A digital comparator 51 receives the locked count content in the counter 45 from the latch 51 and detects the difference between the phase of the incoming horizontal sync pulse and the phase of the divided output signal from the counter 45, which is indicated by the locked the count contents of this counter. The digital comparator 51 emits an output signal at a relatively high level when the phase difference detected by the comparator 51 is within predetermined limits, such as, for example, 3 0.5 microseconds, while the output signal from the comparator 51 has a low level. (O) when the detected phase difference exceeds the predetermined limits, this output signal from the digital comparator 51 is used to actuate a switch or gate 52, which as long as the output signal from the comparator 51 has a relatively high value "1" conducts the output signal from the phase comparator 46 to a holding circuit 53, the output of which is connected to the oscillator 41 and supplies control voltage to this oscillator. The output signal from the digital comparator 51 is then fed through an inverter 54 to actuate a switch or gate. 55 by which the output signal from the monostable flip-flop 48 is selectively fed to the counter 45 to reset it at the occurrence of the the falling side of the output signal or pulse from the monostable flip-flop 48. The switch 55 is in the open state, as shown by solid lines in Fig. 4, as long as the output signal from the digital comparator 51 has a high level "1" for closing the the switch 52 while when the output signal from the comparator 51 is at a low level "0" the switch 55 wears at the same time as the opening of the switch 52.

It is clear that in the automatic frequency control circuit Ä0 described above, the phase comparator 46 will normally compare: U) the phases of the incoming horizontal sync pulses ooh of the divided output signal from the oscillator 41, which is obtained from the V1 counter or frequency counter. 45, and on the basis of this comparison, the phase comparator will output a control signal which is fed through the closed switch 52 to the holding circuit 53. The setting of its output frequency to a value which is maintained until the next horizontal sync signal is obtained from the separator 18.

As long as the phase differences detected by the comparator 51 are within the predetermined limits, the output frequency of the oscillator 41 will vary according to changes in the frequency 7808490-2 ll of the incoming horizontal sync signals, i.e. in accordance with time base errors in the incoming color video signals. If, on the other hand, there is a large or abrupt time base error in the incoming video signals, which results in a corresponding large or transverse deviation in the timing of the horizontal sync signals, for example in the case that the incoming video signals consist of recorded video signals, which are played with a VCR. which the band can jump or slide, the resulting impermissible large phase difference between a received horizontal sync signal and the output signal from the counter or frequency divider 45 will cause the comparator, 51 to output a low level signal "0" whereby the switch 52 and the switch 52 sluts. The opening of the switch 52 opens or breaks the so-called phase-locked loop for the oscillator 41, which loop is constituted by the counter 45, the phase comparator 46 and the holding circuit 53, whereby the holding circuit 53 continues to output the previously determined control voltage to the oscillator 41l to keep its output frequency below its previously determined value. line interval. The closing of the switch 55 at the same time as the opening of the switch 52 causes the output signal or pulse from the monostable rocker 48 to become effective in order to reset the counter 45 at its falling side.

It is clear that the time delay obtained with the monostable flip-flop 47 ensures that such resetting of the counter 45 is effected only after a time interval sufficiently long to allow operation of the switches 52 and 55.

In the above, it is clear that the described automatic frequency control circuit 40 in the write clock generator 20 ensures avoidance of overcorrection of the output signal from the osoilator 41 in response to the described sharp or abrupt changes in the time sequence of the incoming horizontal sync signals or timing.

In the phase control circuit 42 of the write clock generator 20, the output signal is fed from the oscillator 41, which has a center frequency of 21.45 L1, to the phase shift device with variable phase 43 via a frequency divider 56, which divides by 2, to form a center frequency of 10.74 Këz. The output signal from the phase shift device 43 which is the write clock pulse which is supplied to the sample hold circuit 14, the A / D converter 16, the system controller 23 and the main memory controller 24, is also supplied to the phase comparator 44 through a frequency divider 57 which divides by 3 in a center frequency of 3.58 MHz which corresponds to the frequency of the color sync pulses (Fig. 9G) which are supplied to the phase comparator 44 from the separator 19. The phase comparator 44 operates so as to detect speed errors in the incoming video signal and so that it controls the phase shift device 43 with variable phase. As shown in the figure, a flip-flop (F.F.) 58 of each horizontal sync pulse is set from the separator 18 and the flip-flop is reset at the beginning of the first of the corresponding color sync pulses from the separator 19 - as shown in Fig. 9H. The falling edge of the output signal (Fig. 95) of the flip-flop 58 triggers a monostable flip-flop (MK) '59 so that it later emits an output signal (Fig. 9I) whose falling edge is approximately in the middle of the latter half of the separated the color sync pulse (Fig. 9G) at which moment the velocity error indicated by the output signal (Fig. 9K) from the phase comparator 44 has stabilized. The output signal from the comparator 44 is supplied to the speed error holding circuit 33 which also receives the output signal from the monostable flip-flop 59 whereby, when the falling edge of the output signal from the monostable flip-flop 59 occurs, the speed error holding circuit 33 samples and holds ( Fig. 9L) the output signal from the cozparator 44, which then accurately corresponds to the speed error in the previous line interval. The output signal from the monostable flip-flop 59 is also fed to a monostable flip-flop 60, which is triggered by the falling edge of the output signal (Fig. 9I) of the monostable flip-flop 59 to generate an output signal (Fig. 9J) after the speed error has The output signal from the monostable flip-flop 60 closes, when it has a high level "1", a normally open switch 61 through which the output signal from the comparator 44 is supplied to the phase shift device 43 to control the phase of the latter in the circuit. direction which causes the output signal from the phase comparator 44 to be reduced to zero. The period during which the switch 61 is closed is determined by the duration of the output signal from the monostable flip-flop 60, which duration is selected with respect to the time constant of the feedback loop formed by the frequency divider 57, the comparator 44 and the switch 61, so that the phase shift device 43 can hold the phase shift corresponding to an error signal received from the comparator 44 Å at a close of the switch 61 during the interval until the switch 61 is closed again to supply the next error signal l 7808490-2 i 13 from the phase comparator 44 to the phase shift device 43. The System Control Unit Fig. 5 shows that the system control unit 23 in the time base correction device 10 according to the present invention comprises a counter; 62 which receives the write clock pulses from the write clock generator 20 'and the write start pulses (Fig. 10C) from the generator 22. Each write start pulse initiates a counting operation in the counter 62, which thereby counts 640 write clock pulses. The output signal (Fig. 10D) from the counter 62 has a high level "1" to form a write order during the counting operation of the counter 62, i.e. during the counter count of 640 write clock pulses and the output signal from the counter 62 has low level "0" during the intervals between the counting operations. The write command is fed to the main memory controller 24 (Figs. 1 and 6) and to two monostable flip-flops 63 and 64 in the system controller 23. Both flip-flops are triggered by the falling edge of each write command (Figs. E10E and IK). The output signal (Fig. 10E) from the monostable. * Before 63 is fed to a monostable flip-flop 65, which is triggered by the falling edge of each output signal from the nonostable flip-flop 63 to form a corresponding output pulse (Fig. 10F). The output signals or pulses from the monostable flip-flop 65 are counted as -1 a.

J 'J. of a two-bit binary counter 66 which outputs an two-bit output signal which constitutes a write control signal or address (Fig. 10G) for selecting the memory unit in the main memory 21 in which it the digitized information from the A / D converter 16 must be written. The output signal from the monostable flip-flop 65 is also attached to a monostable flip-flop 67, which is triggered by the falling edge of each output signal (Fig. 10F) from the monostable flip-flop 65 to form a pulse (Fig. 10H) to reset a flip-flop 68 after this latter flip-flop has been set by a drop-off signal (Fig. 10I), which flip-flop 68 is received from the drop-out detector 34 (Fig. 1). Therefore, when a dropout is detected and the detector 34 thus generates a dropout signal DO, which is marked with a dashed line in Fig. 101, for setting the flip-flop 68, the output signal rises from the flip-flop 68 to a high level "1" as marked with a dashed line. line in Fig. 10J and remains at this value "1" until the flip-flop 68 is reset by the falling edge of the output signal (Fig. 105) from the monostable flip-flop 67. The output signal from the flip-flop 68 is fed to a fixed contact A on a switch 69 which further carried a grounded fixed contact B 7808490-2 614 and a movable contact connected to the failure memory 35.

The switch 69 is controlled by the output signal (Fig. 10K) from the monstable flip-flop 64 so that the movable contact normally engages the contact B and so that the movable contact is transferred to the contact A only during each output pulse from the monstable flip-flop. 64. Thus, if the output signal from the flip-flop 68 has a high level "1" below the output pulse of the monostable flip-flop 64, this high level "1" will be transmitted as a sensed drop-off signal SDO (Fig. 1OL) through the switch 69 to the drop-off memory 35. The output signal from the microstable flip-flop 64 is so timed that it occurs after the writing of the digitized video information in a selected memory device has been completed and before changing the write address WRA corresponding to the selected memory device.

The write address WBA from the counter 66 is fed to a fixed contact A on a switch 70 (Fig. 5) which is also controlled by the output 'I -s1g-a from the monostable flip-flop 64 and which has another fixed contact B and a movable contact, which is connected to the failure memory 35. The movable contact in the switch 70 is normally in engagement with the fixed contact B and is transferred to engagement with the contact A only when the output signal from the monostable rocker has a high level. Therefore, when a sensed failure signal SDO is fed to the failure memory 35 through the switch 69 in the manner described, the address of the memory unit in which writing takes place during this failure will be simultaneously fed through the switch 70 to the failure memory 35 in the form of a failure memory address DOMA.

The system controller 23 in Fig. 5 also has a counter 71 which receives the read clock pulses RCK from the read clock generator 27 and the read start pulses EST (Fig. 11A) from the generator 26. The counter 71 counts 640 read clock pulses when its counting operation is initiated by each read start pulse RST. The output signal (Fig. 11B) from the counter 71 has a high level "1" to form a read order RCD during each counting operation and the output signal from the counter 61 has a low level "0" during the intervals between the counting operations.

This read order RCD is fed to the main memory controller 24 (Figs. 1 and 6). Each output signal or read order RCD from the counter 71 is fed to a monostable flip-flop 72 which is triggered by the falling edge of the read order RCD to form an output signal or pulse (Fig. 11D). The falling edges of the output signals from the nonostable flip-flop 72 are counted by a two-bit binary counter 73, which outputs a two-bit binary output signal, which constitutes a read control signal or address RA (Fig. 11E). for selecting the memory unit in the main memory 21 from which the stored digitized video information is to be read or retrieved.

The write address WRA from the counter 66 and the read address RA from the counter 73 are fed to a digital comparator 74 and this comes into operation when the level of the output pulse (Fig. 11D) from the monostable flip-flop 72 is high, i.e. immediately after the read operation is completed and then the comparator compares the write address WBA with the read address RA which is then fed to the comparator 74 and on the basis of this comparison the comparator controls or advances the counter 73 so that it forms the read address RA leaving this counter. This will be described in more detail below.

Normally the write address WBA and the read address RA are changed when sequencing the counters 66 and 73 so that the memory units in the main memory 21 are addressed in the repeating cyclic sequence ~ a ~~ no-l, Emß2, HU-3, h -4, lm-l --- etc. and further so that a non-operative memory unit is obtained, i.e. a memory unit in which neither writing nor reading takes place, which non-operative memory unit lies between the memory units in the preceding repeating cyclic sequence which are addressed by the write address NRA and the read address RA for writing resp. reading operations in response to a write order WCD and the more or less overlapping read order RSD. As previously mentioned in connection with Fig. 3, during registration in a selected memory unit LI-1, KU-2, EU-3 or 'LB-á, which is identified by the write address WBA, the read address RA nor-: alt will select and effect reading. from the memory unit HU-3, NU-4, EC-1 or EE-2. However, when correcting for impermissibly large time base errors in the incoming video signals, the normal sequence control of the counters 66 and 73 may cause the read address RA and the suit WBA to identify the same memory unit below overlapping portions of the read and write words R3D resp. NSD. In this case, the apparatus would tend to provide simultaneous writing and reading in the same memory unit and that at different clock rates, which are determined by the write clock pulses WRCK and the read clock pulses RSK, which, however, is impossible.

To avoid this, a digital comparator 74 in the system controller 23 generates a suitable control output signal to the counter 7808490-2 16 73 to shorten or prevent the normal sequence control of the counter 73 on the falling edge of the output signal from the monostable flip-flop 72 below which the write and read addresses WBA and RA are compared whenever this comparison indicates that the normal sequence control of the counter 73 on the falling edge of the output signal from the monostable flip-flop 72 would give rise to a new read address RA 'which is the same as the write address WRA with which comparison is made. If, on the other hand, the comparison of the write and read addresses below the output signal from the monostable flip-flop 72 indicates that the normal sequence control of the counter 73 on the falling edge of this output signal would give rise to a new read address RA 'which is only one address in front of or before the write address WBA with which comparison is made which would mean that sequence control of the counter 66 with the falling edge of the next output signal from the monostable flip-flop 65 would give rise to the write and read addresses becoming equal, then the digital comparator 74 emits a suitable control output signal to the counter 73 so that it is subjected to an additional sequence control before its normal sequence control on the falling edge of the output signal from the monostable flip-flop 72, during which the latter signal the two addresses are compared.

If, for example, during an output signal from the monostable. ' flip-flop 72 the read address RA represents the memory unit MU-1 and this is compared with a write address WBA representing the memory unit KU-3 or KU-4, no control output signal will go from the comparator 74 to the counter 73 because the normal sequence control of the counter 73 on the the falling edge of this output signal from the monostable flip-flop 72 will give rise to a new read address RA ', which represents the memory unit MU-2 and the sequence control of the counter 66 on the falling edge of the next output signal from the monostable flip-flop 65 will give rise to a write address NRA which represents either the memory unit LJ-4 resp. the memory unit HU-1, both of which do not coincide with the memory unit MU-2, which is represented by the read address RA '. From the above, it is clear that no control output signal will be transmitted from the comparator 74 to the counter 73 as long as there is no possibility that the read and write addresses RA and WBA will select the same memory unit in the interval between an output signal from the monostable flip-flop 72 to the next output signal from the same flip-flop.

However, if during an output signal from the monostable flip-flop 72 the read address represents, for example, the memory unit MU-1 and this read address is compared with the write address representing the same memory unit LT-1, the comparator 74 will output a control output signal sequentially controlling the counter 73 before or before its normal sequence control on the falling edge of the output signal from the monostable flip-flop 72, which results in the counter 73 being sequentially controlled or advanced twice to transmit the new read address RA ', which corresponds to the memory unit LE-3. Therefore, if during the reading of the memory unit EU-3 an output signal from the rnostable flip-flop 65 causes the counter 66 to form the read address WBA to the memory unit MU-2, there will be no danger of one and the same memory unit being exposed to double clocking, ie that one and the same memory unit is subjected to simultaneous writing and reading. If, on the other hand, the read address RA and the write address WBA which are compared with each other in the comparator 74 during the output signal from the monostable flip-flop 72 separately represent the memory unit EU-1 resp. EU-2, the control output signal obtained from the comparator 74 will shorten or prevent the normal sequence control of the counter 73 on the falling edge of the output signal from the monostable flip-flop 72 whereby the new read address RA 'will be the same as the read address RA with which the comparison is just made and the memory unit HU-1 will be read again under the next read order RCD. Regardless of whether the counter * is sequentially controlled during the repeated reading of the memory unit EU-1 or not, there is no risk of enrolling in the memory unit KU-1 when reading takes place from it.

The system controller 23 is further shown to include a digital adder 75 which adds -1 to the read address RA from the counter 73 to form an output signal or address (RA-1). Thus, if the read address RA corresponds to the memory unit MU-1, the address (RA-1) from the adder 75 will correspond to the memory unit EU-4. This output signal or address (EA-1) from the adder 75 is compared in the digital comparator 76 with the write address WBA from the counter 66. The comparator 76 outputs a high level output signal "1" if the addresses (RA) are compared. -1) and the WRA corresponds to one and the same memory unit and the output signal from the comparator 76 is at low level "0" when the compared addresses (RA-1) and the WBA correspond to different memory units. This output signal from the comparator 76, i.e. the result of the comparison of the addresses * NRA and (Mfl) is stored in a D-type flip-flop (FF) 77, which is triggered, as shown in Fig. 11F, on the rising edge of each output signal. (Fig. 11D) from the monostable rocker 72, i.e. before the comparator 74 can cause any change in the read address RA from the counter 73 and also for the normal sequence control of the counter 73 on the falling edge of the output signal from the monostable flip-flop 72. The read address RA from the counter 73 is also fed to a second digital adder 78, which adds + 1 to the read address RA so as to output an output signal or address (RA + 1). The output signals or addresses RA + 1) and (RA-1) from the adders 78.resp. 75 are fed to fixed contacts A resp. B of a switch 79 having a movable contact which is controlled by the output signal (Fig. 11F) of the bistable rocker 77 to engage the contact A and pass through the address (RA + 1) as a spare read address SRA only in the case when the output signal from the comparator 76 and thus also that from the bistable flip-flop 77 is at a high level "1". The movable contact engages the fixed contact B in other cases, i.e. when the output signal from the bistable flip-flop 77 is at low level "0", to pass through the address (RA-1) as the backup read address SBA. The output signal from the monostable flip-flop 72 is also fed to a monostable flip-flop 80, which (Fig. 11G) is triggered by the falling edge of the output signal from the monostable flip-flop 72 to form a pulse which, at the falling edge of the latter signal, nal, trigger a bistable flip-flop 81 (FF) and a monostable flip-flop 82 '(ïI). The output signal from the microstable flip-flop 82 is supplied to microstable flip-flops 83 and 84, which according to Figs. both are triggered on the falling edge of the output signal from the monostable flip-flop 82. The falling edge of the output pulse (Fig. 11L) from the monostable flip-flop 83 triggers a bistable flip-flop 85.

As will be described in more detail below, the failure memory 35 outputs dropout information DOI which is fed to the bistable flip-flops 81 and 85 so that these each store the drop-off information obtained from the memory 35 at the moments these flip-flops 81 resp. 85 is triggered on the falling edge of the pulses from the monostable flip-flops 80 and 83.

The output signal (Fig. 11J) from the monostable flip-flop 84 controls a switch 86 which has a fixed contact A which receives the spare read address SBA, i.e. the address (RA-1) or (RA + 1), from the switch 79 and a fixed contact B which receives the address RA from the counter 73. During the output pulse (Fig. 11J) from the monostable flip-flop 84 the movable contact is thrown in the switch 86 to intervene with the fixed contact A so that the spare read address SBA goes to the lapse memory 35, which means that the lapse information (DOI) in this memory will then indicate - whether any lapse occurred in the received video information _ while writing in the memory device identified by the backup load address SRA. In the intervals between the output signal from the monostable flip-flop 84, the switch 86 is in contact with the fixed contact B so that the read address RA from the counter 73 goes to the lapse memory 35, which has the consequence that the lapse information DOI then indicates whether any lapse occurred in the received the video information while writing to the memory device identified by the read address RA.

Assume that the read addresses obtained from the counter 73 during successive read intervals or periods are RA, RA ', RA "- --etc. From the different waveforms in Fig. 11 it is clear that the falling edge of each output pulse from the monostable flip-flop 80 and the sequence control of the counter 73 for changing the read address from RA to RA ', or from RA' to RA ', but before the output pulse from the monostable flip-flop 84 so that the bistable flip-flop 81 is triggered while the switch 86 is in engagement with its con- 3 RA "--- etc. to the default memory 35. Thus, in each case, the bistable flip-flop beer will be triggered before a read interval to store the default ORI associated with the memory unit, which is identified by the read address RA ', RA ", - etc. from which the video information would normally be read in the next reading interval or period It is further clear that the falling edge in the output pulse from the monostable flip-flop 83, which is used for half triggering of the bistable flip-flop 81, occurs after the off, rate for passing the read address - a nn * .mn-a to trigger the bistable flip-flop 85, occurs during the output pulse _ from the monostable flip-flop 84, i.e. while the switch 86 is engaged with its contact A to pass the spare read - eat SRA ', SBA ", --- etc. to the lapse memory 35. In both cases, therefore, the bistable rocker 85 will store the lapse information DOI relating to the memory unit identified by the spare read address SRA ', SRA "--- etc.

Since the triggering of the bistable flip-flop 85 occurs after the falling edge of the output signal from the monostable flip-flop 72, i.e. after the sequence control of the counter 73, it is clear that the spare read address SEA 'is either (RA'-1) or (RA '+ 1) and that the spare read address SRA "is either (RA" -1) or (RA "+ 1) wherein the read addresses RA 'and RA' thus identify memory units from which video information would normally be read in the next reading intervalsà. Since the bistable flip-flop 77 is triggered by the rising edge of the output pulse from the monostable flip-flop 72, i.e. before the sequence control of the counter 73, the determination of whether, for example, SRA 'is (RA'-1) or (RA' + 1) is made on the basis of a comparison of URA and (RA-1), where RA is the address given by the counter 73 within the sequence control of the same.

Each of the bistable flip-flops 81 and 85 emits a high level "1" output signal only in the case where the drop-out information stored in the flip-flop DOI indicates that a drop-out occurred in the incoming video information during entry into the memory unit identified by the read addresses RA ', RA "--- etc. or of the spare read addresses SRA', SRA" --- etc. In all other cases, the bistable flip-flops 81 and 85 emit an output signal at a low level "0".

The output signal from the bistable flip-flop 81 is used in the embodiment shown to control switches 87 and 88, each of which has fixed contacts A and B, which engage with each other movable contact when the output signal from the bistable flip-flop 81 has a high level "1" and a low level, respectively. level "O". The fixed contacts A resp. B in switches 87 resp. 88 are further connected to a switch 79 for receiving from it the backup read address SBA, SRA ', SRA "--- etc., while the fixed contacts B and A of the switches 87 and 88, respectively, are connected to a counter 73 for receiving read addresses RA, RA ', RA "--- etc. from the counter. Therefore, when the output signal from the bistable flip-flop 81 has a low level "0", which indicates that there is no loss in the incoming video signal during the entry into the memory unit identified by the read addresses RA ', RA "--- etc ., the switch 87 forwards the respective read address from the counter 73 to the main memory controller 24 in the form of a definitively determined read address FDRA, while the switch 88 forwards the spare read address S3A ', SRA ", --- etc. from the switch 79 to the main memory. nes control unit 24 in the form of a possible re-registration address PRNRA.

If, on the other hand, the output signal from the bistable flip-flop 81 has a high level "1", which indicates a loss of the incoming video information during the entry into the memory unit, which is identified by the read address RA ', RA "--- etc. from the counter 73, further, the switches 87 and 88, respectively, require the addresses SRA 'ooh RA', SRA "and RA", --- etc. as finally determined reading address FDRA resp. possible re-registration address PREVRA. As shown in Fig. 5, the address PRWRA is passed through the switch 88 to the fixed contact B by the switch 70. Therefore, when the output signal from the monostable flip-flop 64 has a low level "0", the address PRHRA is transmitted from the switch 88 through the switch 70 to the failure memory. 35.

From Fig. 5 it is also clear that the output signals from the bistable flip-flops 81 and 85 (Figs. 11 and 11 fl) are also applied to a control circuit 89, which emits a logic output signal LG at a high level "1" each time the output signals from the bistable flip-flops 81 and 85 are different, for example "0" and "1" or "1" and "0", while the logic output signal LG has a low level "0" each time the output signals from the bistable flip-flops.81 and 85 are the same, for example "O" and "O" respectively. "l" and "l".

The logic_ output signal LG is used to control a switch 90 in the system controller 23 and is also fed to the main memory controller 24 and the speed error memory 32 for purposes which will be described in more detail below in connection with the description of these components. The switch 90 is open as long as the logic output signal LG has a low level "0" and it closes in response to the logic output signal LG going up to a high level "1". Further, a monostable flip-flop (MK) 91 is triggered by each read start pulse ESI to emit an output signal (Fig. 11N) which is passed through the switch 90, when it closes, to a fixed contact B_ on a switch 92, which further has a fixed contact A connected to the output of the monostable rocker-63. The switch 92 is controlled by the output signal from the monostable flip-flop 64 (Fig. 1CK) so that a movable contact in the switch 92 will normally engage the fixed contact B of the switch to switch to the fixed contact A of the switch only during high level output pulse from the monostable flip-flop 64. 7808490-2 22 From the above it is thus clear that during the output pulse from the monostable flip-flop 64, i.e. when switches 70 and 92 switch over to engage their respective contacts A, the output pulse from the monostable flip-flop 63 will be forwarded through the switch 92 to the lapse memory 35 as a lapse write command 'DOWCD for this memory, while the switch 70 forwards the write address WRA to the lapse memory 35 as a lapse memory address DOEA, at which address it sensed the loss SDO, in the event that such a loss occurs at this moment, in a way that will be described in more detail below. During the intervals between successive output signals from the monostable flip-flop 64, i.e. when the switches 70 and 92 are engaged with their contacts B, if the logic output signal LG from the logic circuit 89 has a high level "1" for closing the switch 90, the output pulse from the monostable flip-flop 91, which is triggered by the read start pulse RST, to be forwarded through the switch 92 to the failure memory 35 as an erasure order which causes, on the falling edge of the output pulse 'from the monostable flip-flop 91, erasure of the sensed failure so: possibly previously written at the address in the failure the fall memory 35 which is indicated by the address PRWRA, which is forwarded from the switch 88 through the switch 70 to the drop memory.

The main memory In the main memory shown in Fig. 6, the digitized video information is fed from the A / D converter 16 by means of a bus line 16a to fixed contacts A in switches 93, 94, 95 and 95, respectively. 96 of which each belong to its own memory unit M0-1, EU-2, KU-3 and EU-4. The movable contacts in switches 93, 94, 95 and 96 are connected to fixed contacts B in switches 97, 98, 99 respectively. 100, which in turn have their movable contacts each connected to their respective inputs to the memory units HU-1, HU-2, HU-3 resp. MU-4. The outputs from the memory units MU-1, Mu-2, KU-3 and KU-4 are by means of normally open switches 101, 102, 103 and 104 each connected to the bus line 25 and the video information read out from one of the memory units is fed. back by means of a re-entry loop 105 from the bus line 25 to fixed contacts A in all switches 97-100. Furthermore, individual feedback loops_106, 107, 108 and 109 7808490-2 23 go to fixed contacts B in switches 93, 94, 95 resp. 96 from the outputs of the memory units MU-1, KU-2, MU-3 and HU-4 before connecting these outputs to the respective switches 101, 102, 103 and 104. The movable contacts in the switches 93-96 and in the switches 97-100 is normally engaged with the fixed contacts B and switches over to come into engagement with the fixed contacts A only in cases where these switches receive a control voltage or signal, which will be described in more detail below. The main memory control unit In the main memory control unit 24 in Fig. 6, a decoder 110 receives the read address WRA from the counter 66 in the system control unit 23 and generates a suitable control output signal to one of the selected switches 93-96 associated with the memory unit identified. of the write address WRA received by the decoder 110 in order to switch the movable contact into engagement with the contact A.

The control output signal from the decoder 110, which is thus obtained in response to the read address WRA, is passed on to one of four and gates 111, 112, 113 and 112, respectively. 114 for opening the gate associated with the memory device identified by the read address WBA. An and gate 115 receives write clock pulses WRCK from the write clock generator 20 and the write order WCD from the counter 62 in the system controller 23 whereby the and gate 115 will be opened by the write order WCD to pass write clock pulses WRCK to all the and gates lll-114. The outputs from the and gates lll-l14 are connected to separate or gates 116, 117, 118 and 119, which in turn have their outputs connected to each of the memory units KU-1, HU-2, KU-3 resp. KU-4.

From the above it is clear that when the and gate 115: receives a write order SGD, the write clock pulses WRCK will pass through one of the selected and gates lll-114, more specifically the one having the read address ÜRA which is obtained from the decoder E of the write address WRA , while the decoder 110 simultaneously causes switching in the switch in question among the switches 93-96. Thus, the digitized video information on the bus line 16a will be fed through the switched switch among the switches 93-96 and through the respective switch, which in turn is 7808490-2 24 among the switches 97-100 to the input of the memory unit, which is identified or selected by the write address WBA to be entered; in this selected memory device at the clock rate determined by the write clock pulses WRCK. The main memory controller 24 also includes a decoder 120 which receives the final read address FDRA from the switch 87 in the system controller 23 and which outputs a suitable control output signal for closing that of the switches 101-104 associated with the memory unit identified or indicated by said address FDRA. The outputs of the decoder 120 correspond to min-2 HU-1, Mu-2, HU-3 and KU-4 and are each connected or gates 121, 122, 123 resp. 124 whose outputs the nose units to each resp. 128. The other inputs of the AND gates 125-128 are commonly connected to an output of an AND gate 129, which receives read clock pulses RCK from the read clock generator 27 and the read order RCD from the counter 71 in the system controller 23. The output gates 125-128 corridors are each connected to a separate entrance to the gates 116-119.

Thus, when the read order RCD is received to open the gate 129, the read clock pulses RSK will pass through the gate 129 and through the selected gates 125-128 which have been opened by an output signal transmitted through the or gate in question. the one among the gates 121-124 from the decoder 120 in response to the final read address FDEA. The read clock pulses .CK passed through the selected of and gates 125-128 are transmitted through the respective or gate among gates 116-119 to the respective memory unit among the memory units R -1 --- KU-4 whose respective switches among the switches 101-104 closed in response to the output signal from the decoder 120. Thus, the digitized video information previously stored in the memory device identified by the finally determined read address FDRA will be read out or retrieved from this memory device in response to the read order RCD. and go to the bus line 25 at a clock rate determined by the read clock pulses RCK. It is also clear that during the reading of the stored video information from one of the memory units HU-1 --- EU-4, the read information will be fed back to the input of the common memory unit by means of the respective feedback loop connected to inputs on and gates 125, 126. , 127 '_ 7 8 Û 8 4 9 0 - 2 25 106-109, whereby the one in question of the switches 93-96 then lies in engagement with its contact B and the one in question in the switches 97-100 even then lies in engagement with its contact B.

The main memory controller 24 further includes a decoder 130, which receives the possible rewrite address PRWRA from the switch 88 in the system controller 23 and which operates to generate a control signal at an input to any selected gate of the four gate gates 131, 132. , 133 or 134, which have their outputs connected to their respective gates 121, 122, 123 and 123, respectively. 124. The outputs from the and gates 131-134 are also connected, which is marked with the numbers 0, 1, 2 and 3, to the switches 97, 98, 99 resp. 100 to operate these. Finally, the logic output signal LG from the logic circuit 89 in the system controller 23 is connected to the other inputs on the and gates 131-134. From the above it is clear that when the logic output signal has a high level "1", this high level output signal will pass through a selected and-gate among the and-gates 131-134, which selected and-gate responds against the possible re-write address PRWRA received by the decoder 130 and which has been: closed by the corresponding control signal from this decoder, to be routed to the corresponding switch among the switches 97-100 and to switch dauza moving scars into engagement with the contact A.

The high level logic output LG passing through the opened and-gate among the and-gates 131-134 also goes to the corresponding or-gate among the or-gates 121-124 to open the corresponding and-gate among the and-gates 125- 128. Thus, the read clock pulses RCK pass through the AND gate 129 opened by the read order ECB and through the AND gate opened among the and gates 125-128 by the high level logic output signal LG and through the associated or gate among or grindanaa 116-119 to finally get to the memory unit corresponding to the possible re-registration address PRHRÄ. Therefore, when the logic output signal IG has a high level "1", the digitized video information, which is read out by the memory units EU-1 --- L -4 corresponding to the read address FDRA input at the decoder 120, comes , to be fed back through the re-enrollment loop 105 and re-enrolled in the memory unit identified by the possible re-enrollment address PRNRA incoming at the decoder 130. The loss memory - Fig. 7 shows a loss memory 35 in the time base correction device 10 according to the present invention. The lost memory may comprise four bistable flip-flops (FF) of type D, namely flip-flops 135, 136, 137 and 138, each corresponding to the respective memory units KU-1, MU-2, NU-3 and MU-4. . A decoder 139 receives the default memory address DOMA from the switch 70 in the system controller 23 to form a control signal for opening the and-gate 'among the four and-gates 140, 141, 142 and 143, the key associated with the corresponding bistable rocker among the bistable rockers 135-138. The dropout command DOWCD from the switch 92 in the system controller 23, i.e. the output pulse from the monostable flip-flop 63 fed through the switch 92 when the latter is brought into engagement with its contact A with the pulse from the monostable flip-flop 64 is input to one input of all and gates 140-143.

The bistable flip-flop among the flip-flops 135-138 corresponding to the memory unit, which is identified by the lapse memory address BOOK, is triggered by the drop-off write command DOWCD, which has passed through the opened and-gate among the gates 140-143, so that said triggered bistable flip-flop among the flip-flops 135-138 are adapted to store the sensed drop-off signal SDO, which can then be received from the switch 69 in the system control unit 23 and which is applied to all bistable flip-flops 135-138. When a sensed dropout SDO is stored in one of the flip-flops 135-138, this flip-flop emits an output signal with a high level "1", while the output signal from the flip-flops 135-138 is at a low level "0" in the event that a sensed drop-off _ case SDO is not stored in these. The output signals from the flip-flops 135-138 are arranged to be supplied through normally open switches 144, 145, 146 and 147 to a common line 148 for transmitting failure indications to the bistable flip-flops 81 and 85 in the system controller 23. The failure memory 35 further includes a decoder 149, which receives the read address RA and then the backup read address SRA from the switch 86 in the system controller 23. The decoder 149 enters thereby in operation to form a control signal for closing it among the switches 144-147 associated with that of the flip-flops 135-138 corresponding to the memory unit which is identified by each address which the decoder 149 receives.

The AND gates 140-143 which are selectively opened by control signals from the decoder 139 to pass through the dropout command 78084994 27 DOWCD could be exchanged for normally open switches which are selectively closed by control signals from the decoder 139. Likewise, they would normally open the circuit 144-147 which are selectively closed by control signals from the decoder 149 can be exchanged for and gates which are selectively opened by the control signals from the decoder 149.

Thus, in the failure memory 35 described above, the failure memory address DOMA supplied from the switch 70 in the system controller 23 to the decoder 139 in the presence of output signals from the monostable flip-flop 64 is the write address WRA which the counter 66 is fed to the contact A on the switch 70 with the dropout write command DOWCD which is then fed to the dropout memory 35 is the output pulse which is fed from the monostable flip-flop 63 to the contact A on the switch 92. During each write operation in the main memory 21, the sensed dropout, if any, will thus be stored. in the bistable flip-flop among flip-flops 135-138 which corresponds to the memory unit identified by the write address WBA and in which the digitized video information is being typed.

During a read operation in the main memory 21, and assuming that the logic output signal LG from the logic circuit 89 has a low level "0", the read address RA 'corresponding to the memory unit from which video information is read out or retrieved will first be output from the switch 86. to the decoder 149 so that the latter causes dropout information DOI to be transmitted from the respective flip-flop among the bistable flip-flops 135-135 and goes to the bistable flip-flop 81 in the system controller 23, whereby the output signal from the bistable flip-flop 81 indicates whether or not dropout occurs in the video information which is stored in the memory unit, which is indicated by the read address RA '. During a sizing operation, i.e. during the interval of the output pulse from n-ie w a monostable flip-flop 84, the switch 86 switches to the switch A to output the spare read address SEA 'to the decoder 149, which results in the lapse information DOI then sent to the bistable flip-flop 85 indicating whether loss occurs. or not in the video information stored in the memory device specified by the backup read address SRA '. During a read operation, the switch 70 remains in contact with the contact B so that the address fed through the switch 70 to the encoder 139 in the dropout memory 35 is the possible rewrite address PRWRA obtained from switch 88, ie the address RA'_of the bistable flip-flop 81 indicates the presence of loss in the memory unit corresponding to this address, or the address SRA 'if the bistable flip-flop 81 indicates that the memory unit identified by the address RA' has no loss. If the logic output signal LG from the logic circuit 89 has a high level "1", which indicates a failure in the memory unit identified by the address RA 'or the address SRA', the switch 90 will close and the output pulse from the monostable flip-flop 91 will pass through the current switch 90 and goes to contact B in switch 92. Since switch 92 engages its contact B during the read operation, the pulse from the monostable flip-flop 91 will pass through switch 92 in the form of an erase order, instead of the dropout command DOWCD, to all and gates 140-143. The lapse order proceeds through that of the and gates 140-143 opened by a control signal from the decoder 139 in response to the possible re-write address PRWRA, which is currently applied to the decoder 139, whereby the erasing order triggers or resets it from the bistable flip-flops 135-138 corresponding to the possible re-registration address PRWRA in order to delete it loss information that may have been previously stored in this flip-flop.

The speed error memory In the speed error memory 32 of the time base correction device 10 according to the present invention, the speed error retained in the speed error holding circuit 33 is fed to a fixed contact B shown in Fig. 4 in a switch 105 whose movable contact normally engages this contact B to feeding the velocity sweep to a buffer amplifier 151. the current switch iso switches over and engages the fixed contact A only during re-entry, in a memory unit identified by the address? RWRA, of the video informatics read out of a memory unit, which is identified by the final read address FDEA as described above in connection with Fig. 6. A normally open switch 152 is closed in response to a high level "1" in the logic output signal LG from the logic circuit 89 so that the read start pulse RS? (Fig. 90) is fed through the closed switch 152 to trigger a monostable flip-flop (MM) 153. When this flip-flop is triggered by a read start pulse RST, it emits an output signal at a high J. level "1" whose duration is approx. Microseconds (Fig. 9T) and this high level output signal is supplied to the switch 150 to switch it to engage its contact A. The output signal from the monostable flip-flop 153 is also supplied to a switch 154 with a movable contact which normally engages a fixed contact B which receives the output signal from a digital adder 155 which adds (-1) to the write address WBA from the counter 66 in the system controller 23; i.e. the adder 155 forms the address (WBA-1). The switch 154 further has a fixed contact A which receives the possible re-write address PRWRA from the switch 88 in the system controller 23 and which comes into engagement with the movable contact in the switch 154 in response to a high level output signal from the monostable flip-flop. 153. The movable »switch in switch 154 is connected to a decoder 156 which normally receives the address (NRA-1) from switch B in switch 154. The decoder 156, on the other hand, receives the possible re-write address PRWRA from switch A in switch 154 when the latter is switched over by the output signal from the monostable flip-flop 153 in response to a high-level logic output signal LG.

During a normal write operation in the main memory 21 for writing digitalized video information successively in the memory units identified by the write addresses WBA, WRA '--- etc. switch 154 outputs the addresses (WBA-1), (WRA'-1), --etc. to the decoder 156 (Fig. 9Q). During registration in the memory unit identified, for example, by the address WRA, the decoder 156 outputs a suitable control signal to one of four and gates 157, 158, 159 and 160, more specifically the one corresponding to the address (WBA-1), i.e. to the memory device in which video information was entered during the previous write interval, i.e. during the previous enrollment operation. The falling edge of the output signal (Fig. 9J) of the monostable flip-flop 60 in the write clock generator 20 is used to trigger a monostable flip-flop (MH) 161 which emits a pulse whose duration is 40 microseconds (Fig. 9P), which by an or gate 162 is fed to all and gates 157-160. Thus, when output signal from the monostable flip-flop 161, the control signal from the decoder 156 may pass through the off-gate 157-160 corresponding to the memory unit identified by the address (WRÄ-1) to close an open switch among the normally open switches 163, 164, 165 and 166. At the close of a selected switch among the switches 163-166, the speed error held in the circuit 33 and relating to the speed error which occurred during a previous enrollment interval, ie the range for writing to the memory unit identified by the address (WBA-1), to pass through the switch 150, the buffer amplifier 151 (Fig. 9N) and the only closed switch among the switches 163-166 to the respective analog memory among the the analog memories 167, 168, 169 and 170, which are shown, consist of grounded capacitors, which are connected to each of the buffer amplifiers 171, 172, 173 and 174, which have a high input impedance. á - During the entry of digital video information in the memory units NU-1 --- LM-4 in the main memory 21, the speed error information held in the system control unit 23 (Fig. 9L) will be stored in the memory memory unit 23 (Fig. 9L). the next enrollment interval in a respective analog memory unit among said analog memory units 167-170. One of the speed error information occurs in the form of a voltage being built up (Fig. 93) to a corresponding level across the capacitor selected by closing one of the respective switches 163-166. l.

To effect the reading of the stored speed error information during a normal read operation of the main memory 21, the final read address FDRA is fed from the current generator 87 in the system controller 23 to a decoder 175 in the hash f 'd' fl) -ld 'I The decoder 175 provides control signals or X1 * x signals which selectively close normally open switches 77, 178 and 179, which are connected between the respective output of the buffer amplifiers 171, 172, 173 and 174 and a common line 180 for feeding the read speed error information to the soft look generator 27. It is clear that during the successive reading of the digital video information from the fm H »WJ: him w lm - w C ..._: input units in the main memory 21, which identified by the finally determined read address FDRA, FDRA '--- etc. (Fig. 95), the decoder 175 causes a closure of a respective one of the switches 176-179 during each read interval or period to t to the common line 180 outputs the speed error information from that of the analog memories 167-170 corresponding to the memory unit from which video information is being read.

When the logic output signal LG from the logic circuit 89 has a high level "1" to thereby cause the rewriting in the memory unit identified by the possible rewriting address PRWRA of the digital video information read from the memory unit, which is identified by the finally determined reading address FDRA ', this high-level logic output signal IG will close the switch 152, so that the read start pulse RST can trigger the monostable flip-flop 153, whereby the output signal (Fig. 9T) from this later flip-flop switches the setting modes of the switch axis 150 and 15. that these come into contact with their respective contacts A. When the switch 150 comes into contact with the contact A, the speed error VE which is being read out from that of the analog memories 167-170 corresponding to the memory unit which is identified of the final determined read address FDRA ', to be fed through the switch 150 to the buffer amplifier 151 (fig. 9V). By the switch 154 engaging its contact A, the possible re-write address PRWRA will be fed to a decoder 156, so that the latter emits a control signal or output at that of the and gates 157-160 corresponding to this address.

Since the output signal from the monostable flip-flop 153 is fed through one or gate 162 to all and gates 157-160, this output signal from the monostable flip-flop 153 will pass through that of the and gates 157-160 which receive a control signal from decoder 156 to cause closure of the respective switch among switches 163-166. Therefore, the output signal from the buffer amplifier 151 will pass through that of the switches 163-166 which is closed for storage in that of the analog memories 167-170 corresponding to the main memory unit identified by the possible rewrite address PRWRA.

From the above it is clear that during the re-enrollment in the memory unit identified by the address PRWRA, i.e. the rewrite of the digitized video information being read out from the memory device identified by the address FDRA ', the speed error that is being read out from the analog memory corresponding to the address FDRA' will be rewritten in the analog memory identified by address PRYRA. During subsequent reading of the video information 7808490-2. 32 which has been rewritten in a memory unit in the main memory 21, the speed error memory 32 will thus at the same time offer a speed error corresponding to that which existed during the original E entry of the rewritten video information.

The read clock generator Fig. 8 shows that the read clock generator 28 in the time base correction device 10 according to the present invention may comprise a sawtooth generator 181, which receives the speed error signal VE from the output line 180 of the speed error memory 32. Further, the read order RCD is fed from the counter 71 to the system controller 18 whose output is connected to the sawtooth generator 181 so that the output signal from the sawtooth generator will be zero during those times when the output of the inverter 182 has a high level "1", i.e. in the intervals between successive read- »order RCD. A subcarrier signal SC, which has, for example, the frequency 3.58 MHz in the case of processing NTSC color video signals, is fed from the standard sync generator 26 to a phase modulator 183 for phase modulation therein with the output signal from the sawtooth generator 181. Since the inclination of the sawtooth wave which forms the output signal from generator 181 is proportional to the potential of the velocity error signal VE, which the generator 181 receives from the velocity error memory 32, the output signal from the modulator 183 consists of the subcarrier signal phase modulated with the velocity error signal. The phase-modulated subcarrier signal is fed to a monostable flip-flop 184, which emits a correspondingly phase-modulated square wave signal along with harmonics thereof. The output signal from the monostable flip-flop 184 is fed to a bandpass filter 185, which is tuned to the third harmonic of the subcarrier signal SC, whereby the phase modulated output signal from the bandpass filter 185 has a frequency of, for example, 10.74 MHz.

The output signal from the bandpass filter 185 goes to an amplifier 85 and from there to a square waveformer 187 which emits the desired read clock pulse RSK modulated with the speed error. As mentioned above, this read clock pulse determines the clock rate at which the digitized video information is read from memory 21. fl; Above, the general structure and certain details of the time base correction device 10 of the present invention have been described. It is clear that in this time base correction device, the digital comparator 74 controls the sequence control of the counter 73 that during each reading interval the memory unit enters the main memory 21, which is identified by the read address RA from the counter 73 and from which thus video information is read , to differ from the memory unit identified by the write address WBA and in which thus the video information is entered, whereby so-called double clocking of any of the memory units is avoided. In the time base correction device 10, a lapse indication DOI is obtained each time a lapse occurs in the video information written in one of the memory units in the main memory 21 and this lapse indication is stored in the lapse memory 35 and then also with respect to each of the main memory units. When reading the video information stored in the successive memory units in the main memory Z1, the system controller 23 causes reading of the video information either from the memory unit identified by the read address RA, which is obtained from the counter 73, or in the case the lost memory 35 indicates that a loss occurred in the video information stored in this memory device at the read address RA, from another memory device identified by the backup read address SEA. The reading itself_ takes place with respect to the memory unit, which is identified by the finally determined reading address FDRA. When determining whether the backup read address SBA should be either RA-1 or RA + 1, the digital comparator 76 and the monostable switch 77 in the system controller 23 ensure that this backup read address SRA, in case it becomes the definitively determined read address FDRA, does not gives rise to double clocking of the memory unit in question, ie the read address FRA and the finally determined read address FDRA will not be the same and will not result in overlapping writing and reading with respect to one and the same memory device.

If the time base correction device 10 according to the present invention determines that loss exists in the memory unit identified by the read address RA, whereby the finally determined read address FDRA will be the spare read address SBA, then the video information read from the memory unit identified by the address SBA will be ominous. in the memory unit that has expired, ie the memory device identified 7808490-2 34 by the read address RA which then becomes the possible re-write address? R fl RA. If, on the other hand, the time base correction device determines that loss exists in the memory unit identified by the spare read address SRA, but not in the memory unit identified by the address RA, then the video information read from the memory unit identified by the address RA and it came more to be re-enrolled in the memory unit identified by the SRA address. In connection with the above rewriting or replacement of video information containing lapses with video information not containing lapses, it is clear that the lapse memory 35 also erases the lapse indication in the memory unit in which the rewrite operation has been performed.

In the time base correction device 10 according to the present invention, the speed error memory 32 will remember the speed errors which occur during the writing of video information in each of the memory units in the main memory 21 and each such speed error is used in the read clock generator 28 for phase modulation of the read clock pulses RCK which determines the reading takes place of video information from the respective memory units. When video information from a memory unit with the address FDRA is rewritten in a memory unit with the address PRWRA, the speed error memory 32 will, as mentioned above, store, with respect to this memory unit PRWRA, the speed error associated with the original entry of the video information. in the memory device with the address FDRA. The phase modulation of the read clock panels RSK will thus always correspond to the speed errors that occur during the recording of the video information read from a selected memory unit, regardless of whether this video information was originally written in this memory unit or rewritten in it to replace the originally written one. the video information that contained the omission. "The above-described embodiment of the invention can be modified and varied within the basic spirit of the invention in many ways.

Claims (6)

7808490 ~ 2 35 PATENT CLAIMS A time base correction device for removing time base errors from incoming video signals comprising a main memory having a plurality of addresses for storing respective lines of said incoming video signals, a write clock generator for generating write clock pulses at a variable frequency due to time base errors in the incoming video signals. an input circuit for writing the incoming video signals in said main memory at a rate determined by said write clock pulses, a read clock generator for generating read clock pulses, an output circuit for reading the video signals from said main memory according to said read clock pulses for a control unit for controlling the writing and reading of video signals into and out of said main memory via said input circuit resp. said output circuit, characterized by a speed error detector (44) for detecting speed errors in successive lines of the incoming video signals, a speed error memory (32) having a plurality of addresses which correspond to respective addresses in the main memory (21) and in which is stored detected speed errors (VE) for the lines of the video signals stored in respective addresses of said main memory (21) and a speed error compensator (181-183) for compensating for speed errors of video signals obtained from said output circuit in accordance with respective detected speed errors (VE) stored in said speed error memory (32). Time base correction device according to claim 1, characterized in that said write clock generator (20) comprises a variable frequency oscillator (41) which has an output signal with a center frequency which is a multiple of the color subcarrier frequency of said video signals, a locked loop (45 - 53) which receives said oscillator output signal and horizontal synchronizing signals, which are separated from the video signals received by said input circuit (11 - 16), for varying the frequency of said oscillator output signal according to the variations in frequency of said separated horizontal phase shifters, 7808490-2 36 (43) to which said oscillator output signal is applied to obtain said write clock pulses (WRCK) at the output of said variable phase shifter (43), a phase comparator (44) for comparing the phase of said output signal from the variable phase shifter (43). ) with the phase of the color sync signals at said subcarrier frequency o and which are separated from said video signals received via said input circuit (11 - 16) and for supplying said variable phase shifter (43) with a corresponding control signal, and by a circuit (33) for applying said control signal from said phase comparator (44) on said speed error memory (32) when said speed error information is to be written in the latter. The time base correction device according to claim 1, characterized in that said control unit (23) further controls the writing and reading of the speed errors (VE) into and out of said speed error memory (32). Time base correction device according to claim 3, characterized in that said control unit (23) comprises a write addressing circuit (66) which generates write addresses in a repeated cyclic sequence which are applied to said main memory (21) and said speed error memory (32) for controlling write - the transmission of video signals resp. speed error (VE) at corresponding addresses therein, and a read addressing circuit (73) which generates read addresses which are applied to said main memory (21) and said speed error memory (32) to control the reading of video signals resp. speed errors from the corresponding addresses in these. Time base correction device according to claim 1, characterized in that said speed error compensator (181 - 183) comprises a circuit (183) for phase modulation of said read clock pulses (RCK) in accordance with said detected speed error (VE) stored in the speed error memory (VE). 32). A time base correction device according to claim 3, characterized in that said speed error memory (32) comprises a plurality of capacitors (163 - 167) which correspond to the respective addresses.