CA1076245A - Video time base corrector - Google Patents

Abstract

(S76P108) VIDEO TIME BASE CORRECTOR
ABSTRACT OF THE DISCLOSURE
In a time base corrector which converts incoming video signals to digital form and writes the digitized signals in sequentially enabled units of a main memory at a clocking rate varying generally in accordance with time base errors in the incoming signals, whereupon the signals temporarily stored in the memory are read out or fetched from the successive main memory units at a standard clocking rate and reconverted to analog form for eliminating the time base errors: a drop-out memory stores drop-out information in respect to drop-outs detected in the incoming video signals written in each of the main memory units; drop-outs are eliminated in the output from the time base corrector by rewriting, in each memory unit storing video signals having drop-out as indicated by the drop-out memory, video signals from another memory unit shown by the drop-out memory to be free of drop-out, with such rewriting being effected simultaneously with the read out of the video signals from such other memory unit; and upon the rewriting of video signals in a memory unit, the stored drop out indicating information in respect to that memory unit is erased from the drop-out memory. Further, the clocking rate for reading out the video signals from each of the main memory units is modulated in accordance with velocity error information stored in a velocity error memory during writing of such video signals in the respective main memory unit, and the velocity error memory is operative, upon rewriting in a main memory unit for eliminating drop-out, to replace the velocity error information stored in respect to such main memory unit with the velocity error information associated with the main memory unit from which the rewritten video signals are drawn.

Description

BACKGROUND OF Tt~ INIJE~IO~
Field of the Inventio~
This in~ention relates t~ the processing of periodic information signals, s~ch as, vide~ sig~als, and ~ore particularly is directed to apparatus by which ti~e base errors introduced during recording an~!or reproducmg of such signals may be removed.

Yideo sig~als are frequently recorded on magnetic tape and su~equently reproduced for la~er broadcas~ing or viewing purposes. Duri~g the reproduction of recorded video signals, t~me base or frequency errors are usua~ly introduced by reason of expansion or contraction of the record med_um ~uring or ~ter recording, variation in the speed of the tape relative ~o the magnetic head or heads during recording or reproduction, variaticn between the tape recording speed and the tape reproducing speed, and the like. Such time base errors, when present in the reproduced video signals, cause a frequency shift of the latter which can result in many observable undes~rable effects, particularly when the reproduced :. : : . . : . . : - . . . , :. . - , . .: . .
, ,, . ,. . , . . .. .. . , , . :.. ~ , ~ 4 5 video ~ignals are to be transmitted or broadcast and ~ay be mixed with live broadcast material that do not have such t~me base errors. The observable undesirable effects resulting from relatively small time base errors are a smeared or jittery picture with erroneous intensity variations and, in the case of color video sig~als, improper color display. When the time base erxors are lar~e~ ~he reproduced picture will fail to lock hoxizontally or vertically.
IR ~n existing t~me base corrector for subs~antially remov~ng timQ ba~e errors from ~ideo signals, for example, as disclosed in U.S~ Patent No. 3,860,952, issued January 149 1975, the incoming video signals are converted from analog tG digitaL ~orm and temporarily stored in a memory. Time base errors are removed from the video signals by writing ~e digitlzed signals in th~ memory a~ a clocking rate which varies i~ a manner generally proportional to the time base errors, a~d by fetching or reading o~t these stored signals at a standard clocking rate. After such readi~g out of the dlgitized video signals9 the latter are reconverted to analog fonm and applied to an output terminal. The memory used in the kn~wn time base corrector comprises a plurality of memory , units each capable o storing one or more horizontal lines of video information. A sequence control unit con~rols the selectio~:of each memory- unit for writing and reading so that the sampled ~ideo information is seque~tially stored by .
~yclically enabling the plurality of memory units and seriaLly .

~3 storing one or more lines of digitized video informa~ on ;n each selected memory unit, and further so that, contemporaneousLy with the storage of sampled video informa~ on in a selected memory unlt, the sequence control unit enables the video information stored in a different one of the memory uni~s to be sequentially fetched or read out there~rom~ with the enabling of the memory u~its ~or the reading o~ of the information stored therein being also ei~ected in a cyclical manner. However, the arrangemen~ disclosed in the above idëntified patent for preventing double clocking of a single memory unit, that is, an att~mpt to read and write contemporaneously from the same memory unit in response to an ;~
excessive time base error, xesults in at least one incomplete or det~r~orated line ;nterval signalj and possibly even two incomple~e or deteriorated line interval signals which are :
out o~ horizontal synchroniza~ion with each other and which are prese.nt in the output from the time base corrector~ :
FuIther, the above referred to existing time base corrector is not capable of eliminating f~ m its output those line in~er- .
vals of the incomin~ v~deo signals in which crop-outs may occur.
In view of the above, it has been proposed, for example~ in ~.S. Patent No. 4,063,284, Issued :
December 13, 1975, and havin~ a common assig~ee herewith, to ~, . .
.~ provide a t~me base correc~or gcnerally of the type described 1 ~bove and in wh~ch those line in~ervals of the incomiQg ~ideo 1 " '' ~ 7 6Z 4 S

signals having drop-outs occurring therein are omitted fr-om the output of the time base corrector and replaced by previously s~ored line intervals o~ similar video information. In such time base corrector, the elimination of video signals con~aining drop-outs is achieved merely by extending the writing per;od of a memory unit i~ response ~o a detected drop-out in the ~ncoming ~ideo ~ignals so as ~o store, i~ such me ry unit, the next oscurring line in~erval which is free of drop~out, and~ thereafter, during reading out of ~he stored signals, the line interval preceding ~he detect~ed or omitted line i~terval i~ read twice to replace the omitted line in~exval.
The foregoing arrangemen~ is generally satisfactory except in the case where drop-outs occur in two or more suc:cessive line intervals of the incoming videD signals, in which case the line interval precedi~g the onset of drop-out is repeated three or more times in the output of the time base corrector and such repetition of a single line interval may be perceptible in the picture reproduced ~rom the corrected video signals.
Moreover, ln order to avoid doub~e-clocking o a memory uni~
in respanse to excessive time base errors in the incoming video signals, the wri~ing ox reading period of a memory unit is eæ'cended, for example, from a normal one line interval to two line intervals, and 3uch concept for avoiding double-clocking ~ .
may accentuate the above problem associated with the elimination ~:
of drop-out.

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Z~L5 Further ~ in the existing time base correctors, a~
described above, the read out of the temporarîly stored digitized video signals is effected at a fixed, standard clocking rate, and thus cannot compensate for velocity or phase errors occurring within a line interval of the incoming;
~ideo signals.

y _~ . .. -Accordingly7 it is an object of the invention to provide an impro~Ted t~me base corrector particularly suited for proeessi~g video slgnals, ar~ which the previously descr~bed problem3 are effectively avoided.
~ lore specifically, it is an object of this invention to provide a time bass correctc~r, as aforesaid, having an improved arrangement for omitting rom its output line ~ntervals o video irlformatiorl having drop-outs therein.
~ nother object is to provide a ~ime base corrector as aforesaid~ in which the reading of video information from the memory is effect~d at a standard clocking rate which is modulated in accordance with velocity errors occurring in such ~rideo information as written in the memory..
Still anoth~r object is to provide a time base corrector, as aforesaid~ in which the compensation for velocity errors i~ coordinated wi~ the elimination of drop-out ~n the output o the time base corrector so as not to be disturbed . . . .
by the drop-out elimina~ion~

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~37~2~5 In accorda~ce with an aspect of this invention, in a time base corrector which converts incom~ng video or other periodic information signals to digital form and writes the digitized signals in a main memory at a clocki~g ra~e varying generally in accordance with t~me base errors in the i~co~lng signals, whereupon the signals ~emporarily stored in the main memory are read out or etch~d therefrom at a standard clocking rate and reconverted to analog form for el~minating the time base errors, and in which the main me~ory is composed of a plurality of cyclically enabled memory units: a drop~out memory is pro~ided f~r storing drop~out infoxmation in respect to drop-outs detected in the incoming vldeo information written in each of the main memory units; the drop-outs a~ el~mina~ed by rewriting, in each memory unit $tori~g information having drop-out~ informa~ion free of drop-out from another memory unit s~ultaneously with the reading o such other memory u~it; a~d, upon such rewriting of information in a memory unit, the stored drop-out informa~ on in respect to that memory un~t is erased from the drop-out memory.
Furth~x, in accordance with a eature of this in~ention, a time base corrector as described above is provided with a velocity error memory for storing velocity error i~forma-tions as to the velocity errors in the incoming video siRnals as written i~ the several main memory units, and such velocity error ~n~ormations are sequentially read simultaneously with the reading of the video information from the respective main memory units for modula~ing ~he ~locking rate at which the .
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reading is effected. Furthermore, when video information is rewritten in a mairl memory unit or eliminating drop-out, as described above, the ~elocity error memory exchanges the veloeity error information associated with the rew~itten vîdeo informa-tion for the velocity error information ~ssociated with the video i~formation origirlall written in the respective main mems)ry unit.
The above, and other objects, features and advantages of the invention, will be apparent in ~he following detailed de~cription o an illustrative embodiment which is to be read irl conju~ction with the accompanying drawings, . ' ' ',' - ' " '.
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~Fig. 1 is a schematic block diagram of a time ~ -ba~e corrector according to an embodiment of this ~nven ion;
Fig. 2 i~ a schema~ic diagram illust~ ting a color ~ldeo si~na} that may be applied to the tima base corrector of Fig. 1 ~or removal o~ time base errors rom such signal;
Fig. 3 ~ s a timing chart showing the cyclic orders in which signal informat:~on may normally be written in and read out of the several memory units of the time base corrector of Fi8. 1;

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,~ ' 76~'24L5 Fig. 4 is a schematic block diagram ill~lstra~ing details of a write elock generator and a velocity error memory which a~e included irl the time base corrector o~
Fig. l;
Fig. S i~ a schema~ic block diagram illustrating detaiLs of a system ~o~trol included in the time base oorrector of Fig. l;
F~g. 6 is a schematie block diagram illustrating details of a main memory and a mai~ m2mory ontrol included ~n the ~me ba~e corrector of Fig. l;
~ ig. 7 is a schematic block diagram ill~s~rating detail~ of 8 drop-out memory lncluded in the time base corrector of Fig. l;
: Fig~ 8 i~ a schematic block diagram ~llustra~ing details of a read clock generator included ln the time ba~e correc~or of Fig. 1, Fig~. 9A-W are waveforms to which reference will be madc i~ explaining the operation o~ the write clock gener~tor a~d ~he v~locity error m~mory of Fig. 4; and ; F~gs. lOA-L and llA-N are waveforms to wh~ch reerence will be made in;explai~ing the operation of the system control of Fig. 5 dur~ng writing a~d reading operations, respectively.
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~ESCRI~ION OF A PREFER~ED EMsoDIMENT
Referring to the d~awings in detail, and initiallyto Fig. 1 thereo~, it will be seell that a time base corrector lO according to ghis invention has an input ~erm~nal 11 for receiving periodic information s~gnals, suc~ as composite color video signals reproduced by a so-called VTR and having ~-t~me base errors. If the reproduced composite color video ~ig~als applied to ~erminal 11 are not already in the standard ~TSC form~ such s~gnals are applied to a demodulator 12 which may includ~ an NTSC encoder. The resulting NTSC color vid~o ~ignal~ are applied ~hrough a buffer ampLifier 13 to a sample-hold circuit 14 and fxom the latter through an ampl~ier 15 ~o an analog-to-digital (A/D) conver~er 16. As shown, a D.C.
restoring loop 17 is provided between amp~ifiers 13 and 15 . .
so that the NTSC color video ~igna~ are ~ampled in D.C.
r~stored form. ~ :
The D.C. restored ~TSC color video signals issuing ~ra~ amplifier 13 are fuxther applied to a separator 18 whic~
separates horizontal synchronizing signaLs therefrom, and to a ~eparator 19 which is gated by the separated horizontal synch~oniz~ng ~gnals ~o as ~o ~eparste burst signaLs from the ~TSC color video s~gnals. The separa~ed hor~zontal ~ynchronizl~g slgnals and burst signals are applied to a w~ite clock generator 20 which, as is hereinafter described in:detail, produces write clock puls~s WRCR having a relatively high frequency, for exæmple~ of about 10.74 ~Hz whi~h is . , . . :
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~7~245 three times the color or chrominanee subcarrier frequency fc for NTSC signals, and with their frequency or repetition rate and phase being varied in accordanee w~th changes in the frequency and phase, respectively, of the horizontal synchronizing signaLs and the subcarrier burst signals extracted from ~he incoming color video signals so as to closely follo~ or be d~pend2nt upon ~ime base errors in such incomin~ signals.
~ ~her, it will b~ seen ~hat the wr~te clock pulse~ WRCX issuing from 8enerator 20 and having a fre~uency o approx~ately 10.74 MHz are applied to A/D converter ~6 ~nd to ~ampl~-hold c~rcuit 14 to con~roL the rate at which the latter ~amples the demodulated or detected video signals and the rate at which convexter L6 c~n~er~s the sampled signals ~rom their original a~alog form into digital form. More speclfically, ill response to each write elock pulse from generator 20, ~/D converter 16 is operati~e to sample the d~odulated video signal a~d convert the latter into a plurality o parallel ~it ~lgnals, for example~ dlgital lnformation o eight parallel b~tsO
The paralle~ bits of digltized ~gnaL in~ormation are supplied f~ m conYertex 16 to main memory 21 by way of a digital information bus 16a which, or ea~e of illustra~ion, is represente~ by ~ double line. The main memory ~1 is shown on FLg. 6 to include memory unlts MU-l, MU-2, MU-3 and ~ 4, each of which is comprised of a plurality of shift registers equal in number to the number of parallel b~ts making up each :, :

word of the digit~ zed video signals . Thus, in the example being described, each of the four memory units MU~l, MU-2, MU-3 and ~ 4 is made up of eight shift registers.
Each shift register of the memory units ~ 2, ~U 3 and MU-4 i5 desirably selected to have a storage capacity or memory which, in considerati~ of the frequen~:y of the ~ri~e clock pulses from generator 209 is sufficient to store the digitized inform~tion c:orresponding to one or moreD and preerably aII eYen numbe~, that is, 2,4,6,8 --etc. of the horizontal or Line intervals o the incoming video signals.
ïn the case of ~SC color ~ideo signals and a write clock pulse frequency of about 10.74 ~Hz, there are 682.5 words o~
digi~al lnformation for each horizontal or line irlterval indicalted at H on Fig. 2. However, in the illustrated time b2~e corrector, the horlzonta} synchro~izing ~ignals arld burst signals occurring ~tlri~lg the interval a in each horizontal . ~i blanking period are preferably ~tripped from the incoming video sign~ls prior to the converslon of the latter to di~ital orm ~o that, for example, only 640 words of digi~al information need to be accommodated ~ the registers of memory units P~ 1, MN-2, MU-3 and MU-4 for each of ~he horizo~tal or li~e int~rvals to be stored therain.
. The separated horizon~al synchron~zing ~ignals are : further shown to be applied to a wr~te start generator 22 ~hich produce~ write ~tart pul~es ~ST at predetermined ~ntervaLs~
for example9 at the begi~n~g of evary horizontal or line ;~
; ~12-' '.............. ~ .:

~7~Z45 interval of the incomlng video signals in the case where ~igital information corresponding to one horizontal or li~e f_ -interval ls to be stored in each of the memory ~nits~
The write s~art pulses WST from generator 22, and the write clock pulses WRC~~from generator 20 are applied to a ~ystem oontrol 23 which, as hereinafter described ln detail, eo~trols the operations o~ a main m2mory control 24 for effect=
~ng ~he selec~ive writ~ng and reading vperations of the mem~ry units ~1,MU-27MU-3 a~d ~U-4. Genera~y, under normal circums~ances, sy3tem control 23 causes ~ain memory con~rol 24 to produce write control signals occurring in a repeating cyclic order and which are re~pectively sppLied to the memory units MU-l,MU-2,~U-3 and ~U-4 i~ order to determine ~he sequences in which such memory units are selected or e~abled for the writing9 in the ~elected mem~ry unit, of ~he dLgitized information corresponding to the desixed number of horizontal or line i~tervals of th~ incomlng video sig~als.
Further, the memory control 24 receive~ the write clock pulses WRC~ fr~m generator 20 and, during the wxiting period determined by each w~ite control signal, the m~mory control 24 supplied the wx~te cloek pulses WRC~ to the respective memory uQit :
~U~ U-2,~U-3, or MU-4 which is then selected or enabled for writing, ~o that the digitized ~nformatio~ correspond~ng :~ to ~he desired number of horizontal or line in~ r~als of the vid~o slgnals is written ~n the shi~t regis~ers of the selected memory unLt at the clocking rate determined by the frequency ~.

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~ ~7 ~2 4 5 o~ ~he write clock pu~ses W~CK whic~ varies in accordance with t~me base errors in the incoming video signals.
After momentary storage in memory units ~-1,MU-2~
MU-3 and ~U-4, the d;gitized video signal information is read out therefrom in a predetermined sPquence to an information or da~a bus 25. In order to determine the clocking rate at which the digitized information is read ou~ of each of the :~
memory uni~ he illustrated ~me base corrector 10 includes a sta~dard sync generator 26 which supplie~ a carrier signal at a f~xed or standard frequency, for example, ~he standard chrominance subcarrler frequency fc o 3.58 Maz ~r NTSG color vldeo signals, to a read clo~k generator 27 which, in tur~, pxoduces read clock pulses RC~ hav~ng a standard frequency~
for example, 10.74 MHæ, at lea5t at the beginning and end of each reading p~riod. The standard sync generator 26 is further shown to produce read ~tar~ pulses ~ST~ for exampLe, at intervals correspondin$ to the desired number o~ the horizonta1 or line ~ntervals of ~rsc ~ideo signals stored in each memory unit.
The read start pulses RST fr.om generatar 26 axe applied to system control 23, and the read clock pulses RCK
are applied from generator 27 to sy~tem control 23 and main ~
memory control 24. Under normal circu~stances, system control .
23 causes main memory cnntrol 24 to produce read control signals ~ `
occurring in a repeating cyclie order and which are respecti~ely ~pplied to memory units Mn~ U-2~MU-~ and MU-4 in oxder to determine the sequence i~ which such memory units are selected -14- :

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or enabled for the reading out therefrom of the digitized ~nformation corresponding to ~he number of horizontal or line intervals which had been previously stored in th~ ~elected memory unit. Further, during the reading period detenmined by each read control signaL, the memory control 24 supplies the read clock pulses RCK to the selected or enab1ed me~ory u~it, so tha~ the digitized informa~ion corresponding ~o one or more horizo~tal or line ~ntervals of the video signals i~
read out of the sh~t registers of the selected memary unit at th0 standard c~ocking rate of the read clock pulses RC~.
The ~ead clock pulses RCK are also applied to a bufrer memory 28 which receiv2s the digiti~ed in~orsrlation sequentially read out of main memory 21, and to a digital-to-analog ~/A) co~verter 29 which is operative to convert the ~u~ered digitsl output o memoxy 28 back to the original analog form. The analog output of D~A conver~er 29 is appt ied to a proces~or 30 wh~ch receives the standard frequency carrier signal from generator 26, and which is operat~ve ~o add to the output o~ converter 29 the color burst and composite synehron~zing ~lgnals which were pxeviously stripped from ~he ~ncoming vid~o signals. The resllltirlg compc~si'ce color video signals are then obtained at an output term~llal 31 of processor 30.
In order to correct for velociky errors that may appear ~n the incoming.video ~ignals" the t~e base corrector 10 accord~ng to this ~Inventlon fur~her detects the velocity :

~5 ~ 6~ 4 5 error at the write clock generator 20 during each writing period and then supplies the detected velocity error to a velocity error memory 32 by way of a velocity error hold circuit 33. The veloci~y error memory 32, under the control of system control 239 memorizes the velocity error detected during the writing period of each of ~he memory ~nits MU-l, ~-2,~3 and MU-4, and, during the reading period of each of the memory uni~s, applles a corresponding velocity error :
corxecting signal to read clock ~enerator 27 by which the read clock pulse~ RCK from the latter are suita~ly modulated ~o el~m~na~e or compensa~e or the ve~ocity errors, as hereinafter descri~ed in detail. Thus, the xsad clock pulses R~, while having the stan~ard frequency at the beginning and end of each reading period, may vary in phase during such reading period.
Further, the ~ime base corrector 10 according to this invention is shown to be provided with a drop-ou~ deteetor 34 which is connected with input terminal 11 ~or detecting any drop-out in t~e incoming ~ideo signals and providing a corresponding drop-out signal D0 to the sys~em con~rol circui~
23, and with a drop-out memory 35 in which informa~ion concerning ~he occurrence of drop-out i~ the ineoming video signals is stored for influenci~g the reading sequences o the memory unl~s and or efecting wr~ting in the latte~ of video information free of drop~out so as to eliminate such drop-out from the time bsse corrected ~ideo signals obtained a~ output terminal 31, as hereinafter described in detail.

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As is shown on Fig. 3, ;n the ilLustrated time basecorrector lO, the cyclically occurring wri~e control signals for sequentially writing digital inform~ion corresponding to any desired nu~ber o~ horizontal or line int rvals in each of the memory units MU-l,MN-2,~ 3 and MU~4 may normally occur simulta~eously wi~h the cyclically occuring read control sig~al~ for se~uentially read~ng out the diOital i~formation previously st~red in t~e respective memory units ~3,~-4,~
and ~w29 respectively.
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Referrin~ now to Flg. 4, it will be seen that the write clock generator 20 o~ the time base corrector 10 according to ~his invention may generally comprise an automatic frequency control circuit 4~ having a variable frequency oscillator or VCO 41 wi h its control ~oltage being determined by comparison o~ a suitably di~ided output of VCO 41 wi.th the horizontal ~ynchxo~i~in$ signals received from separator 18, and an automatic phase control circuit 42 having a variable phase shifter 43 which receives a suitab~y divided output of.VCO 41 and which i8 controLled by 8 phase comparator 44 comparing a suitably divided outp~ of phase sh~ter 43 wi~ the burst signals rece~ved from separator 19.
More particular~y, it wiLl be seen that, ~n $he -~
write clock generator 20 illustrated on Fig. 4, the output of VCI:) 41 has a center frequency which is 2N tim~s the chrom-inanee subcarrier frequency of the color video signals being ' ~7 ~2 ~5 processed, for example, 6 x 3.58 ~Mz or 21.48 ~z in the case of NrSC coLor vide~ signals and N being 3, and such output rom VCO 41 is supplied t~ a counter 45 which operates as a freque~cy divider divid~ng by 455xN. Thus, counter 45 provides a divided output at the horizontal or line requency of 15.75 KHz, and sueh divided output is applied to one of the inputs o~ a phasa compara~ r 46. The horisontal synchronizing signal ~Fig. 9B) separated rom the incoming ~ideo signal (Fig. 9A) by separat~r 18 triggers a monostable m~ltivibrator 47 acting as a de~ay, and the fall;ng side of the output pulse (Fig. 9E) fxcm monostable multivibrator 47 triggers a mor~ostable multivibrator , 48 to prov~de an o~tput pulse (Fig. 9F) from the lal:ter which is in predetermined timed relation to the horizontal synchroniz-ing signal and is applied to another input of phase comparator 46 for comparison in ~he latter with the divided output of VCO 41 obtained from cou~ter 45. The hori20ntal synchronizing signal from separator 18 ;Eurther triggers a monostable multi-~ibrator 49 to provide an output pulse (Fig. 9C~ which9 at its alling side, actuates a latch circuit 50 or Latchin~ the contents of counter 45 at such ti~ne. A digital comparator 51 .
r~ce~ves the latched conterlts of coun'cer 45 from latch circui~
50 and detects the dierence between the phase of the incoming horizontal synchroslizing signal or pulse and the p~ase o~ the d~vided outpus ~rom counter 45 as irldicated by the latched co~tent~ Qf such counter. The digital comparator ~I pro~ides an j ~

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output signal of a relatively high level lll" when the phase difference detected by comparator 51 lies within prede~ermined limits, such as, for example ~ 0.5 microseconds, whereas, the output signal from comparator 51 has a low LeveL "O"
when the de~ec~ed phase difference exceeds ~he prede~ermined limits. Such output signal from digital comæarator 51 is employed to actuate a switch or gate 52 which, so long as th~
output signal ~rom comparator 51 has its rela~ively high ~alue conducts the output of pha~e comparator 46 to a hold circuit 53 which, in turn~ has its output connected to VCO 41 as the control voltage for the lat~er. The output signal f~om digital compara~or 51 is further applied through an inverter 54 for actuating a switch or gate 55 through wh~ch the output signal of mono~table muLt~vibrator 48 is selectively applied .. . .
to counter 45 or resetting the lattex at the falLing side of the outp~t sig~al or pulse from monos abLe multivibrator 48. The switch 55 is in its open co~dition, as shown ~n full lines on ~ig. 4, so long as the output signal from digital comparator 51 i~ at its high level "1" for c~osing switch 52, whereas, when the outpu~ signal from compara~or 51 is at its low level'O", switch 55 is closed simultaneously with the -Dpening of switch 52.
I~ will be apparent that, in the autom~ ic frequency control circuit 40 as descr~be~ abo~e, ph~se comparator 46 ., .
will ~ormally compaxe the ph~ses of the inc~ming hori~ ~tal : synchronizlng si~nals and o the divided outpu~ sf VCO 41 '; 1~- .
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as obtained from counter or ~requency divider 45 and, on the basis of such comparison, provide a control signal which is supplied through cl~sed swi~ch 52 to hold circuit 53. The resulting output of hold circuit 53 .is applied, as a control voltage, to VCO 41 so as to adjust the output frequency o~ the latter to a value which is held until the next horizontal synchronizing signal is received from separator 18. Thus, so long as the phase differences detec~ed by comparator Sl are within the predetermined limits~ the output fre~uency of VCO 41 wilL be varied in accordance with changes ~n the fr~quency of the incomi~g horizontal synchroniz~ng signals, tha~ is, in accordance with time base errors in the incoming color video signal~. However, when there is a ~ross or abrupt t~me base error in the incom~ng color video signals ~o produce a corresponding abrupt or gross deviation tn the timing of the hor~.zontal synchroniz~ng signals, for example, when the incoming-signals are recorded video signals;being reproduc~d by a vid~o ~ape recorder in wh~ch a jumping or slippage o~ the tape may occur~ the resulting excessive phaæe difference be~ween a received horizontal synchronizing signal and the output of counter or fre~uency divider 45 causes comparator 51 to provide its output signal with the low level "O" so that sw~tch 52 ~s opened and switch 55 is closed. The opening of switch 52 opens or i~terxupts the so-called phas~ locked loop for VCO 41 constituted by counter 45, phase comparator 46 and hold circuit 53 so that hold circui~ 53 con~i~ues to apply .

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~ ~7 6Z ~ 5 the previously established control voltage to VCO 41 for maintaining the output frequency of the latter at its previously es~ablished value for anothex hoxizontal or line interval.
The closing of switch 55 sim~ltaneously with the opening of switch 52 c~uses the output signal or.pulse from monostable m~ltivibrator 48 to be effective 9 at its falling side, to reset counter 45. It will be noted that the delay provided by the monos~able multivibrator 47 ensures that such resetting of counter 45 wîll be effected only after a time interval suficient to allow actuation of the swi~ches 52 and 55.
From t~e foregoing, it will be apparent that the described automatic ~requency con~rol circuit 40 of the write cLoc~
generator 20 is ef~ective to avoid overcorrection of the o~tput from VCO 41 in response to the described gross or abrupt changes i~ the timing of the incoming horizontal synchronizin~ signa~s.
In the phase control cixcuit 42 o~ write clock gen~rator ~0, the output of VCO 41 having a central frequency of 21.48 MHz is supplied to va~iable phase shiter 43 th~ ugh a d~vide-by-2 requency divlder 56 so as to have a central frequency of 10.74 ~. The output of phase shif~er 43, ~hich ls th~ write clock pulse W~CK for applica~ion to s~mple-hold circuit 14, AtD converter 16, system control 23 a~d main memory control 24, ~s also applied to phase comparator 44 through a divide-by-3 frequency divider 57 so as to have a central freque~cy of 3~58 M%z corresponding to the frequency of the burst signals (Fig. 9G) applied to phase comparat~r 44 rom .

..... .. .. .. . . . . .. . . . . . . .. . . . . .

~62~5 separal:or 19~ The phase comparator 44 funct~ons to de'cect veloci~y error in ~e incoming vldeo signal and to control the variable phase shifter 43. ~5ore particularly, as shown, a ~lip-flop (F.F.) 58 is set by each horizontal synchronizing signal from separator 18 and is rese~- at the onset of the f~rs~ of th~ correspondi~g burst signals from separator 19"
as shown on Fig. 9H. The ~alli~g edge o~ the ou put (Fig. 9H) of F.F. 58 triggers a monosta~le mul~ivibrator (~ 59 so tha~ ~he la~ter produces an output (Fig. 9I) having its falling edge at about the center or later half of the separated burst (Fig. 9G) by which t~ne the velocity error indicated by t~ output (Fig. 9K) of pha~e comparator 44 has become stable~
The OUtpQlt of canparator 44 is applied to velocity error hold circuit 33 which also l~eceives the output of MM 5~ so tha~"
at the falling edge of the output rom ~ 59, hold circuit 33 ~amples a~d holds ~Fig. 9L) the output of comparato~ 44 which then accura~ely corresponds to the velocity error o~ the prev~ous ~: horizontal or ~ine interval. Th~ output of ~ 5g ls also appLied to a monostable~multivibra~or ~IM) 60 which is triggered by the falling etge o the output ~Fig. 9I)of M~ 59 to produce an output (Fig. 9J~ after the ~relo~:ity error has been sampled an~ held in circuit 33. The output o~ ~I 60, when at its high level "1", closes ~ normally operl switch 61 through which the output o comparator 44 is applied o varia~le pha~e shif~er 43 ~or controlli~g ~he latter în the direction to cause the output of phase comparal:or 44 eo be reduced to zero. The .

:

;2~L5 period during which switch 61 is closed i5 detexmlned by the duration of the output of M~l 60, which dùration is selected, in consideration o the ti~e constant of the feedback loop constituted by ~reque~cy divider 57, comparats:~r 44 and switch 61, so that p~ase shifter 43 can hold ~he phase shi~t corres-porldirlg to an error signal received rom cornparator 44 upon a closin~ of switch 61 ~or the inte~al until the switch 6L
i.5 ag ln clos~d for appl~ing ~he next error sig~al rom phase comparator 44 to phas~ shifter 43.
SY5~ CO~ROL
R~ferring now to Pligo 5~ it will be see~ that, in th~ system control 23 of the illustrated time base corrector 10 accord~ng to this invention, a counter 6~ receives the write clock pulses W~ K ~rom the write clock generator 20 and the write start pulses ~7ST (~ig. lOC) from the generator 22r l:ach write start pulse WST ini ia~es counting operation of counter 62 which then counts 640 write clock pulses ~lRCK.
The output (Fig. lOD) of counter 62 is at a high level "1" to constitute a write commatld WCD dur;ng the counting opera~ion o counter 62, that is, during the counting by the latter of 640 write clock pulses WRCK~ and the output o~ counlter 62 is at a r~lat~ely low level "0" during the ~ntervals between counting operations. The write command WCD is applied to the main m~mory control 24 ~Fig~sr 1 and 6) and to two monostable ~aultivibratoxs (MM~ 63 and 64 in ~ystem control 23 which are iboth ~riggered by the falling edge of each wri~e command ~WC~
(Figs. 1013 and K~. The oul:put (~ig. l~)E) o;E ~S 63 is applied ~23--1~371~Z45 to a monos~able m~ltivibrator ~M) 65 which is triggered by the falling edge of each output of ~ 63 to provide a corres-ponding output or pulse (Fig. lOF). The outputs nr pulses from MM 65 are counted by a two-bit binary counter 66 which provides a two-bi~ ~inary ou~put cons~ituting a write control signal or address 'WRA ~Fig. lOG) ~or selecting ~he memory unit of mai~ memory 21 in which the digitized infonmation Erom A/D converter 16 is to be written. The output of MM 65 is further shown to be applied to a monostable multivibrator (MM) 67 which is triggered by the ~alling edge of each output (F~g. lOF) of MN 65 to provide a pulse (Fig. lOH) for resetting a flip-flop (~F) 68 after ~he latter has been set by a drop-out signal D0 (Fig. lOI) received by FF 68 from drop-out detector 34 (Fig. 1). Therefore, when a drop-out is detected to causa de~ector 34 to produce a drop-out signal D0, as indicated in broke~ es on Fig. lOI, for sett~ng FF ~8, the ou~put of FF 68 rises to a re~ati~ly high value l'l", as indicated in broken Lines on Fig. 103, and retains that value "1" until ~F 68 is ~eset by the faIing edge o the output (Fig. lOH) from MM 67. The output of FF 68 is applled to a fixed contact A
of a switch 69 which urther has a grounded fixed contact B
and a mova~le contact connected to drop-out memory 35. The s~itch 69 is controlled by the output ~Fig. lOK) of ~ 64 ~o as to nor~ally engage lt~ contact B and to change-over to its contact A only dur~ng each outpu~ or pulse fro~ ~ 64. Thus~ :
if the output of FF 68 is at its high level "1l' during the .
~24-- . .

~76'~45 .

output or pulse from ~ 64, that high level "1" is transmitted as a sensed drop out signal SDO (Fig. lOL), through switch 69 to drop out memory 35. It will be noted that the;output or puLse from MIS 64 is t~ned o occur after the completion o~
the wri'cing of the digiti~ed video information in a selec~ed orle of the memory units and before chaslging of the write address WRA correspon~ng to that selected memory unit.
l~urthex, the write addre8s ~RA rorn calnter 66 is showrl on Fig. S ~o be applied to a fixed con~act A o a switch 70 which is also ~ntrolled by the output of MM 64 and which has another fixed contact B and a movable contac~ connected to drop c~ut memo~y 35. The movable contact of switch 70 ormally engages its fi~ed contaet B and is changed-ov~r to engage its contact A only during the pulse or high- level ou~put from ~ 64. Therefvre, when a sensed drop-out signal SDO is app~ied to drop-out memory 35 thr~ugh switch 69 9 a~
preYlously described, the address WRA o the memory unit being writte~-i~ durlng such drop-out is simultaneously applied through swi~ch 70 ~o drop-out memory 35 as a drop-out memory address DO~A.
The system control 23 of Fig. 5 is ~urther shown to compri~e a co~nter 71 which receives the read clock puLses RCK rom read clock generator 27, and the read start pulses R$T (Fig. 1~) from generator ~6. The counter 71 counts 64û
read oloc~ pulses RC~ after it~ eolmting operatioll has been initiated by each read start pulse RS'r. The output (Fig. llB) ' ~

.. ..

~ Y6Z45 of counter 71 is at a high level "1" to cosLstitute a read commarld RCD during each counting operatio~" and the output o~
counte~ 71 is at a relatively low or "O" level during the intervals between counting operations. Such read co~mand RCD
is applied to the main m~mory control 24 ~Figs. 1 and 6).
Further, each output or read command R~D from courltex 71 is applied to a monostable multivibrator (M~5~ 72 which is triggered b~ th~ ~alling edge o~ the read command RCD ~o prov~de an out~ut or pulse (Fi~. llD). The falling edges of the outputs or pulses frsm k~M 72 æe cou~ted by a two-bit bina~y couIlter 73 which provides a two-bit baslary output constituting a read control signal or address ~A ~Fig. llE) or selectin~ the memory uni~ of main memory 21 from which the stored digitiæed video in:Eorma~ion is to be read or fetched.
The write address ~RA from co~mter 66 and the read address RA from coun~er 73 are applied to a di8it~1 comparator 74 and the Ia~ter ~s macle operative by the high level output :
or pulse ~ig~ llO) from ~D!I 7~, that is, ~mmediately follow~g the comple~ion of a reading operation, to compare the write address WRA and the xead address RA t:hen being supplied to comparator 74 and, on the basis of such comparison, to further control or step the counter 73 for af~ecting the read address RA issuing there~rom as hereinafter described.
Normally, the write address ~JRA and the read address RA are change~ by ~equenc~ng o cou~ters 66 and 73, respective1y3 so as to address the memo~y units of m~ memory ~L in ~he - :
repeatin~ cyclic order ME3-l,MU-2,~J-3,,MU-r, ~SU~ etc.3 and .. . ... ......... . .
- , . ., ., . .. . . ~

~l0'76~4~

further to provide an inoperative memory unit, that is, a memory unit wh~ h is neither writing nor reading, between the memory units in the foregoing repeating cyclic order which are addressed by write address I~R~ and read address RA for wri~ing and reading operations, respectiv~ y, in response to a write comm~nd WCD and the more or less oYerlapping read command ~CD. Thus~ as previously mentioned with reference to ~ig. 3, during the wr~ting in a selected one of the memory uni s MU-l?~U 2,MU 3 and ~-4 identified by the write address W~A9 the read address RA normally selec~s and causes reading from the memory unit MU-3,MU-4,MU-l,or ~-2, respectively.
~wever7 in correcting for excessive t~me base errors in the i~coming video si~nals, the normal sequencing of counters 66 ~n~ 73 may cause the read address R~ and the write address WRA
to identify the same memory unit during overlapping port;ons of the read and write commands RCD and WCD. In such case, the apparatus would seek to effect sim~ltaneous writing and reading operation~ in the same memory unit at the diferent clocking rates e~tablished by the writ~ clock ~ulses WRCK
and the read clock pulses RCK~ whieh i~ o~viously not possible.
In order to avoid t~ foregoing, digital comparator 74 in the sy~tem control 23 provides a suitable control output to cour~t~r 73 for abo~ng or preventirlg the normal sequencing of counter 73 at the falling edge of the output or pulse from MM 72 during which the write and read addresses WRA and RA

.

.

,~ . - , - . . ~

~ 24S
are being compared~ whenever such comparison indicate~ that the normal sequencing of counter 73 at the falling edge of the output from MM 72 would result in the new read address RA' then being the same as the write address ~ which has been compared.
On the other hand, if the comparison of the write and re~d addresses d~ring an output from MM 72 indicates that the normal sequencing of coun~er 73 at the falling edge of such output ~ould provide a n~w read address RA' th~t is only one addre~s in adYance of the compared writ~ address WR~ so that the se~uenci~g o~ cou~ter 66 by the falling edge of the next o~tput from MM 65 would result in the write and read addresse~
then being the same, then the digital comparator 74 provides a suitable control output or signal to counter 73 for an additional sequencingo~ latter in advance of t~ normal seque~cing thereof at the falling edge of the output from MM
72 during which the addresses are coMpared.
Thus~ ~f for example, during an output from MM 729 the read addre~s RA represen~ing memory unit ~-1 is compare~
wi~h a write address W~A representing the memory unit MU-3 or ~U-~, no control output is applied from comparator 74 to counter 73 as the normal ~equenclng o~ counter 73 at the falling edge `of ~uch outp~t fxom MM 72 will resuls in a new read address RA' represent~ng ~nemory unit ~ 2 and the sequencing oi~ counter 66 at the falling edge of the next output froE~ ~ 65 will result in a write address ~ representing either mesnory unit ~U-4 or MU-l, respectively, which are different from the memory u~lt Ml3-2 represented by ~he read address RA'. From the -28~

s ~oregoing, it will be seen that no control output issues from comparator 74 to counter 73 so long as there is no possibility that the read and write addresses RA and l~RA will select the same memory unit in the interval between an output from MM 72 and the next output from the latter.
However, if, during an output from ~M 72, the read address representing, for example, the memory unit is compared with ~he write address repr~senting the sam2 m~mory unit MU-l, the co~parator 74 provides a control output or signal which ~equences counter 73 in advance of the normal sequencing thereof at the falling edge of the output from NM 72 with the result that counter 73 is sequenced or stepped twice to issue the new read address RA' corresponding to memory unlt MU-3~ Therefore~ ~f, duri~g the reading of memory unit MU-3 an output from MM 65 causes counter 66 to provide the write address WRA for memory unit ~U-2, there is no danger of double clocki~g of a si~gle memory unit, that is~ the ~imulta~eous writing 2nd reading of a single memory unit. On the other hand, if the read address RA and the write address W~A which are compared by comparator 74 during an output from MM 72 respect~vely represent memory un~ts ~-1 a~d MU-2, the resulting control ou~put from compara~or 74 will abo~t or prevent the normal sequencing of counter 73 at t~e ~alling edge of s~ch output from ~ 72 ~o tha~ the new read address RAI will be the same as the compared read address RA and the ~emory u~it MN-l will be read again during the next read command RC~. Thus9 .
whether or not counter 66 ~s sequenced during ~he repeated reading ,~
~, ~9_ .

. : ..
.. . . : . . . .

~76~5 of m.omory unit MU-l, there is no danger of writing in memory unit ~ 1 dur ing the reading there;Erom .
The system control 23 is further shown to comprise a digita~ adder 75 which adds -1 to the read address RA from counter 73 to provide an output or address (RA-l). Thus, if read address RA cor~responds ~o memory unit MU-l, the address rom add~r 75 will correspond to memory unit ~ 4.
Such OUtpllt or address (RA-l) from adder 75 is compared, in a digital ccmpara~or 76, wi~ch the write ad~ress l;~RA rom counter 66. The comparator 76 provides an output of high level ~1~ if the compared addxesses (RA-l) and WRA correspond to the s~me memory unit, and the output o comparator 76 has a low value ~'0~ when the compared addresses tRA-l) and WRA correspond to different memory units. Such output from comparator 76, that is~ the result o ~he comp~rison of addresses WRA and ~RA L)~ is stored in a D-type flip~flop (FF) 77 which is triggered, as indicated on Fig, llF, at the rising ed~e of ç~ach output (Fig. llD) rom ~. 72, that is, before the comparator 74 may e:Efect any change in the read address RA
from counter 73 and also beore the normal sequencing of eounter 73 by the falling ed8e of the output from M~ 72.
The read address RA from counter 73 is further shown to be applied to a second digital adder 78 which adds ~1 to ~he read address RA and, therefore, provides an output or address - (RA~l~. The outputs or addresses ~RA~l~ and (RA-l) from adders 78 a~d 75, respectively are applied to fixed contacts , ~ '' ; -30- :
, :, 1~376~4S
.

A and B, respectively, of a switch 79 which has its movable ~ con~act con~rolled by the output (Fig. llF) of ~F 77 to engage ;~ contact A and pass address (RA~l~ as a spare read address S~A
only when the output o~ comparator 76 and he~ce of FF 77 is at the high level l'l", and otherwise; that is, when the o~tput -~
oiE FF 77 is at the low level "0", to engage the contact B
for passing the address (RA-l) as the spare read address SRA.
The output of ~ 7~ is further shown to be appli~d to a monostable multivibrator ~) 80 which, as shown on Fig,.
llG, is trîggered by the fa11ing edge of the output or pulse from ~M 72 to provide a pulse which, at the falling edge of the latter, triggers a 1ip-flop (FF) 81 and a monostable multivibra~or (~M) 82. The ou~pu'c o ~5 82 is applied to monostable mul~iYibrators (MM) 83 and 84 which, as sho~n on Fig. llL and ~ig. LlJ, respectively~ are both trig~ered by the falling edge of the output or pulse from ~M 82. The fall~ng edge of th~ output or pulse ~Fig. llL) from ~ 83 triggers a ~Lip-flop ~FF) 85. As hereina~ter described in detail, the drop out me~nory 35 provides drop-out informa'cion DOI which ~s applied to FF 81 and FF B5 so that the FF~ ~l and ~5 re~pecti~ely s~core the drop out information provided by memory 35 at the times when FF 81 and FF 85 are respectively triggered by the falling edges of the pulses from ~ 80 and `` ~ 83~

.~, . ..

., ';

~76245 The output or pulse (Fig. llJ~ from ~5M 84 controls a switch 86 havin~ a :Eixed con'cact A which receives the spare read address SRA, that is, the address (RA-l) or (RA+l~, from switch 79, and a fixed contact B which receives the address RA from counter 73. During the output or pulse (Fig. lLJ) from klM 84, the mov ble cont~ct of switch 86 is changed-over to e~gage the fixed con~act ~ thereof so tha~ the spare read address SRA is passed thereby to the drop-ou~ memory 35 so that ~he drop-ou~ in:ormafion DOI from the latter then indicates whether there was any drop-out irl the video information received while writit~g in the memory unit identified by the sp~re read address SRA. In thE~ intervaLs between the output or pulse from ~1 84, switch 86 engage~ its fi~ced eontact B so as ~o pass the read addre~s RA from counter 73 to drop-out memory 35 with the resu~t that the drop Otlt information DOI then iEIdicates whether any drop out appeared in the video information received while writing in the memory unit identifie~ by the read address RA.
As~um1ng; that the read addresses provided by counter 73 for successive readin~s intervals or periods are RA, etc., it will be seen f~om the respectilve waveforms orl Fig. ll that the fall~rlg edge of each output or pulse from 80 for triggering PT 8l occur~ after the respective sequerlcing of counter 73 or changing the read addre s from RA to RA' ,or from RAt to RA", but before the output or pulse fror~ ~IM 84 so that ~F 81 is 'criggered while switch 86 engages i~s B con~act , ` , . .
-32- ~
:. ,.:, . - - . , - ., ., ~ :

~ 7 62 ~

to pass the read address RA', Rh"- ~etc~ to drop~out memory 35. Therefore, in each instance, FF 81 is triggered prior to a read interval to store the drop-out information D0I relative to the memory unit identified by the read address ~A', RA",---etc. and from which the video information would nonmally be read in th~ nex~ read interval or period. Fur~her, it will be seen that the alllng edge-of the output or pulse from MM 83 for triggering FF 85 occurs during the output or pulse from ~ $4, ~hat ist while switch 86 engages i~s A contact ~o pass the spare read address SRA1 9 SRAf~ etc. to drop~out memory 35. Therefore, in each instance, FT 85 stores the drop-ou~ inormation DOI rela~ive to the memory unit identified by the spare read addres~ SRA', SRA"---etc.
S~nce the triggering of FF 85 occurs ~fter the falling edge of the output from MM 72, that is, after the sequencing of cou~ter 73, lt will be apparent that the spare read address SRA' is either (RA'-l) or (RA'~l) a~d the spare read addres~
SRA" is either (RA"-l) or (RA~ , w~th the read addresses RA' and RA" ident~ying~ as mentioned above, memory units from which video information would normally be read in the following read intervals or periods. ~owevera since FF 77 is triggered ..
by the rising edge of the outp~t or pulse from MM 72, that is, :~
before the se~uencing of counter 73, the determination o whether9 or ex~mple, SRA' is ~RA'~l~ or (RA'~l) is made on the basis of a comparison of ~RA and (RA-l) in which RA:is ~he address indicated by counter 73 prior to i~s being sequenced.
.~

.

.. . . . .

~ 6 Z ~ S

Each o the F~s 81 and 85 provides a high level output ~1l' only when the drop-out information ~OI stored therein indicates that drop-out appeared in the incoming vldeo ~formation during writing in the memory unit identiied by the read address RA' 9 RA~ ete. j vr by the spare read address SRA'~SRA~ etc., respect;vely, and at all other times the FFs 81 and 85 each provide a low level output "O".
The output of FF 81 is shown to be employed for controlling switches 87 and 88 eAch having fixed contacts A and B which a~e engaged by a respective movable contact -~ when the outpu~ of ~F 81 is at its high level "1" and at its low level ~0"~ respectively. Further, the fi~ed contacts A
and B of switches 87 and 8~, respectively, are connected to swltch 79 ~or receiving the spare read address SRA,SRA', SRA",-~-etc. from ~he latter~ while the fixed contac~ B
and A of switches 87 and 88, respectiveLy, are connected to co~nter 73 for receiving the read address RA, RA'JRA",---etc.
rom the latter. Therefore, when the output o~ FF 81 is at its low level "0~', indicating no drop-out in the incoming video ;
i~format~.on dur~ng writing in the memoxy unit identified by read address RA',RA"9- -etc~D th~ switch 87 del~vers the respective read address from counter 73 to the main memory control 24 as a ~inally determined xead address FD~A~ while the switch 88 delivers the spare reat address S~A',SRA",---etc.
from ~witch 79 to main memory control 24 as a possible rewrite ~ddress PRW~A. OQ the other hand, when the output of FF 81 is at its high lev~l l'l" indicating a d~op-out in the lncom~ng :

~ 7 62 4 S

video information during writing in the memo~y unit iden~ified by read address RA' ,E~ etc. ~rom counter 73, the switches 87 and 88 respectively deliver the addresses SRA' and RA', SRA" alld RA", --etc~ as the FDRA and the l?B~A, respectivelyO
Further, as shown on Fig~ 5, the address P~WRA obtained ~hrough ~witch 88 ~s also applied to fixed contact B of switch 70. Therefore, when the outpu~ of ~M 64 is at its low level "Q", the address P~RA from switch 88 is ~ran~mikted through switch 70 to ~he drop out memory 35.
It will also be seen on Fig. S that the outputs from F~ 81 and FF 85 (Fi~s. llI and llM) are applied to a log~c circuit 89 which provides a logic ou~put I.G at a high lev~l l" whenever the ou~puts of FFs 81 and 85 are different, for exarnple, 10'l and "l~' or ~ and J~0~9 respectively; whereas, the logic ou~put L~ is at a low level"Otl whenever the outputs ~- of FFs 81 and 85 are the ~ame, ~or example, "O" and "O" or ~llt~ and 1'15', respeoti~ely.
: The logic output LG is employed for con~rolling a swi~ch 90 in system control 23, and is aLso applied to main .;
memory control 24 and velocit~ error memory 3~ for purpos~s that will appear from the follow~ng detailed descripti~ns o the l~tter components. The switch 90 is open so long as the logic output LG is at the ~ow le~el lloll and is closed in respQnse to the logic outpue LG attaining the high le~el l'lJ'.
~urther, a monostable multivibrator (~) 91 is triggered by each ~ead start pulse RST to provide an output or pulse (Fig. llN) '.

~-~ w35~, ~
' . ,~ . . , . -, , ~!~76Z4~

which is pas~ed through switch 90, upon closing of th~ latter3 to a fixed contact B of a switch 92 which further has a ixed contact A connected to the output of MM 63. The switch 92 is con~rolled by the outpu~ of MM 64 (Fig;. lOK) so tha a movable contact of switch 92 normally enga~es its fixed cc)ntact B and is changed- over to its fixed contact A only during the h:Lgh level output or pulse rom ~M 64.
It ~ill be seell from the above that, during the output or pulse rom~I 64, ~hat is, when switches 70 and 92 are c:hanged over to er~gage their respective contact~ A, the output or pulse from ~M 63 is passed through swit:ch 92 to the drop-out memory 35 as a drop-out write command DOWCD
for ~he latter, while switch 70 passes the write addre~
~RA to the drop-out memory 35 as the drop-out memory address DO~ at which the sensed drop-out SDO~ i~ it then exists, is to be written or 5ts~red ~ drop-out memory 35~ as hereinafter described :in detail. On the other harld, in the in~ervals between success:~ve oultptlts or pulses from MM 64, that is, when switches 70 a~d 92 eng,age thei.r B contacts, if the logic output LG iErom logic circuit 89 is at the high level ~ ' for .:
closing ~witch 90, ~he pulse from MM 91 triggered by read start pulse P~ST is passed through switch 92 to drop--out memory 35 as an erase command so as ~o cause erasing, at the falling ~:
edge of the pulse rom ~I 9t, of the sensed drop-out that may have bee~ prevlou~Ly written at the address in drop-out memory 35 ind~cated by tha address PRWRA passed fr~m switch 88 ~hrough :
s~i tch 70 to the dxop--out mem~ry .
' -~6- ~ ~

~37~2~S
~ .

Reerring now to Fig. 6, it will be seen that, in the main memory 21, the digitized video informa~ on from A/D
converter 16 is applied, by way of bus 16a, to fixed contacts A of switches 93, 94,95 an~ 96 whieh are respectively associated with memory units MU-l,MU-2,MU-3 and MU-4. The movable con~acts of switches 93,94,95 and 96 are co~nected to fixed con~acts B of switches 98,98,99 and 100, respectively, which, in turn, have their movable contacts connected to the i~puts of memory uni~s MU-1,MU-2,~ 3 and ~-4~ respectively~
The outputs o memory units MU~1,MU-2,MU-3 and ~U-4 are connected by way of normally open switches 101, 102~ 103 and 104, respectiYely~ tQ the bus 25, and the video informatio~ read out of any one o the memory units ~s fed back~ by way of a rewriting loop 105, from bus 25 to fixed contacts A of all of ~; ~he switches 97~100 0 Eurther, individual feedback loops 106 107 ,108 and lV~ e~ctend to fixed c:ontacts B of switches 93, 95,95 and 96, re~pect~vely, from the outpuks o~ memory units MIJ-1,~-2,MU-3 and MU-4 in advance o~ the respectlve switches 101,102,103 and 104. The movable contacts o~ switches 93-96 and of 9witches 97-100 normally engage the respective fixed contacts B and are changed-over to en~age the respective fixed contact~: A only whe~ such.switches receive respective contro~
voltages or signals, ~ hereinafter described in detaiL.
.
~37-.' ' ' .
. ' '~ ' .

~ IN M~M~RY CONTROL
In the main memory control 24, as shown on Fig. 6, a decoder 110 xeceives the write address WRA from counter 66 in system control 23 and pro~vides a suitable con~rol output o~
signal to a selected one of the switches 93-96 which is assoc-iated with the mem~ry unit identified by the wri~e address ~RA received~y the decoder 110, so as to change over the :~
selected one of switches 93-96 to its contaot A. Further~
the control output or signal issuing ~rom decoder 110 in response to the write address WRA is applied to a respective one o~ four AND ga~es lll,L12,113 and 114 for opening the one of such gates assoeiated with the memory unit ide~tified by t~ write address WRA. An AND ga~e 115 receives the write clock pul~es WRCX from the write clock generator 20 and the write command . . .;
WCD from t~3 counter 62 o~ system control ~3 so that AND gate 115 is ope~ed by the write command ~CD for passir~ ~he write look pulses W~C~C to all of the AND gates 111-114. The outputs of A~D gates lLl, 112~113 and 114 are respectively connected to 0~ gates 116,,117,118 an~ 119 which, in ~uxn, have their outputs suitably connected to memory units ~U-l,MU-2,~-3 and MU-4, respectively.
It will be apparent from the above; that, upon ~ the reception of a wrlte command W~D by AND gate 115 the wr~te -~, clock pu~se~ WRCK are applied through a ~elected one o AND
: gates lll-L14, as ~etermi~ed by the write address W~A received by decoder 1109 and th~Dugh a respectlYe one of OR gates 116 119 ..

'.

- . . . ~ . - . . , ~ . . ..
.. . ..

~ ~ 6~ 45 to the one of memory units MU~ MU~4 identi~ied by the write address WRA, while ~he decoder lL0 simultaneously causes the change-over of the respective one of the switches 93-96.
Thus, the digitized video inormation received by bus 16a is applied through the changed-over one o the switches 93-96 and through the respeetive one o the switches 97 100 ~o the input o~ the memory un~t identified or selected by the write addres~ W~A so as to be written in such selected memory unit at he clocking rate determined by the write clock pu~ses WRC~C.
The ma~n mem~ry control 24 is furth2r shown to co~prise a decoder 120 which receives the finally determined read address FDRA from switch 87 of system control 23, and which provides a ~uitable contro} ou~put or signal for closing a selec~ed one o the switche3 101-104 which i3 associated with the memory unLt identified by the ~nally determined read address ~DRA.
The output~ o~ decoder 120 corresponding to memory units MU-1,MU-2,MU~3 and MU-4 are also respectively connected to inputs of O~ gates 121!,122 > 123.and 124 havin~ the~r outputs connected to inputs o~ AND gates 125,126,127 and 128, respectively.
Other inputs o AND gates 125-128 are all connected to the output of an AND gate 129 which receives read clock pu}ses ~:
RCg from read clock generator ~7 and read command RCD from counter 71 of system.control. 23O Further, the outputs of AND ~ates 125~128 a~e connected to ~nputs of OR gates 116-119, respectiveLy~

39- .

. ' : ,, ~

~ 7 6~ ~5 .
It w;ll be apparent from the above that, when the read command RCD is received ~o open AND gate 129, the read clock pulses RC~ are passed through gate 129 and through a selected one of the AND gates 125~128 which has been opened by an output signal transmitted by wa~ of the respective one o~ the OR gates 121-124 from decoder 120 in response ~o the received f~nally determine~ read address FDRA. The read c1Ock pulse~ RCK passed through a selected one of the A~D gates 125-128 are transmitted through the respective o~e of the O~
gates lL6=119 to ~he one of the memory units ~U~ MU-4 which ha~ had its respect~ve switch 101-104 closed in response to the ou~p~t signaL from decoder l~O. Thus, the digitized video inormation previously stored in the selected one of the memory units identified by the finally determined read ad~re~s FD~A is read out or fetched from such memory unit to the bus 25 in response to the read command RCD and at a clocking rate determined by the read cloc~ pulses RCK. It wi~l also be seen that, during the read out of stored video information from any one of the memory units ~ 4, the read-out information is ~ed back to the ~npu~ of the same , memory unit by way of the respective one of the feedback loops . 106-109, the respective one of the switches 93-96 then engaged wi~h its eontact B and the respectiv~ one o~ the switches 97-100 also then engaged.w~th its contact B.
. , :
~ . .
~, -40-. . .
. .

~7 62~

The main memory control 24 is further shown to comprise a decoder 130 w~ich receives the possible rewrite address PRWRA from swltch 88 of system control 23, and which is operative to provide a control signal or output to an input of a selected one of four AND gates 131,132,133 and 134 which ~ave their outputs connected to OR gates 121~122,123 and 124 respectively. The outputs of A~D gates 131,132,133 and 134 are also connec~ed, a~ indica~ed at O,l,Z and 3, to ~he switches 97~98,99 and 100, respec~ively, for operating ~he latter.
Finally, the logic output LG from logic circuit 89 of sy~tem control 23 is connected to other ~nputs of AND gates 13~-134.
It will be apparent rom the abo~e that, when the logic output LG is at its high level 1'1", such high logic output is passed through a selected one o~ AND gates 131-134 which corresponds to the possible rewrite address PRWRA
received by decoder 130 and which has been closed by the corresponding control signal or output from such decoder, to a respective one of the swltches 97~100 for changing-over that respect~ve ~witch to its contact A. Simultaneously, the high .1 .
level ~ o logic output LG passing through the opened one of AND gates 131-134 is ~urther passed through the respective one of OR gates 121; ~24 or open;ng the respective one of AND gates 1250128. Accordingly, the read clock pulses RCK
are passed through AND gate 129 opened by read command P~CD
a~d through the selected one of AND gates 125~128 opened by ~che high leveI logic output W for passage ~hrough the respective Qne of OR gates 116 119 to the memory unit correspond~g to the possible rewrite address PR~ A. Therefore, wh~n the logic 41- :
,, ,, ~ . ~ .... . ..
.. : , , , , .. . . , ... ~

~76~45 :~

output LG is at its high level "1", the digitized video in-formation being read out of a sel~cted one of memory units MU-l---MU-4 corresponding to the finally determined read address FDRA applied to decoder 120 is fed back through rewrite loop 105 and rewritten in the memory unit which is identified by the possible rewrite address PRWRA applied to decoder 130.

DROP - OUT MEMORY
Referring now to Fig. 7~ it will be seen that the drop-out memory 35 of the time base corrector 10 according to this invention may com~pJise four D-type flip-flops (FF) 135, 136, 137 and 138 which respectively correspond to memory units MU-l, MU-2, MU-3 and MU-4. A decoder 139 receives the drop-out memory address DOMA from switch 70 o:E system control 23 --so as to provide a control signal or output for opening a selected one of faur AND gates 140,141, 142 and 143 whlch are associated with FFs 135, 136, 137 and 138, respectively. The drop-out write command DOWCD from switch 92 of system control :. .
23, tha-t is, the output or pulse from MM 63 passed through ~.-.
switch 92 when the latter is made to engage its contact A by . .
the pulse from MM 64 is applied to inputs of all of the AND
gates 140-143. Therefore, a select~d one of the FFs 135-138 corresponding to the memory unit identified by drop-out memory address DOMA is triggered by the drop-out write command DOWCD passed through the respective opened one o:E AND gates 140-143, so that the triggered one of the FFs 135-138 is adapted to store the sensed drop-out si~nal SDO which may ~''. ' .

: .

' 624~

~hen be received fro~ switch 69 of system control 23 and which is applied to all o~ the FFs 135-138. Each of FFs 135-138 provides an output of high level ll" when a sensed drop~out SDO is stored therein, while ~he o~tput from each of the FFs 135-~ 8 is at a-relati~ely lo~ level "O"--in the a~se~ce of a sensed drop~out SDO stored therein. The outputs o~ FFs 135 138 are adapted ~o be applied through normally open swi~ches 144, 1459146 and 1473 xespecti~ely, $o a common line 148 for tra~s-mitting drop-out indications DOI to FFs 81 and 85 of sys~em control 23. Drop-out memory 35 further includes a decoder 149 which receives the read address RA and t~en the spare read address SRA from switch 86 of system control 23 and is operative tu provide a control signal or output for closing a selected one of the switches 144-147 a~sociated with the one of FFs 135~
138 corresponding to the memory unit identi~ied by each address receiYed by decoder 149.
It will be noted that, in drop-out memory 35, AND
, ~
ga~es 140~J43 which are selectively opened by contxol signals or outputs from decoder 139 to pass the drop-o~t write command DOWCD, could be replaced by normally open switches which are selectively closed by the control s~gnals or outputs from decoder 139. Fuxther, the normally open switches 1440147 which are selectively closed by control signals or outputs from decoder 149 could be replaced by AND gates which are selectively opened by the control signals fnom decoder 149.

-, ~ . , ,~ , ~76Z~

It will be apparent that, in the drop~out memory 35as described above, the drop-out memory address DOMA applied from switch 70 of system control 23 to decoder 139 dur;ng the pulse or output from M~ 64 is the write address W~ applied from counter 66 to contact A af switch 70, while the drop-out write command ~O~CD then applied to drop-out memory 35 ~s the pul~e or output ~rom ~ 63 applied to con~act A o~ swi~ch 92.
Thus, during each writing operation o~ main memory 21, the se~sed drop~out SD09- if it exists9 is stored in the one o~
~Fs 135 138 which corresponds to the memory unit ident~fied by the write address WRA and in which the digitiæed video in~ormation is being written.
In a reading operation of main memory 21, and assuming that the log~c output LG from logic circuit 89 is at its low lev~l "O", the read addxess RA' correspond~ g to .. . .
th~ memor.y unit from which the video informa~bn is to be read or fetched is fir~t applied from switch 86 to dec~der 149 so ~at the latter ca~ses the drop-out information DOI to be transmitted from the respective one of FFs 135-L38 to FF 81 of ~ystem control 23, whereby the output o~ FF 81 indicate~

whether or not dxop-out occurs ~n the video information s~ored 1~ the memory unit identified by read address RAI. Further, in the xeading operation !, during the interval o~ the pulse . -from MM:849 sw~tch 86 is; changed-over to its contact A to supply the spare read acidres~ SRA' to decoder 149 with the result that ~he drop-out ~nformation DOI then transmi~ted to .

-44- :

~ 2 ~S

FF 85 indicates whether or not drop-out occurred in the video information stored in the memory unit identiied by the spare re~d address SRA'~ In the reading opera~ion, switch 70 remains engaged with its contaot B so ~hat the address supplied through switch 70 tc decoder 139 of drop-out memory 35 is the possible rewrite address PRI~RA obtained from switch 88, ~hat is, the address RA' if FF 81 indicates drop-ou~ in the memory unit correspo~ding to that address a or the address SRA' if FF 8L
indic~ es that the memory unit iden~ified by the address RU
is free o~ drop-out~ ~urthermore, if the logic output LG
of logic circuit 89 is at the high level t'1" indicating drop~
out in the memory unit id2ntified by the address RA' or the address S~A'~ æwitch 90 is closed and the output or pulse from MM 91 is passed therethrough to contact B of switch 92.
Since switch 92 engages its contact B during the reading opera-tion, the pulse from M~ 91 is passed through switch 92 as an erase command~ i~ place of the drop-out write command DOWCD~
to a11 o the FFs 140~143. The more command is urther passed through the one o~ FFs 140-143 which is opened by a control signal from decoder 139 in response to the possible rewrite address P~WRA then applied ~o decoder 139 3 whereby the described erase command triggers or resets the one of the FFs 135-138 cnrrespondin~ to the possible rewrite address PRWRA for erasing aly drop-out information previously s~ored in such flip-flop.

.

.' ' ~ ~45- .

.. . . . .

76Z9~5 ~EL~ITY ERR0~ MEMORY
Referring again to Fig. 4, it will be seen that, in the velocity error memory 32 of time b~se corrector 10 according to this lnvention, the velocity error held in circuit 33 is applied to a ixed contact B of a sw~tch 150 having a movable contact that normally engages such contact B for supplying th~
veloci~y error to a buffer amplifier 151. The switch 150 i~ .-.
changed-over ~o engage a fixed contact A thereof only during ~he rewriting, i~ a memory unit id~ntified by the possible rewrit~ address ~?R~A,- of the video information being read out of memory unit identified by the finally determined read address FDRA, as described above wlth reference to Fig. 6.
~ore particularly ~ a normal~ open switch 152 is closed ir~
response to the high level "1" OIC logic output LÇ: rom logic circuit 89 so that the read start pulse RST (Fig~ 903 is applied through closed switch 152 for triggering a monostable mu}ti~ibrator (MM~ 153. When triggered by read start pu~ e ~ST, ~M 153 provides an output of relatively high level "1"
for about 20 microseconds (Fig. 9T), and such high level output of ~M 153 i5 applied to switch 150 or changing-over the lat~er to its contact A. The outpu~ of ~M 153 is further applied to a ~witch 154 having a movable contac~ which normally engages a fixed contact B receiving the output of a digi~al adder 155 wh~ch adds(-~)to the wr~te address W~A from counter 66 of .
system control 23~ that is, adder 155 provides the address 62 ~ ~

~WRA-l). The switch 154 further has a fixed contact A receiving the possible rewrite address PRW~A from switch 88 of system control 23 and which is engaged by the movable contact of switch 154 in response to the relatively high level output of MM 153. The ms)vable contact of switch 154 is connected to a decc~der 156 which normally reeeives the address (~ l) from contact D of switch 154, whereas decoder 156 receives the possible rewrite address PRWRA from contact A of switeh lS4 when the lat~er is changed~over by the output of ~ 153 in re~ponse to ~he high level of logic output LG.
~ uring a normal writing operation of main memory 21 for writi~g digitized video information successively in the m~mory units thereoi~ identified by write addresses WRA"WRA'- -etc., switch L54 delivers the addresses (WRA~ (WRA'~ -etc.
to decoder 156 (Fig. 9Q). Thus, for example, during the writing irl the memory unit identified by address WRA, decoder 156 applies a su~table control signal or output to th~ one o~
four AND gates 157,158,159 and 160 which corresponds to the address ~WRA~l), that is, to the memory unit in which video information was written duri~g the preceding writing inter~al or operation. The fa~ling edge of the output or pulse (Fig~ 9J) from MM 60 in w~ite clock generator 20 is employed to trigger a monostable m~ltivibrator (~) 161 which produces a pulse of 40 microsecond d~ration (Fig. 9~) applled th~3ugh an OR gate 162 to al~ of the AND gates 157-160. Thus~ durin~ the existence . .

76Z~S

of the output frs:~m MM 161, the control output or signal from decoder 156 can pass th~gh the one of A~D ga~es 157-160 corresponding to ~he memo~y unit identified by the address ar~l can close a respective one o~ four normally open switches 163,164,165 and 166. Upon closin~ of a selec~ed one of switches 163-166 ,, the veloci~y error held in circuit 33 and which relates to the velocity error occurring durin$ a preceding writing inter~al9 that ~s, the interval of writing in the memory unit identi:Eied by address ~WRA L~, is appl~ed throu~h switch 150, buf~er amplifier 151 (Fig. 9N) and the closed one of switch~s 163-166 to a respective one of four analog memories 167,168,169 and 170, which are shown as ~rounded c~pacitors cotmected to respect~ve buffer amplifiers 171,172p ~73 and 174 ha~ring high input impedances. Thus, during the writing of digital video infor~ation in the memory units ~U-4 of maîr~ m~nory 21, the velocity error information held i~ circuit 23 (Fig. 9L) in respec~ to the writing in each such main memory unit~ is stored in the next writing interval in a respective one o a~alog mernories 167-170. The storage of ~relocity error information is in the form of a build-up of potenti3.1 (Fig. 9R~ to a correspc~nding level on the capacitor selected by the closing of one of switches 163-166 In order to provide for the read ou~ of the stored velocity error information during the normal reading operation o main me~ory 21, the finally determined read address FOR~ is applied from switch 87 of system control ~!3 to a decoder L75 ~7~ 5 in veloci~cy error memory 32. Deeoder 175 is operati~Te to provide control signals or outputs or selectively closing normally open swi~ches 176,177,178 and 179 interposed between the outputs of bufer ampli:Eiers 171,172,173 and 174, respectively, and a co~non Line 180 for applying the read out velocity error information to the read clock geneEI tor ~7. It will be apparent ~hat, during the reading of the digital video information suecessively from the memory uni~s of main memory 21 identified by She f ir~ally determined read address FDRA, FDRA ' ---etc O (Fig .
9S~, decoder 175 causes closing of a selected one of switches 176-179 during each reading interval or period for applying to the common line 180 the stored velocity error information from the one o~ analog memories 167-170 corresponding to the main memory unit from which video infonnation is being read.
li~en the logic output IG from logic circuit 89 ~s at its high levellll" so as 'co cause l~he rewri'cing ~n the memory Utlit identified by the possible rewrite address PRWRA
of the digital video information being read out ~Pom the memory unit identiXied by th~ finally det~rmlned read address FDRA' "
such high lev~l logic output LG closes switch 152 ~o tha~ read start pulse RST can trigger MM 153, whereupon ~he output (Fig.
9T) from the latter changes-over switches 150 and 154 to engage the~r respecti~e contacts A, Upon engagement of switch lS0 w~th its contact A, the velocity error VE being read out of the one of analog memories 167~170 w~.ch corresponds with the memo~y unit identified by the finally determined read address : ' r ~49~

~ 7 6'~ ~5 FDRA' is applied through switch 150 to buffer amplifier 151 (Fig. 9V). The engagement of switch 154 with its contact A
causes the possible rewrite address PRI~ to be applied to decoder 156 so that the latter applies a co~ ral signal or output to the one o~ AND gates 157-160 corresponding to such address. Since the output of M~ 153 is appLied th~ ugh OR gate 162 to all of AND gates 157-160, such output f~om MM 153 passes ~hu~gh the one of AND gates 157~160 receiYing a rontrol sig~al or output from decoder 156 so as to cause closing of the respect~ve one of switches 163-166. Therefore9 the output of buffer ampLifier 151 is app~ied th~ough the closed one of switch~s 163-166 for storage in the respective one of analog memories 160-170 corre~ponding to the main memory unit which is identified by ~he possible rewrite address PR~RA.
It will be apparent from the above that, during the rewrite in the memory unlt identified ~y the address PRWRA
of the digitized video information being read out of the memory unit ~dentified by the address FDRA', ~he velocity error being read out o the analo~ memoxy corresponding to the adress FD~A' ~9 sim~ltaneously rewritten in the analog memory identifed by the addres~ PRWRA. Thus, during subsequent reading o~ the v~deo information that has been rewritten in a ~emory unit of main memory 21, the ~eloc~ty error memory 32 will simultaneously provide a velocity error corresponding to tha~ which existed d1ring the orLginal wri~ing of the rewritten video information~

: 5~-:

P~XAD CLOCK GENERATOR
Referring now to ~ig. 8, it will be seen that the read clock gene~ator 28 of the tLme base corrector 10 according ~o this invention may include a sawtooth generator 181 which receives the velocity error signal VE from the output line 180 of veloci~cy error memory 32. Further, the read command RCD
~rom counter 71 o~ system control 23 ;s applied to an inverter 182 hav:ing ~ts output conrlected to sawtooth genera~or 181 so that ~he output o:E the l~tter re}slains zero dur;ng the time when the output of inverter 182 i~ at a high level t'l", that is, in the intervals betweer~ success~ve read cornmands RCD. A
sub-carrier signal SC~ for example~ having the frequency 3.58 MHz irl the case o the processing o NTSC color video signals9 is applie~ rom the s'candard sync generator 26 to a phase modulator 183 for phase modulation in the latter by the outptlt of sawtooth generator 181, Since the inclirlation o the sawtooth wav~ forming the outpu~ of generatox 181 is proportional to the .. potential of the velocity error signal VE received by generator 181 from velocity error memory 32, the output of modulator 183 is the subcaxricr signal phase modulated by the veloc:l.ty error signal. T~le phase modulated subcarrier signal is applied to a monostable multivibrator 184 which produces a corresp~ndingly phase modulated square wave signal and the harmonics thereuf.
The output of MM 184 is applied to a band pass fi:Lter 185 which is tu~ed to the third harmonic o:~ the subcarrier signal SC so .

:~ -51~ :
,, :

- - - .. .. . , ~ .. . - - .:-.. . ~. . . .-~)76Z45 that the phase modulated output of band pass ~ilter 185 has a frequency of, for example, 10.74 MHz. F;nally, the output o~
band pass filter 185 is supplied through an ampli~ier 186 to a square-wave former 187 to provide the desired read clock p~lse P~CK modulated by the velocity error and which, as previously ~o~ed, determine the clocking rate at which the digitized video info~ma~ion ~s read out of main memory 21.
Having described the general arrangement of ~he vari~us components of the time base corrector 10 according to this in~en~ion and the details of such components9 it ~ill be noted that, in ~uch tLme base corrector, the control of the sequencin~ of the counter 73 by the digital comparator 74 ensures that, duri~g each reading interval, the memory unit of main memory 21 identifled by the read address RA from counter 73, and hence from which video information is being read, will be diferent rom the memory unit identified by ~he write address 9 and he~ce in which the video informa~ on is bein~ written~
whereby to avoid the so-called doubLe clocking o~ any one of the memory units. Furthe~, in the time base corr~ctor 10, a ~rop-out indication DOI is provided whenever a drop-out occurs in the video information being written in any one of the ~i memory units of the main memory 21 and such drop-out indica~ion is s~ored in the drop-out memory 35 in respect to each of the ~:~ mai~ memory uni~s. Upo~ reading out of the ~ideo informa~ion . ~. ..
stored in the ~uccessive memory uni~s of main memory 21, the ` . . .

, .

~L~76245 system controL 23 causes reading of the video information either from the memory unit identified by ~he read address RA provided by coun~er 73 or, in the event that the drop-out memory 35 indicates that there is drop-out in the ~ideo informa~ion s~ored n such memory unit a~ ~he read add~ess RA, then from another memory unît identifed.by the ~pare read address SRA.
Thus, actual reading i~ ef~ected in respeGt to the memory unit identi~ied by ~he finally determined read address FDRA. In determining the spare read address SRA as being either RA-l or RA+l, th digital comparator 76 and FF 77 of system control 23 ensure that such spare read address SRA, if it becomes the finally detenmlned read address FDRA, will not result in double clocki~g of the respective memory unit, that is~ the write address WRA a~d the finally ~etermined r~ad address FDRA
will not be the same to cause overlapping writing and rea~ing opera~ion~ in respec~ to the same memory unit.
Fu~thermore, in time base correc~or 10 according to this inventio~, i ~ ~s determined that drop-out exists in the memory unit ide~tlfied by r~ad address RA so that the ~i~ally determined read address FDRA is the spare read address SRA, then the video infoxmation being read ou~ of the memory unit identified by the address SRA is rewritten in the memory unit ha~ing dropout~ that is the memory unit identified by the read address RA which then beco~es the possible rewrite address PRWRA.

. .
-53~

.

~ 6~ ~ 5 Conversely, if it is determined that drop~o~t exists in the memory unit identified by the spare read address SRA, but not in the memory uni~ identified by the address RA, then video information is actually read out of the memory unit identified by the address RA and is rewritten in the memory unit identiied by the address SRA. In connection wi~h the foregoing rewr~ting, or replacing o~ video info~mation containing drop-ou~ by video information free of drop-out, it will be noted tha~ the drop-out ~emory 35 is e~fective to era~e the drop-out indication in raspect ~o the memoxy uni~ in which ~he rewriting opera~ion is being performed.
.. It w~ll be further apparent that, in time base corrector 10 according to 'chis invention,yelocity error memory 32 memorizes the velocity errors occurring during the writi~g of ~ideo inormatio~ in each of the memory units of main memory ., .
21~ and ea~h ~ch velocity error is employed in read clock ~en~ra~or 28 for phase modulating the read clock pulses RCK
which ~etermine ~he clocking rate on reading the v~deo information frcm the respecti~ one of the memory units~ Moreover~ when ~ideo infsrmation from a memory unit at address FDRA is rewritten in a memory u~it at address PRI~RA, as dPscribed above, the velocfty errcr memory 32 is effective to store, in respect to such memory unit PRW~A, the velocity error associa~ed with the original writing of the video infonmatbn in the memory unit at the address F~RA. Thus, the phase modulation of ~he read 3L~7~ LS

clock pulses RCK will always correspond to the velocity errors occurring dllring the writing of the video information which is being read from a selected one o~ the memory units, whether such video informati on was originally written in that memory unit or rewritten in the lat~er so as to replace originally written video information containing drop-out.
Although a specific embodiment of he invention has been described herein with reference ~o the accompanying drawings, ~t is to be noted ~ha~ ~he invention is not limited tv that precise e~nbod~ent, and that ~rarious changes an~
modifications may be effected therein by one skilled in the ar~ without departing from the scope or spirît of the invention a~ defined in the appended claims.

.

- ~55- ~ -- ~ .: . : - . .

Claims (13)

(S76P108) WHAT IS CLAIMED IS:

1. A time base corrector for removing time base errors from video signals comprising: main memory means including a plurality of memory units each having a capacity sufficient to store a predetermined whole number of line intervals of the video signals; input means for receiving the video signals;
write clock generating means coupled to said input means for generating write clock pulses at a variable rate dependent upon time base errors in the incoming video signals; read clock generating means for generating read clock pulses at a rate which is standard at least at the beginning and end of each standard line interval of the video signals; main memory control means for selectively enabling said memory units to write therein the video signals received from said input means at a clocking rate determined by said write clock pulses, and for selectively enabling said memory units to read out therefrom, at a clocking rate determined by said read clock pulses, the video signals written in said memory units; output means for receiving the video signals selectively read out from said memory units; drop-out detecting means for providing drop-out information in respect to the video signals received by said input means; drop-out memory means having a plurality of addresses respectively corresponding to said memory units for `
storing said drop-out information in respect to the video signals written in the respective memory units; and system control means including write addressing means generating write addresses of said memory units in a repeating cyclic order for causing said main memory control means to selectively enable said memory units in said repeating cyclic order for the writing therein of the video signals received from said input means, and read addressing means responsive to the drop-out information stored in said drop-out memory means for generating read addresses causing said main memory control means to selectively enable the thereby read addressed memory units for the reading-out of the video signals stored therein, with each memory unit thus addressed for reading-out being different from the memory unit then addressed for writing and further being a memory unit storing video signals free of drop-out as indicated by the drop-out information at the respective address in said drop-out memory means.

2. A time base corrector according to claim 1; in which said main memory control means includes rewriting means for selectively rewriting, in any one of said memory units, video signals being read-out of any other one of said memory units; said system control means further includes means responsive to the drop-out information stored in said drop-out memory means for causing said rewriting means to rewrite in a selected one of said memory units, indicated by the drop-out information at the respective address to be storing video signals containing drop-out, the video signals being read-out of the memory unit then enabled for reading-out; and said drop-out memory means includes means operative upon the rewriting in said selected one of the memory units for erasing the drop-out information at the respective address of said drop-out memory means.

3. A time base corrector according to claim 2;
further comprising velocity error memory means having a plurality of addresses respectively corresponding to said memory units for storing velocity error information in respect to velocity errors in the video signals as written in the respective memory units of said main memory means, and means responsive to said rewriting of video signals in a selected one of said memory units for substituting, at the respective address of said velocity error memory means, the velocity error information corresponding to the video signals being rewritten in said selected-one of the memory units for the velocity error information corresponding to the video signals originally written in said selected one of the memory units.

4. A time base corrector according to claim 3; in which said velocity error memory means includes means responsive to said read addressing means of the system control means for selectively reading-out the velocity error information from the address thereof which corresponds to the one of said memory units then enabled for said reading-out of the video signals therefrom; and said read clock generating means includes means for modulating said read clock pulses with the velocity error information being read-out of said velocity error memory means.

5. A time base corrector according to claim l;
further comprising velocity error memory means having a plurality of addresses respectively corresponding to said memory units and including means responsive to said write addressing means of the system control means for selectively writing, at said addresses, velocity error information in respect to velocity errors occurring in the video signals as written in the respective memory units, and means responsive to said read addressing means of the system control means for selectively reading-out the velocity error information from the address of said velocity error memory means which corresponds to the one of said memory units then enabled for said reading-out of the video signals therefrom; and in which said read clock generating means includes means for modulating said read clock pulses with the velocity error information being read-out from said velocity error memory means.

6. A time base corrector according to claim 5; in which said write clock generating means includes a variable frequency oscillator having an output with a center frequency which is a multiple of a color subcarrier frequency of said video signals, phase-locked loop means receiving said oscillator output and horizontal sync signals separated from the video signals received by said input means for varying the frequency of said oscillator output in accordance with variations in the frequency of said separated horizontal sync signals, variable phase shifting means, means for applying said oscillator output to said variable phase shifting means so as to obtain said write clock pulses at the output of said variable phase shifting means, phase comparator means for comparing the phase of said output from the variable phase shifting means with the phase of burst signals at said subcarrier frequency separated from said video signals received by said input means and for providing a corres-ponding control signal to said variable phase shifting means;
and further comprising means for applying said control signal from said phase comparator means to said velocity error memory means as said velocity error information to be written in the latter.

7. A time base corrector according to claim 1; in which said read addressing means includes read address generating means for providing main read addresses which are different from the write addresses simultaneously generated by said write addressing means, means for providing alternate read addresses which are one higher and one lower, respectively, than said main read addresses, means for selecting, as a spare read address, the one of said alternate read addresses which is also different from the write address then generated by said write addressing means, and means responsive to said drop-out information from said drop-out memory means for selecting, as a finally determined read address for said main memory control means, the one of said main and spare read addresses which identifies a memory unit storing video signals free of drop-out.

8. A time base corrector according to claim 7; in which said main memory control means includes rewriting means for selectively rewriting, in any one of said memory units, video signals being read-out of any other one of said memory units; said system control means further includes means for selecting the other of said main and spare read addresses as a possible rewrite address, and means responsive to the drop-out information in said drop-out memory means indicating storage in the memory unit identified by said possible rewrite address of video signals having drop-out for causing said rewriting means to rewrite, in said memory unit identified by said possible rewrite address, the video signals being read-out from the memory unit identified by said finally determined read address.

9. A time base corrector according to claim 8; in which said drop-out memory means includes means operative upon the rewriting in said memory unit identified by said possible rewrite address to erase the drop-out information at the respective address in said drop-out memory means.

10. A time base corrector according to claim 9;
further comprising velocity error memory means having a plurality of addresses respectively corresponding to said memory units for storing velocity error information in respect to velocity errors in the video signals as written in the respective memory units of said main memory means, and means responsive to said rewriting of video signals in the one of said memory units identified by said possible rewrite address for substituting, at the respective address of said velocity error memory means, the velocity error information corresponding to the video signals being rewritten in said one of the memory units for the velocity error information corresponding to the video signals originally written in said one of the memory units.

11. A time base corrector according to claim 10; in which said velocity error memory means includes means responsive to said finally determined read address from the read addressing means of the system control means for selectively reading-out the velocity error information from the address thereof which corresponds to the one of said memory units then enabled for said reading-out of the video signals therefrom; and said read clock generating means includes means for modulating said read clock pulses with the velocity error information being read-out of said velocity error memory means.

12. A time base corrector according to claim 7;
further comprising velocity error memory means having a plurality of addresses respectively corresponding to said memory units and including means responsive to said write addressing means of the system control means for selectively writing, at said addresses, velocity error information in respect to velocity errors occurring in the video signals as written in the respective memory units, and means responsive to said finally determined read address from the system control means for selectively reading out the velocity error information from the address of said velocity error memory means which corresponds to the one of said memory units then identified by said finally determined read address; and in which said read clock generating means includes means for modulating said read clock pulses with the velocity error information being read-out from said velocity error memory means.

13. A time base corrector according to claim 12; in which said write clock generating means includes a variable frequency oscillator having an output with a center frequency which is a multiple of a color subcarrier frequency of said video signals, phase-locked loop means receiving said oscillator output and horizontal sync signals separated from the video signals received by said input means for varying the frequency of said oscillator output in accordance with variations in the frequency of said separated horizontal sync signals, variable phase shifting means, means for applying said oscillator output to said variable phase shifting means so as to obtain said write clock pulses at the output of said variable phase shifting means, phase comparator means for comparing the phase of said output from the variable phase shifting means with the phase of burst signals at said subcarrier frequency separated from said video signals received by said input means and for providing a corresponding control signal to said variable phase shifting means, and further comprising means for applying said control signal from said phase comparator means to said velocity error memory means as said velocity error information to be written in the latter.