SE424118B - Forfarande for framstellning av halvledarkomponenter med hog sperrformaga - Google Patents

Forfarande for framstellning av halvledarkomponenter med hog sperrformaga

Info

Publication number
SE424118B
SE424118B SE7706667A SE7706667A SE424118B SE 424118 B SE424118 B SE 424118B SE 7706667 A SE7706667 A SE 7706667A SE 7706667 A SE7706667 A SE 7706667A SE 424118 B SE424118 B SE 424118B
Authority
SE
Sweden
Prior art keywords
procedure
manufacturing
semiconductor components
lock
lock semiconductor
Prior art date
Application number
SE7706667A
Other languages
English (en)
Inventor
W Tursky
M Chadda
H Schefer
Original Assignee
Semikron Gleichrichterbau
Ik Mbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semikron Gleichrichterbau, Ik Mbh filed Critical Semikron Gleichrichterbau
Publication of SE424118B publication Critical patent/SE424118B/sv

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/761PN junctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Thyristors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Bipolar Transistors (AREA)
SE7706667A 1976-07-24 1977-06-08 Forfarande for framstellning av halvledarkomponenter med hog sperrformaga SE424118B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2633324A DE2633324C2 (de) 1976-07-24 1976-07-24 Verfahren zum Herstellen von Halbleiterbauelementen hoher Sperrspannungsbelastbarkeit

Publications (1)

Publication Number Publication Date
SE424118B true SE424118B (sv) 1982-06-28

Family

ID=5983823

Family Applications (2)

Application Number Title Priority Date Filing Date
SE7706678A SE7706678L (sv) 1976-07-24 1977-06-08 Forfarande for framstellning av halvledarkomponenter med hog sperrformaga
SE7706667A SE424118B (sv) 1976-07-24 1977-06-08 Forfarande for framstellning av halvledarkomponenter med hog sperrformaga

Family Applications Before (1)

Application Number Title Priority Date Filing Date
SE7706678A SE7706678L (sv) 1976-07-24 1977-06-08 Forfarande for framstellning av halvledarkomponenter med hog sperrformaga

Country Status (9)

Country Link
US (1) US4135291A (sv)
JP (1) JPS5315084A (sv)
BR (1) BR7704608A (sv)
CH (1) CH615046A5 (sv)
DE (1) DE2633324C2 (sv)
FR (1) FR2359507A1 (sv)
GB (1) GB1589733A (sv)
IT (1) IT1080969B (sv)
SE (2) SE7706678L (sv)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2410363A1 (fr) * 1977-11-28 1979-06-22 Silicium Semiconducteur Ssc Procede de fabrication de caisson dans un dispositif a semi-conducteurs
JPS56103447A (en) * 1980-01-22 1981-08-18 Toshiba Corp Dicing method of semiconductor wafer
US4355457A (en) * 1980-10-29 1982-10-26 Rca Corporation Method of forming a mesa in a semiconductor device with subsequent separation into individual devices
BR8203630A (pt) * 1981-06-29 1983-06-14 Westinghouse Electric Corp Dispositivo semicondutor processo de preparacao de uma pluralidade de dispositivos semicondutores apassivados com vidro
FR2542148B1 (fr) * 1983-03-01 1986-12-05 Telemecanique Electrique Circuit de commande d'un dispositif a semi-conducteur sensible du type thyristor ou triac, avec impedance d'assistance a l'auto-allumage et son application a la realisation d'un montage commutateur associant un thyristor sensible a un thyristor moins sensible
US4814296A (en) * 1987-08-28 1989-03-21 Xerox Corporation Method of fabricating image sensor dies for use in assembling arrays
US4904609A (en) * 1988-05-06 1990-02-27 General Electric Company Method of making symmetrical blocking high voltage breakdown semiconductor device
JPH0750700B2 (ja) * 1989-06-27 1995-05-31 三菱電機株式会社 半導体チップの製造方法
US5041896A (en) * 1989-07-06 1991-08-20 General Electric Company Symmetrical blocking high voltage semiconductor device and method of fabrication
KR940016546A (ko) * 1992-12-23 1994-07-23 프레데릭 얀 스미트 반도체 장치 및 제조방법
DE102004063180B4 (de) * 2004-12-29 2020-02-06 Robert Bosch Gmbh Verfahren zum Herstellen von Halbleiterchips aus einem Siliziumwafer und damit hergestellte Halbleiterbauelemente
US8163624B2 (en) * 2008-07-30 2012-04-24 Bowman Ronald R Discrete semiconductor device and method of forming sealed trench junction termination
US20100025809A1 (en) 2008-07-30 2010-02-04 Trion Technology, Inc. Integrated Circuit and Method of Forming Sealed Trench Junction Termination
US8174131B2 (en) * 2009-05-27 2012-05-08 Globalfoundries Inc. Semiconductor device having a filled trench structure and methods for fabricating the same
CN105453250A (zh) * 2013-08-08 2016-03-30 夏普株式会社 半导体元件衬底及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3121279A (en) * 1957-12-31 1964-02-18 Philips Corp Method of fastening connecting wires to electrical component parts
US3414780A (en) * 1966-01-06 1968-12-03 Int Rectifier Corp High voltage semiconductor device with electrical gradient-reducing groove
IE34162B1 (en) * 1969-05-05 1975-02-19 Gen Electric Junction-containing semiconductor pellets and wafers divisible into pellets
US3608186A (en) * 1969-10-30 1971-09-28 Jearld L Hutson Semiconductor device manufacture with junction passivation
FR2100997B1 (sv) * 1970-08-04 1973-12-21 Silec Semi Conducteurs
JPS5137467Y2 (sv) * 1971-08-07 1976-09-14
JPS5235500B2 (sv) * 1972-06-29 1977-09-09
DE2306842C3 (de) * 1973-02-12 1981-10-29 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Herstellen einer Vielzahl von Halbleiterelementen aus einer einzigen Halbleiterscheibe
US3879839A (en) * 1973-06-04 1975-04-29 Ibm Method of manufacturing multi-function LSI wafers
JPS5631898B2 (sv) * 1974-01-11 1981-07-24
JPS5719869B2 (sv) * 1974-09-18 1982-04-24

Also Published As

Publication number Publication date
CH615046A5 (sv) 1979-12-28
JPS5315084A (en) 1978-02-10
DE2633324A1 (de) 1978-01-26
SE7706678L (sv) 1978-01-25
IT1080969B (it) 1985-05-16
FR2359507A1 (fr) 1978-02-17
DE2633324C2 (de) 1983-09-15
BR7704608A (pt) 1978-04-04
US4135291A (en) 1979-01-23
GB1589733A (en) 1981-05-20

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NUG Patent has lapsed

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Effective date: 19900522