SE402493B - Serie-adderare - Google Patents

Serie-adderare

Info

Publication number
SE402493B
SE402493B SE7317458A SE7317458A SE402493B SE 402493 B SE402493 B SE 402493B SE 7317458 A SE7317458 A SE 7317458A SE 7317458 A SE7317458 A SE 7317458A SE 402493 B SE402493 B SE 402493B
Authority
SE
Sweden
Prior art keywords
adderer
series
series adderer
Prior art date
Application number
SE7317458A
Other languages
English (en)
Swedish (sv)
Inventor
J Rabasse
Original Assignee
Cit Alcatel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cit Alcatel filed Critical Cit Alcatel
Publication of SE402493B publication Critical patent/SE402493B/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/504—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
    • G06F7/5045—Adding; Subtracting in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other for multiple operands

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Logic Circuits (AREA)
  • Error Detection And Correction (AREA)
SE7317458A 1972-12-29 1973-12-27 Serie-adderare SE402493B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7247029A FR2212952A5 (ja) 1972-12-29 1972-12-29

Publications (1)

Publication Number Publication Date
SE402493B true SE402493B (sv) 1978-07-03

Family

ID=9109547

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7317458A SE402493B (sv) 1972-12-29 1973-12-27 Serie-adderare

Country Status (11)

Country Link
US (1) US3941990A (ja)
BE (1) BE808706A (ja)
DE (1) DE2363262A1 (ja)
DK (1) DK140612B (ja)
FR (1) FR2212952A5 (ja)
GB (1) GB1451974A (ja)
IE (1) IE38630B1 (ja)
IT (1) IT1006685B (ja)
LU (1) LU69036A1 (ja)
NL (1) NL7400047A (ja)
SE (1) SE402493B (ja)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5557948A (en) * 1978-10-25 1980-04-30 Hitachi Ltd Digital adder
FR2454136B1 (fr) * 1979-04-12 1985-12-06 Materiel Telephonique Additionneur sequentiel rapide
US4368993A (en) * 1981-04-30 1983-01-18 Centronics Data Computer Corporation Replaceable assembly for multicolor printing
GB8707493D0 (en) * 1987-03-28 1987-08-05 Stonefield Systems Plc Cellular array processing
US5105379A (en) * 1990-04-05 1992-04-14 Vlsi Technology, Inc. Incrementing subtractive circuits
EP0489952B1 (de) * 1990-12-11 1998-08-19 Siemens Aktiengesellschaft Schaltungsanordnung zur digitalen Bit-seriellen Signalverarbeitung
CA2135857A1 (en) * 1994-01-03 1995-07-04 Shay-Ping Thomas Wang Neural network utilizing logarithmic function and method of using same
US5958001A (en) * 1994-03-31 1999-09-28 Motorola, Inc. Output-processing circuit for a neural network and method of using same
US5685008A (en) * 1995-03-13 1997-11-04 Motorola, Inc. Computer Processor utilizing logarithmic conversion and method of use thereof
US5644520A (en) * 1995-05-31 1997-07-01 Pan; Shao Wei Accumulator circuit and method of use thereof
US5771391A (en) * 1995-08-28 1998-06-23 Motorola Inc. Computer processor having a pipelined architecture and method of using same
US6385634B1 (en) 1995-08-31 2002-05-07 Intel Corporation Method for performing multiply-add operations on packed data
US7395298B2 (en) * 1995-08-31 2008-07-01 Intel Corporation Method and apparatus for performing multiply-add operations on packed data
US6230253B1 (en) * 1998-03-31 2001-05-08 Intel Corporation Executing partial-width packed data instructions
US6230257B1 (en) 1998-03-31 2001-05-08 Intel Corporation Method and apparatus for staggering execution of a single packed data instruction using the same circuit
US7430578B2 (en) * 2001-10-29 2008-09-30 Intel Corporation Method and apparatus for performing multiply-add operations on packed byte data
CN104202053B (zh) * 2014-07-17 2017-04-19 南京航空航天大学 一种快速n位原码到补码的转换装置和转换方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3264458A (en) * 1963-04-04 1966-08-02 Burroughs Corp Serial binary adder

Also Published As

Publication number Publication date
DK140612B (da) 1979-10-08
GB1451974A (ja) 1976-10-06
LU69036A1 (ja) 1974-07-05
BE808706A (fr) 1974-06-17
IE38630L (en) 1974-06-29
NL7400047A (ja) 1974-07-02
FR2212952A5 (ja) 1974-07-26
DK140612C (ja) 1980-02-25
IT1006685B (it) 1976-10-20
IE38630B1 (en) 1978-04-26
US3941990A (en) 1976-03-02
DE2363262A1 (de) 1974-07-04

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