SE366599B - - Google Patents

Info

Publication number
SE366599B
SE366599B SE15988/70A SE1598870A SE366599B SE 366599 B SE366599 B SE 366599B SE 15988/70 A SE15988/70 A SE 15988/70A SE 1598870 A SE1598870 A SE 1598870A SE 366599 B SE366599 B SE 366599B
Authority
SE
Sweden
Application number
SE15988/70A
Inventor
Santis A De
L Beers
J White
J Moysey
Original Assignee
Burroughs Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Publication of SE366599B publication Critical patent/SE366599B/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words
SE15988/70A 1969-11-28 1970-11-25 SE366599B (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US88053569A 1969-11-28 1969-11-28

Publications (1)

Publication Number Publication Date
SE366599B true SE366599B (de) 1974-04-29

Family

ID=25376496

Family Applications (1)

Application Number Title Priority Date Filing Date
SE15988/70A SE366599B (de) 1969-11-28 1970-11-25

Country Status (10)

Country Link
US (1) US3680058A (de)
JP (1) JPS5113540B1 (de)
BE (1) BE758811A (de)
CA (1) CA945688A (de)
CH (1) CH532288A (de)
DE (1) DE2054830C3 (de)
FR (1) FR2069370A5 (de)
GB (1) GB1336981A (de)
NL (1) NL176888C (de)
SE (1) SE366599B (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3924241A (en) * 1971-03-15 1975-12-02 Burroughs Corp Memory cycle initiation in response to the presence of the memory address
US4028675A (en) * 1973-05-14 1977-06-07 Hewlett-Packard Company Method and apparatus for refreshing semiconductor memories in multi-port and multi-module memory system
US4068299A (en) * 1973-12-13 1978-01-10 Honeywell Information Systems, Inc. Data processing system incorporating a logical compare instruction
FR111574A (de) * 1973-12-13 1900-01-01
US4015246A (en) * 1975-04-14 1977-03-29 The Charles Stark Draper Laboratory, Inc. Synchronous fault tolerant multi-processor system
US4135242A (en) * 1977-11-07 1979-01-16 Ncr Corporation Method and processor having bit-addressable scratch pad memory
CA1128212A (en) * 1979-01-02 1982-07-20 Jerry L. Kindell Apparatus for reformating a binary number
US4467443A (en) * 1979-07-30 1984-08-21 Burroughs Corporation Bit addressable variable length memory system
GB2117945A (en) * 1982-04-01 1983-10-19 Raytheon Co Memory data transfer
US4667305A (en) * 1982-06-30 1987-05-19 International Business Machines Corporation Circuits for accessing a variable width data bus with a variable width data field
US5034900A (en) * 1984-10-05 1991-07-23 Hitachi, Ltd. Method and apparatus for bit operational process
US6552730B1 (en) 1984-10-05 2003-04-22 Hitachi, Ltd. Method and apparatus for bit operational process
JP2520882B2 (ja) * 1986-08-27 1996-07-31 株式会社日立製作所 デ−タ処理装置およびデ−タ処理方法
US5210835A (en) * 1986-08-27 1993-05-11 Ken Sakamura Data processing system having apparatus for increasing the execution speed of bit field instructions
DE3837847A1 (de) * 1988-02-19 1989-08-31 Hercules Computer Technology N Einrichtung und verfahren zum verschieben eines bitfoermigen datenblocks
US7581026B2 (en) * 2001-12-28 2009-08-25 Intel Corporation Communicating transaction types between agents in a computer system using packet headers including format and type fields
US7191375B2 (en) * 2001-12-28 2007-03-13 Intel Corporation Method and apparatus for signaling an error condition to an agent not expecting a completion
US7184399B2 (en) * 2001-12-28 2007-02-27 Intel Corporation Method for handling completion packets with a non-successful completion status
US7099318B2 (en) 2001-12-28 2006-08-29 Intel Corporation Communicating message request transaction types between agents in a computer system using multiple message groups
EP2863566B1 (de) 2013-10-18 2020-09-02 Université de Nantes Verfahren zur Rekonstruktion eines Datenblocks und Vorrichtung zur Verwendung davon

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3109162A (en) * 1959-01-15 1963-10-29 Ibm Data boundary cross-over and/or advance data access system
US3331056A (en) * 1964-07-15 1967-07-11 Honeywell Inc Variable width addressing arrangement
US3374467A (en) * 1965-05-27 1968-03-19 Lear Siegler Inc Digital data processor
US3401375A (en) * 1965-10-01 1968-09-10 Digital Equipment Corp Apparatus for performing character operations
US3387280A (en) * 1965-10-04 1968-06-04 Sperry Rand Corp Automatic packing and unpacking of esi transfers
US3411139A (en) * 1965-11-26 1968-11-12 Burroughs Corp Modular multi-computing data processing system
US3500337A (en) * 1967-09-27 1970-03-10 Ibm Data handling system employing a full word main memory transfer with individual indirect byte addressing and processing
US3581287A (en) * 1969-02-10 1971-05-25 Sanders Associates Inc Apparatus for altering computer memory by bit, byte or word
US3577130A (en) * 1969-10-03 1971-05-04 Fairchild Camera Instr Co Means for limiting field length of computed data

Also Published As

Publication number Publication date
CH532288A (de) 1972-12-31
US3680058A (en) 1972-07-25
NL176888B (nl) 1985-01-16
NL7016736A (de) 1971-06-02
JPS5113540B1 (de) 1976-04-30
GB1336981A (en) 1973-11-14
CA945688A (en) 1974-04-16
DE2054830A1 (de) 1971-06-09
DE2054830C3 (de) 1984-03-01
FR2069370A5 (de) 1971-09-03
BE758811A (fr) 1971-04-16
NL176888C (nl) 1985-06-17
DE2054830B2 (de) 1976-04-08

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