SE319033B - - Google Patents
Info
- Publication number
- SE319033B SE319033B SE14662/64A SE1466264A SE319033B SE 319033 B SE319033 B SE 319033B SE 14662/64 A SE14662/64 A SE 14662/64A SE 1466264 A SE1466264 A SE 1466264A SE 319033 B SE319033 B SE 319033B
- Authority
- SE
- Sweden
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
- G06F2207/4921—Single digit adding or subtracting
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Quality & Reliability (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Detection And Correction Of Errors (AREA)
- Reciprocating, Oscillating Or Vibrating Motors (AREA)
- Error Detection And Correction (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US327915A US3300625A (en) | 1963-12-04 | 1963-12-04 | Apparatus for testing binary-coded decimal arithmetic digits by binary parity checking circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SE319033B true SE319033B (US08197722-20120612-C00042.png) | 1969-12-22 |
Family
ID=23278631
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SE14662/64A SE319033B (US08197722-20120612-C00042.png) | 1963-12-04 | 1964-12-04 |
Country Status (9)
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1524158B1 (de) * | 1966-06-03 | 1970-08-06 | Ibm | Addier-Subtrahier-Schaltung für kodierte Dezimalzahlen insbesondere solche in Byte-Darstellung |
| FR2056229A5 (US08197722-20120612-C00042.png) * | 1969-07-31 | 1971-05-14 | Ibm | |
| US3986015A (en) * | 1975-06-23 | 1976-10-12 | International Business Machines Corporation | Arithmetic unit for use in a digital data processor and having an improved system for parity check bit generation and error detection |
| US4799222A (en) * | 1987-01-07 | 1989-01-17 | Honeywell Bull Inc. | Address transform method and apparatus for transferring addresses |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL197751A (US08197722-20120612-C00042.png) * | 1954-06-04 | |||
| IT557030A (US08197722-20120612-C00042.png) * | 1955-08-01 | |||
| US2914248A (en) * | 1956-03-07 | 1959-11-24 | Ibm | Program control for a data processing machine |
| GB802705A (en) * | 1956-05-14 | 1958-10-08 | British Tabulating Mach Co Ltd | Improvements in or relating to digital calculating apparatus |
| US3046523A (en) * | 1958-06-23 | 1962-07-24 | Ibm | Counter checking circuit |
| US3061193A (en) * | 1958-10-21 | 1962-10-30 | Bell Telephone Labor Inc | Magnetic core arithmetic unit |
| US3063636A (en) * | 1959-07-06 | 1962-11-13 | Ibm | Matrix arithmetic system with input and output error checking circuits |
| US3078039A (en) * | 1960-06-27 | 1963-02-19 | Ibm | Error checking system for a parallel adder |
-
0
- GB GB1054203D patent/GB1054203A/en active Active
-
1963
- 1963-12-04 US US327915A patent/US3300625A/en not_active Expired - Lifetime
-
1964
- 1964-11-24 AT AT994364A patent/AT249411B/de active
- 1964-11-24 DE DEP1270A patent/DE1270306B/de not_active Withdrawn
- 1964-12-04 NL NL6414095.A patent/NL155959B/xx not_active IP Right Cessation
- 1964-12-04 CH CH1571464A patent/CH421568A/de unknown
- 1964-12-04 SE SE14662/64A patent/SE319033B/xx unknown
- 1964-12-04 BE BE656664A patent/BE656664A/xx unknown
- 1964-12-09 ES ES0306696A patent/ES306696A1/es not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| GB1054203A (US08197722-20120612-C00042.png) | |
| AT249411B (de) | 1966-09-26 |
| DE1270306B (de) | 1968-06-12 |
| CH421568A (de) | 1966-09-30 |
| NL6414095A (US08197722-20120612-C00042.png) | 1965-06-07 |
| US3300625A (en) | 1967-01-24 |
| BE656664A (US08197722-20120612-C00042.png) | 1965-04-01 |
| NL155959B (nl) | 1978-02-15 |
| ES306696A1 (es) | 1965-04-16 |
