SE300065B - - Google Patents

Info

Publication number
SE300065B
SE300065B SE12432/67A SE1243267A SE300065B SE 300065 B SE300065 B SE 300065B SE 12432/67 A SE12432/67 A SE 12432/67A SE 1243267 A SE1243267 A SE 1243267A SE 300065 B SE300065 B SE 300065B
Authority
SE
Sweden
Application number
SE12432/67A
Inventor
O Avsan
F Hjaelm
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE12432/67A priority Critical patent/SE300065B/xx
Publication of SE300065B publication Critical patent/SE300065B/xx
Priority to US753631A priority patent/US3584207A/en
Priority to GB40303/68A priority patent/GB1171266A/en
Priority to NO3406/68A priority patent/NO120167B/no
Priority to BE720342D priority patent/BE720342A/xx
Priority to DE19681774771 priority patent/DE1774771B2/de
Priority to FR1581830D priority patent/FR1581830A/fr
Priority to DK430568AA priority patent/DK131406B/da
Priority to NL6812751A priority patent/NL6812751A/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Logic Circuits (AREA)
SE12432/67A 1967-09-08 1967-09-08 SE300065B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Priority Applications (9)

Application Number Priority Date Filing Date Title
SE12432/67A SE300065B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1967-09-08 1967-09-08
US753631A US3584207A (en) 1967-09-08 1968-08-19 Arrangement for carrying out alternatively addition or one of a number of logical functions between the contents in a position of two binary words
GB40303/68A GB1171266A (en) 1967-09-08 1968-08-22 Arithmetic and Logic Circuits, e.g. for use in Computing
NO3406/68A NO120167B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1967-09-08 1968-09-02
BE720342D BE720342A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1967-09-08 1968-09-03
DE19681774771 DE1774771B2 (de) 1967-09-08 1968-09-03 Anordnung, um wechselweise eine addition oder eine aus einer anzahl logischer funktionen zwischen den stellenwerten zweier binaerwoerter durchzufuehren
FR1581830D FR1581830A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1967-09-08 1968-09-06
DK430568AA DK131406B (da) 1967-09-08 1968-09-06 Apparat til ved hjælp af fælles logiske kredsløb at udføre enten en sumdannelse eller en af et antal valgbare logiske funktioner imellem indholdet i en position i to binære ord.
NL6812751A NL6812751A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1967-09-08 1968-09-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE12432/67A SE300065B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1967-09-08 1967-09-08

Publications (1)

Publication Number Publication Date
SE300065B true SE300065B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1968-04-01

Family

ID=20295717

Family Applications (1)

Application Number Title Priority Date Filing Date
SE12432/67A SE300065B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1967-09-08 1967-09-08

Country Status (9)

Country Link
US (1) US3584207A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
BE (1) BE720342A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE1774771B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DK (1) DK131406B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR1581830A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB1171266A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
NL (1) NL6812751A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
NO (1) NO120167B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
SE (1) SE300065B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1957302A1 (de) * 1969-11-14 1971-05-19 Telefunken Patent Volladdierer
US3700868A (en) * 1970-12-16 1972-10-24 Nasa Logical function generator
USH1970H1 (en) 1971-07-19 2001-06-05 Texas Instruments Incorporated Variable function programmed system
US4037094A (en) * 1971-08-31 1977-07-19 Texas Instruments Incorporated Multi-functional arithmetic and logical unit
US4503511A (en) * 1971-08-31 1985-03-05 Texas Instruments Incorporated Computing system with multifunctional arithmetic logic unit in single integrated circuit
US3749899A (en) * 1972-06-15 1973-07-31 Hewlett Packard Co Binary/bcd arithmetic logic unit
US4157589A (en) * 1977-09-09 1979-06-05 Gte Laboratories Incorporated Arithmetic logic apparatus
US4160290A (en) * 1978-04-10 1979-07-03 Ncr Corporation One-bit multifunction arithmetic and logic circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL292437A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1962-05-09
US3291973A (en) * 1964-09-22 1966-12-13 Sperry Rand Corp Binary serial adders utilizing nor gates
US3440413A (en) * 1965-11-17 1969-04-22 Ibm Majority logic binary adder
US3458240A (en) * 1965-12-28 1969-07-29 Sperry Rand Corp Function generator for producing the possible boolean functions of eta independent variables
US3465133A (en) * 1966-06-07 1969-09-02 North American Rockwell Carry or borrow system for arithmetic computations

Also Published As

Publication number Publication date
NO120167B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1970-09-07
US3584207A (en) 1971-06-08
DK131406C (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1975-12-01
NL6812751A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1969-03-11
BE720342A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1969-02-17
FR1581830A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1969-09-19
DK131406B (da) 1975-07-07
DE1774771A1 (de) 1971-12-30
DE1774771B2 (de) 1972-11-30
GB1171266A (en) 1969-11-19

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