RU96708U1 - THREE-LEVEL INVERTER WITH SOFT COMMUTATION - Google Patents

Abstract

 Three-level inverter with soft switching, characterized in that it contains a rack of four series-connected primary keys with anti-parallel diodes, a rack of four series-connected secondary keys with anti-parallel diodes, a rack of two series-connected filter capacitors, each of which is located between positive and negative power bus, a rack of two series-connected fixing diodes, the cathode of which is connected to the connection point the upper key pair in the main key rack, and the anode to the connection point of the lower key pair in the main key rack, while the middle points of the additional key rack, the filter capacitor rack and the fixing diode rack are connected to a common power bus, two consecutive LC circuits, the first of which is connected between the connection point of the upper pair of keys in the rack of additional keys and the cathode of the rack of fixing diodes, and the second between the connection point of the lower pair of keys in the rack of additional keys and the anode of the rack of fix diodes, a load current source, the first pole of which is connected to the midpoint of the main key rack, and the second pole to the neutral point of the load, two additional capacitors, the first of which is connected parallel to the upper key in the main key rack, the second - parallel to the lower key in the rack main keys, while two damping capacitors are introduced into the inverter, each of which is connected in parallel to one of the fixing diodes.

Description

The proposal relates to the field of power electronics, in particular to converter circuits with reduced switching losses in power semiconductor switches and can be used in the development of autonomous inverters and switching regulators.

There is a known scheme of a three-level inverter, in which the four main transistors in each phase of the inverter are gently turned on and off with the help of four additional keys, a parallel switching choke and additional capacitors connected in parallel with the main keys (see US 6205040 B1, 03.20.2001).

The disadvantage of this invention is that the soft shutdown of the main transistors at zero voltage requires the use of additional capacitors with a relatively large capacity. A soft turn on of the main transistors is possible only when the current in the switching choke increases above the load current, which leads to an increase in additional conductivity losses and complicates the control circuit of the inverter.

A technical solution is known (see US 6337801 B2, 01/08/2002), in which the soft shutdown of the main keys of a three-phase inverter is realized at zero current and does not require the use of additional parallel capacitors. However, the inclusion of the main transistors in this circuit occurs at zero current, which does not allow a preliminary discharge of voltage at the output capacities of these transistors and leads to an increase in switching losses.

The closest in technical essence is the solution (see RU 92581 U1, 03/20/2010.), Including a rack of four series-connected main keys with anti-parallel diodes, a rack of four series-connected additional keys with anti-parallel diodes, a rack of two series-connected filter capacitors, each of which is located between the positive and negative power bus, a rack of two series-connected fixing diodes, the cathode of which is connected to the point of connection the upper pair of keys in the main key rack, and the anode to the connection point of the lower key pair in the main key rack, while the midpoints of the additional key rack, filter capacitors and fixing diode racks are connected to a common power bus, two consecutive LC circuits, the first of which is connected between the connection point of the upper pair of keys in the rack of additional keys and the cathode of the rack of fixing diodes, and the second between the connection point of the lower pair of keys in the rack of additional keys and the anode of the rack of fix coding diodes, a load current source, the first pole of which is connected to the midpoint of the main key rack, and the second pole to the neutral point of the load, two additional capacitors, the first of which is connected parallel to the upper key in the main key rack, the second parallel to the lower key in the main key rack .

In this solution, soft switching of both primary and secondary keys is provided. However, the two middle keys in the main inverter rack of the inverter are switched only at zero current. In this case, there is no preliminary discharge of voltage at the output capacities of these keys, which leads to an increase in switching losses.

Another drawback of this circuit is also the increased conductivity loss in the diodes of the main inverter keys, since one of the additional capacitors is recharged through these diodes.

The objective of the utility model is to expand the arsenal of technical means.

The technical result of the proposed device is as follows.

1. The conditions for soft switching of the main and additional circuit keys with a wide change in the load current are ensured by the choice of the necessary values of the damper capacitors in accordance with the newly established criteria.

2. The reduction of switching losses for medium keys in the rack of the main inverter keys is provided by a preliminary discharge of voltage at the output capacities of these keys by connecting damping capacitors.

3. The reduction of additional conductivity losses in the main keys of the inverter is ensured by eliminating overcharging of the damper capacitors through the inverse diodes of these keys.

The technical result is achieved by the fact that the three-level inverter with soft switching contains a rack of four series-connected main keys with anti-parallel diodes, a rack of four series-connected additional keys with anti-parallel diodes, a rack of two series-connected filter capacitors, each of which is located between the positive and negative power bus, a rack of two series-connected fixing diodes, the cathode of which is connected to the connection point of the upper key pair in the main key rack, and the anode to the connection point of the lower key pair in the main key rack, while the midpoints of the additional key rack, the filter capacitor rack and the fixing diode rack are connected to a common power bus, two serial LC circuits, the first of which is connected between the connection point of the upper pair of keys in the rack of additional keys and the cathode of the rack of fixing diodes, and the second between the connection point of the lower pair of keys in the rack of additional keys and the anode ohm of the rack of the fixing diodes, the load current source, the first pole of which is connected to the midpoint of the main key rack, and the second pole to the neutral point of the load, two additional capacitors, the first of which is connected parallel to the upper key in the main key rack, the second parallel to the lower key in the rack main keys, while two damping capacitors are introduced into the inverter, each of which is connected in parallel to one of the fixing diodes.

Figure 1 presents a three-level inverter with soft switching.

Figure 2 presents the scheme of the prototype.

Figure 3 presents the equivalent half-bridge circuit with the main keys 1 and 3.

Figure 4 presents the equivalent half-bridge circuit with the main keys 4 and 2.

Figure 5 presents the calculated waveform of the voltage on the main switch 3 of the inverter and the damper capacitor 26.

Figure 6 presents the calculated waveform of the voltage on the main key 3 of the inverter in the prototype circuit.

The device contains: a rack of four series-connected primary keys 1, 2, 3 and 4 with counter-parallel diodes, a rack of four series-connected additional keys 5, 6, 7 and 8 with anti-parallel diodes, a rack of two series connected filter capacitors 9 and 10, a rack of two series-connected fixing diodes 11 and 12, a positive 13 and a negative 14 power bus, a common bus 15, two consecutive LC circuits 16 and 17, the first of which contains a reactor 18 and a capacitor 19, and second The first contains a choke 20 and a capacitor 21, a load current source 22, a neutral point of load 23, two additional capacitors 24, 25, and two damper capacitors 26 and 27.

The rack of the main keys 1, 2, 3 and 4, the rack of additional keys 5, 6, 7 and 8, as well as the rack of filter capacitors 9 and 10 are located between the positive 13 and negative 14 power bus. The cathode of the rack of the fixing diodes 11 and 12 is connected to the connection point of the upper pair of keys 1 and 2 in the main key rack, and the anode of the rack of the fixing diodes 11 and 12 is connected to the connection point of the lower pair of keys 3 and 4 in the main key rack, while the middle points of the rack additional keys 5, 6, 7 and 8, racks of filter capacitors 9 and 10 and racks of fixing diodes 11 and 12 are connected to the common power bus 15. Serial LC circuit 16 is connected between the connection point of the upper pair of keys 5 and 6 in the rack of additional keys and cathode rack fixing diodes 11 and 12, and a serial LC circuit 17 between the connection point of the lower pair of keys 7 and 8 in the rack of additional keys and the anode of the rack of fixing diodes 11 and 12. The first pole of the load current source 22 is connected to the midpoint of the rack of the main keys 1, 2, 3 and 4, and the second pole of the load current source 22 to the neutral point of the load 23. The first additional capacitor 24 is connected in parallel to the upper key 1 in the main key rack, the second additional capacitor 25 is connected in parallel to the lower key 4 in the main key rack, the first dump The black capacitor 26 is connected in parallel clamp diode 11, and second damper capacitor 27 is connected in parallel clamp diode 12.

The inventive device operates as follows.

To generate the phase voltage of the load with the required harmonic composition, pulse-width modulation (PWM) is used when switching the main transistors 1, 2, 3 and 4. The width of the conductivity pulses of the main transistors is modulated within each period of the inverter output frequency according to a certain law. In the three-level scheme of the inverter, the PWM concept, based on the phase-matching of the reference signals of the carrier frequency, known in the English abbreviation as Phase-Disposition, is most widely used. With this control principle, the operation of a three-level circuit is reduced to the sequential operation of two equivalent half-bridge circuits, in the first of which the load current is switched between switches 1 and 3 (Figure 3), and in the second between switches 4 and 2 (Figure 4). The role of antiphase diodes for keys 1 and 4 is played by fixing diodes, respectively, diode 11 and diode 12. And for keys 3 and 2, antiphase diodes are counter-parallel diodes, respectively, of keys 1 and 4.

Then, soft switching in each of the half-bridge circuits can be achieved using two series-connected additional keys connected in parallel to the half-bridge power buses, and a serial L-C circuit connected between the midpoints of the connection of the main keys of the half-bridge circuit and these additional keys.

Consider soft switching in the equivalent half-bridge circuit (Figure 3) with keys 1 and 3, which occurs on the conduction interval from zero to π-φ (where φ is the angle of the phase voltage and current shift).

The power source of this half-bridge is a filter capacitor 9. Between the power buses of the half-bridge circuit, additional keys 5 and 6 are connected. The serial LC circuit 16 is connected between the midpoint of the connection of the additional keys 5 and 6 and the connection point of the main keys of the half-bridge 1 and 3. Note that the connection point primary keys 1 and 3 is formed as a result of the open state of key 2, which remains in this state for the entire interval of operation of the specified half-bridge circuit.

Suppose that the load current 22 is equal to IH and flows from the connection point of the keys 1 and 3 to the neutral point of the load 23. When the main transistor 1 is turned off, this current is closed to the fixing diode 11, which is out of phase with respect to the transistor 1. In this case, the additional capacitor 24 connected in parallel with the key 1 is charged to a half-bridge supply voltage equal to the voltage on the filter capacitor. We denote this voltage by the symbol E. The damper capacitor 26, which is connected in parallel with the key 3 through the diode 12, is discharged to almost zero.

Before turning on the main key 1, the additional key 6 is turned on. The capacitor 19 of the circuit 16 is charged to the initial voltage U ₀ ⁺ with a positive polarity on its left lining. The specified initial voltage corresponds to the inequality:

where ρ is the characteristic resistance L-C of circuit 16.

The oscillatory process of increasing current in the circuit 16 begins. When this current reaches its maximum, the polarity of the voltage across the capacitor 19 of the circuit changes. For half the period of the resonant frequency, the loop current coincides in the direction with the load current, and then reverses the direction. When the current of the inductor 18 in the circuit 16 reaches the value of the load current the fixing diode 11 is turned off. In this case, the voltage across the capacitor 19 is equal to:

After turning off the locking diode 11 between the serial L-C circuit 16 and the capacitors 24 and 26, a quasi-resonant process begins.

We establish the criterion for soft inclusion of key 1 at zero voltage.

The additional capacitor 24, connected in parallel with the key 1, is completely discharged (accordingly, the damper capacitor 26 is fully charged to the voltage of the power source E) using a quasi-resonant process, if the inductance of the inductor 18 of the circuit 16 accumulates at least energy that corresponds to the load current (i.e. . ), and the voltage across the capacitor 19 U _С19 (t) of circuit 16 in the interval of overcharging of capacitors 24 and 26 satisfies the inequality:

where: U _С24 (0) is the initial voltage across the capacitor 24.

Given that U _С24 (0) = E, condition (3) can be rewritten in the form:

T.O. the voltage on the capacitor 19 of the circuit 16 in the interval of overcharging of the capacitors 24 and 26 should remain at least half the value of the supply voltage of the half-bridge.

After the capacitor 24 is completely discharged, switch 1 can be turned on at zero voltage.

The voltage on the capacitor 19 of the circuit 16 after a complete discharge of the capacitor 24 becomes equal to:

where ΔU is the change in voltage across the capacitor 19 of circuit 16 over the interval Δt _{p of the} overcharge of capacitors 24 and 26.

The current in the inductor 11 of the circuit 10 after a full discharge of the output capacitance of the key 1 becomes equal to:

where ΔI is the change in current in the inductor 18 of the circuit 16 in the interval Δt _p .

In the absence of capacitors 24 and 26, ΔU and ΔI can be considered practically equal to zero.

When connecting these capacitors:

Where: ;

After turning on the main switch 1 at zero voltage, the current in the inductor 18 of the circuit 16 begins to decrease, and accordingly, the current in the switch 1 starts to increase. When the current of the key 1 reaches the load current, the current of the inductor 18 becomes equal to zero. The voltage on the capacitor 19 of the circuit 16 is equal to:

Since the polarity of the voltage across the capacitor 19 of circuit 16 has reversed as compared to the original, when the additional switch 5 is turned on at the corresponding time, it is possible to turn off the main switch 1 at zero current if the condition is fulfilled:

In this case, the current of the oscillating circuit 16 begins to increase counter to the load current passing through the public key 1. At the moment of the equality of the loop current and the load current, the counter-parallel diode of the main switch 1 is turned on, through which the difference of the indicated currents then flows.

Obviously, turning off the key 1 must be done before the equality of these currents.

Note that at the time when the current of the circuit 16 reaches its maximum value, the voltage across the capacitor 19 again changes its polarity and then increases. However, the level of this voltage is much lower than the initial, equal to U ₀ ⁺

To ensure the stability of the soft switching cycles of key 1, it is necessary to raise the level of this voltage to the original value. To this end, when the main key 1 is turned off at zero current, the additional key 5 is left open. The current in the L-C circuit at the time the main switch 1 is turned off is equal to the load current. The out-of-phase diode of the key 1 (i.e., the fixing diode 11) remains in the off state, since the voltage on the capacitor 19 of the circuit 16 is much less than the supply voltage E. Thus the only way to close the load current is through the serial LC circuit 16. In this case, the load current starts charging the capacitor 19. When the voltage at the indicated capacitor reaches the supply voltage E, the diode 11 opens, and another quasi-resonant process begins in the oscillating circuit 16, after which the voltage to the capacitor 19 is set equal to the initial:

After determining the initial voltage U ₀ ⁺ on the capacitor 19, you can select the values of additional LC circuit elements at which the criterion for turning on the main switch 1 at zero voltage and the criterion for turning it off at zero current will be fulfilled.

Using equations (2) and (4), it can be established that the criterion of zero voltage is satisfied if the characteristic resistance of circuit 16 satisfies the condition:

On the other hand, according to equation (10), the zero current criterion is satisfied if the characteristic resistance of the circuit satisfies the condition:

Thus, it is necessary to choose a lower resistance value ρ from formulas (12) and (13) so that both of the criteria for soft switching are satisfied.

The greater the load current, the more difficult it is to fulfill the soft switching criteria. Therefore, the selection of the ratings of additional circuit elements satisfying the indicated restrictions should be carried out for maximum load current. For all other current values below the maximum condition, soft switching of the main inverter keys will be performed automatically.

The dynamic processes in the additional keys 5 and 6 of the device in question are also soft, since the change in current in these transistors is determined by a smooth change in current in the oscillatory L-C circuit. In additional keys 5 and 6, there is no preliminary discharge of their own output capacities before switching on, which in general leads to additional losses. However, since the operation of these keys occurs at relatively short time intervals, keys are used whose average current value is several times smaller than in the main keys. For this reason, the output capacities of the additional keys are relatively small.

With a change in the direction of the load current, i.e. when it flows from the neutral point of load 23 to the connection point of keys 1 and 3, when the main key 3 is off, this current will be closed to the on-parallel diode of the main key 1. Similarly to the considered stages of soft switching of the main key 1, it is now possible to carry out soft switching of the load current at switching the main key 3. For this purpose, before turning on the key 3, the additional key 5 is unlocked. Then, processes similar to those previously discussed proceed with the proposed device, with one exception. With quasi-resonant recharging of the capacitors 24 and 26, the discharge of the own output capacitance of the main key 3 passes through a damper capacitor 27 connected in parallel with the fixing diode 12. This is due to the fact that the key 3 at this time interval is separated from the quasi-resonant circuit by means of the fixing diode 12, which is in the process the overcharging of the capacitors 24 and 26 is in the locked state. In this case, the inclusion of the main switch 3 at zero voltage is provided provided that the capacitance of the damper capacitor 27 is much greater than the own output capacity of the main switch 3.

Further, before turning off the main key 3, an additional key 6 is turned on, which provides conditions for turning off the key 3 at zero current.

Soft switching in the equivalent half-bridge circuit with keys 4 and 2 (Figure 4) occurs in the conductivity interval from (π-φ) to 2π. All processes in this half-bridge are similar to those considered earlier for the equivalent half-bridge circuit with the main keys 1 and 3 (Figure 3).

The recharge of the damper capacitors 26 and 27 due to the quasi-resonant process is not associated with the flow of currents of their discharge through counter-parallel diodes of the main switches 2 and 3, which distinguishes the proposed device from the prototype circuit and thereby reduces additional conductivity losses.

The presented device provides soft switching of the load current for a single phase. Since the considered processes are autonomous in nature, using three similar devices can be provided with soft switching conditions for the twelve main keys in a three-phase circuit.

The principle of operation of the device and the criteria for soft switching do not change when applying different types of keys (TIR, IGBT, IGCT, etc.).

An example of a specific implementation of the proposed device on IGBT.

The voltage of the inverter power supply is 2E = 640 V (the voltage E = 320 V on each of the filter capacitors).

Load current I _H = 100 A.

The main switches 1, 2, 3 and 4, as well as the fixing diodes 11 and 12, are the power module (three-phase bridge for a three-level inverter with a fixed zero point), voltage class 600 V, average current 100 A.

Additional keys 5, 6, 7 and 8 - power module (three-phase bridge), voltage class 600 V, average current 50 A, pulse current 400 A.

Inductors 18 and 20 in consecutive L-C circuits 16 and 17 - inductance 0.6 μH.

Capacitors 19 and 21 in serial L-C circuits 16 and 17 - 1 μF capacitance, voltage 630 V.

Additional capacitors 24, 25 and damping capacitors 26, 27 - capacitance 22 nF, voltage 630 V.

Modeling of the proposed device was carried out in the calculation program of electronic circuits PSpice.

Figure 5 presents the calculated waveform of the voltage on the main switch 3 of the inverter (channel 2) and the damper capacitor 26 (channel 1). The channel arrows indicate the zero voltage level of the corresponding channel.

Vertical Scale:

Voltage is 100 V / div.

Horizontal Scale:

Time - 500 ns / div.

When quasi-resonant discharge of the capacitor 26 using a capacitor 27 connected in parallel to the diode 12, there is also a discharge of the output capacitance of the main switch 3.

Figure 6 presents the calculated waveform of the voltage on the main switch 3 of the inverter (channel 2) in the prototype circuit and an additional capacitor - an analog of the capacitor 26 (channel 1). The channel arrows indicate the zero voltage level of the corresponding channel.

Vertical Scale:

Voltage - 100 V / div.

Horizontal Scale:

Time - 500 ns / div.

When the quasi-resonant discharge of the additional capacitor (analogue of the capacitor 26) practically does not discharge the output capacitance of the main key 3, since the own output capacitance of the fixing diode 12 in the prototype circuit is relatively small.

Claims (1)

Three-level inverter with soft switching, characterized in that it contains a rack of four series-connected main keys with anti-parallel diodes, a rack of four series-connected additional keys with anti-parallel diodes, a rack of two series-connected filter capacitors, each of which is located between positive and negative power bus, a rack of two series-connected fixing diodes, the cathode of which is connected to the connection point the upper key pair in the main key rack, and the anode to the connection point of the lower key pair in the main key rack, while the middle points of the additional key rack, the filter capacitor rack and the fixing diode rack are connected to a common power bus, two consecutive LC circuits, the first of which is connected between the connection point of the upper pair of keys in the rack of additional keys and the cathode of the rack of fixing diodes, and the second between the connection point of the lower pair of keys in the rack of additional keys and the anode of the fixi rack diodes, a load current source, the first pole of which is connected to the midpoint of the main key rack, and the second pole to the neutral point of the load, two additional capacitors, the first of which is connected parallel to the upper key in the main key rack, the second - parallel to the lower key in the rack main keys, while two damping capacitors are introduced into the inverter, each of which is connected in parallel to one of the fixing diodes.