RU94016329A - Electronic puzzle - Google Patents

Electronic puzzle

Info

Publication number
RU94016329A
RU94016329A RU94016329/12A RU94016329A RU94016329A RU 94016329 A RU94016329 A RU 94016329A RU 94016329/12 A RU94016329/12 A RU 94016329/12A RU 94016329 A RU94016329 A RU 94016329A RU 94016329 A RU94016329 A RU 94016329A
Authority
RU
Russia
Prior art keywords
output
flip
additional
flop
trigger
Prior art date
Application number
RU94016329/12A
Other languages
Russian (ru)
Other versions
RU2120320C1 (en
Original Assignee
Фирма "ВДК"
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Фирма "ВДК" filed Critical Фирма "ВДК"
Priority to RU94016329A priority Critical patent/RU2120320C1/en
Publication of RU94016329A publication Critical patent/RU94016329A/en
Application granted granted Critical
Publication of RU2120320C1 publication Critical patent/RU2120320C1/en

Links

Landscapes

  • Toys (AREA)

Abstract

FIELD: games. SUBSTANCE: device has starting unit, generator of single pulses, n flip-flops, which have information and dynamic inputs, and n delay gates, each of which is connected to output of corresponding flip-flop. Delay time for pulses of delay gates is greater than duration of single pulses generated by pulse generator. In addition device has k additional flip-flops, n+k indicators which are connected to outputs of corresponding flip-flops, and at least one additional generator of single pulses. Dynamic input of each flip-flop is connected to output of at least one pulse generator. Output of each primary flip- flop is connected to its information input through delay gate. Information input of each additional flip-flop is connected to output of corresponding primary flip-flop. Each pulse generator is connected to input of at least two flip-flops which are not connected to one another. EFFECT: development of memorizing capacity and logical reasoning.

Claims (1)

Изобретение может быть использовано при изготовлении игрушек, предназначенных для развития памяти и способностей к логическому мышлению детей младшего школьного возраста. Технической задачей является создание игровых ситуаций. Поставленная задача достигается тем, что в устройство, содержащее пусковой блок, генератор одиночных импульсов, n триггеров, снабженных информационными и динамическими входами, и n блоков задержки, каждый из которых соединен с выходом соответствующего триггера, причем время задержки импульсов блоков задержки больше длительности одиночных импульсов генераторов импульсов, введены k дополнительных триггеров, n + k индикаторов, подключенных к выходу соответствующего триггера, и по крайней мере один дополнительный генератор одиночных импульсов, причем динамический вход каждого триггера соединен по крайней мере с выходом одного из генераторов, выход каждого основного триггера соединен через блок задержки со своим информационным входом, информационный вход каждого дополнительного триггера связан с выходом одного из основных триггеров, а каждый генератор импульсов соединен с входами по крайней мере двух не связанных между собой триггеров.The invention can be used in the manufacture of toys intended for the development of memory and logical thinking abilities of children of primary school age. The technical task is to create game situations. The problem is achieved in that in a device containing a start-up block, a single pulse generator, n triggers equipped with information and dynamic inputs, and n delay blocks, each of which is connected to the output of the corresponding trigger, and the delay time of the pulses of the delay blocks is longer than the duration of single pulses pulse generators, added k additional triggers, n + k indicators connected to the output of the corresponding trigger, and at least one additional generator of single pulses o, and the dynamic input of each trigger is connected to at least the output of one of the generators, the output of each main trigger is connected via a delay unit to its information input, the information input of each additional trigger is connected to the output of one of the main triggers, and each pulse generator is connected to the inputs at least two unrelated triggers.
RU94016329A 1994-04-26 1994-04-26 Electronic puzzle RU2120320C1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
RU94016329A RU2120320C1 (en) 1994-04-26 1994-04-26 Electronic puzzle

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
RU94016329A RU2120320C1 (en) 1994-04-26 1994-04-26 Electronic puzzle

Publications (2)

Publication Number Publication Date
RU94016329A true RU94016329A (en) 1996-08-20
RU2120320C1 RU2120320C1 (en) 1998-10-20

Family

ID=20155514

Family Applications (1)

Application Number Title Priority Date Filing Date
RU94016329A RU2120320C1 (en) 1994-04-26 1994-04-26 Electronic puzzle

Country Status (1)

Country Link
RU (1) RU2120320C1 (en)

Also Published As

Publication number Publication date
RU2120320C1 (en) 1998-10-20

Similar Documents

Publication Publication Date Title
KR890017866A (en) Filter circuit
RU94016329A (en) Electronic puzzle
JPH0542031B2 (en)
KR880013320A (en) Output pulse generator
SU820867A1 (en) Electronic chess information training appliance
JPS5386122A (en) Pattern signal generator
SU744526A1 (en) Equilibrium code shaper
SU832550A1 (en) Digital function generator
SU524199A1 (en) Random process generator
JPS5495126A (en) Display device
JPS54162428A (en) Output circuit of micro processor
KR920015712A (en) Selective pulse generator circuit device
RU2026107C1 (en) Electron game control unit
JPS52154336A (en) Pulse generator circuit
SU675438A1 (en) Pseudorandom pulse train generator
SU720708A1 (en) Ramp oscillator
SU1564682A1 (en) Device for teaching fundamentals of computers and data processing
SU1236539A1 (en) Demonstrating device
SU961720A1 (en) Sportsmen trainer
JPS5382253A (en) Logical operation circuit
JPS56147235A (en) Carry signal generating circuit
KR890004223A (en) Switch-Driven Clock Switching Circuit
JPS63153625U (en)
KR890007502A (en) Test Logic Circuit Using Counter
JPS5491171A (en) Pulse counting system