RU87535U1 - DEVICE FOR DETERMINING THE PARAMETERS OF THE SEQUENTIAL DISPLACEMENT SCHEME FOR THE POWER CONDENSER USING INTEGRAL POWER - Google Patents

Abstract

A device for determining the parameters of a sequential equivalent capacitor circuit using integrated capacities, characterized in that an active resistance and capacitance calculation unit in which the first and second sampling and storage devices are connected in series to the power capacitor in the places of its connection to the power line through the emergency recorder connected to the emergency recorder, and the first programmer and the second a grammer, the output of which is connected to a computer, and a third programmer is connected to the output of the first fetch-storage device, to which a fourth programmer is connected, the output of which is connected to a computer, and the first, third programmers and programmer of effective values are connected to the output of the second fetch-storage device, to the output of which the second and fourth programmers are connected, while a clock generator is connected to each sampling-storage device.

Description

The utility model relates to the field of information processing systems and can be used for functional control and diagnosis of a power capacitor based on its sequential equivalent circuit using integrated capacities.

Devices for determining the parameters of a series equivalent capacitor circuit using integrated capacities are unknown.

The objective of the device is to determine the parameters of a sequential equivalent circuit of a power capacitor using integrated capacities.

The problem is solved due to the fact that the capacitor in the places of its connection to the power line through the emergency recorder is connected in series to the resistance and capacitance calculation unit, in which the first and second sampling and storage devices are connected to the emergency recorder, and to the first sampling device -storage is connected in series with the first programmer and the second programmer, the output of which is connected to a computer. Moreover, a third programmer is connected to the output of the first sample-storage device, to which a fourth programmer is connected, the output of which is connected to a computer. The first, third programmers and the programmer of effective values are connected to the output of the second sampling-storage device, the second and fourth programmers are connected to the output of which. A clock is connected to each sample-storage device.

Using the proposed device circuit, it is possible to determine the parameters of a series capacitor equivalent circuit using integrated capacities: active resistance 1.1 (Fig. 1) and capacitance 1.2 (Fig. 1).

Figure 1 shows the serial equivalent circuit of the power capacitor, where the active resistance 1.1 is connected in series with the capacitance 1.2.

Figure 2 shows the structural diagram of a device for determining the parameters of a sequential equivalent circuit of a power capacitor using integrated power.

Figure 3 shows the hardware circuit of the unit for calculating the active resistance and capacitance 2.

A device for determining the parameters of a sequential equivalent capacitor circuit using integrated capacities contains a block for calculating the active resistance and capacitance 2 (block for calculating R, C), the inputs of which are connected to the connection point of the capacitor to the power line through the emergency recorder, and the outputs of the block for calculating the active resistance and capacity 2 (calculation unit R, C) are connected to the computer 3.

The unit for calculating the active resistance and capacitance 2 (unit for calculating R, C) (Fig. 3) consists of the first 4 (UVX 1) and second 5 (UVX 2) sampling and storage devices, the inputs of which are connected to the emergency recorder. The first programmer 6 (P 1) and the second programmer 7 (P 2), the output of which is connected to the computer 3, are connected in series to the first sampling-storage device 4 (UVX 1). In addition, to the output of the first sampling-storage device 4 (UVX 1) ) the third programmer 8 (P 3) is connected, to which the fourth programmer 9 (P 4) is connected, the output of which is connected to the computer 3. The first 6 (P 1), the third 8 are connected to the output of the second fetch-storage device 5 (UVX 2) (P 3) programmers and a programmer of effective values 10 (PDZ), the output of which is connected to the second 7 (P 2) and four The second 9 (P 4) programmers. A clock generator 11 (TG) is connected to each sample-storage device.

All sampling and storage devices 4 (UVX 1) and 5 (UVX 2) are implemented on 1100SK2 microcircuits. Programmers 6 (П 1), 7 (П 2), 8 (П 3), 9 (П 4) and the programmer of effective values 10 (ПДЗ) can be executed on a microcontroller of a series 51 of the manufacturer atmel AT89853. The clock generator 11 (TG) can be implemented on the AT80C2051 microcontroller.

The device operates as follows. The inputs of the unit for calculating the active resistance and capacitance 2 (unit for calculating R, C) of the device from the emergency recorder provide the following signals: and ,

Where - an array of samples of instantaneous voltage values at the terminals of the power capacitor 1,

- an array of samples of instantaneous current values at the beginning of the power capacitor 1.

The input of the first sample and hold device 4 (SHA 1) receives a signal _{u (t j), i (} t j) signal is input to the second sample-and-storing device 5 (SHA 2)

where t _j = t ₁ , t ₂ , ..., t _n are times,

- the number of partitions on the period T,

∆t is the discretization step of arrays of instantaneous current / voltage values.

The values of the signals are recorded in the blocks of sample-storage 4 (UVX 1) and 5 (UVX 2) and stored there as current. Then, from the outputs of the sampling-storage devices 4 (UVX 1) and 5 (UVX 2), the signals u (t _j ) and i (t _j ) simultaneously arrive at the inputs of programmers 6 (P 1) and 8 (P 3). At the same time, the signal i (t _j ) from the output of the sample-storage device 5 (UVX 2) is fed to the input of the programmer of effective values 10 (PDZ).

At the output of the first programmer 6 (P 1) get the value of the loss of active power AR on the active resistance of the capacitor.

From the output of the programmer 6 (P 1), the value of the active power loss is fed to the input of the second programmer 7 (P 2). At the same time, using the third programmer 8 (P 3) determine the value of reactive power

Q:

From the output of the third programmer 8 (P 3), the value of reactive power is supplied to the input of the fourth 9 (P 4) programmer. At the same time using the programmer of effective values of 10 (PDZ) determine the effective value of current I:

From the output of the programmer of effective values 10 (PDZ), the value of the signal I is supplied to the inputs of the second 7 (P 2) and fourth 9 (P 4) programmers.

Using the second programmer 7 (P 2) get the value of the active resistance of the capacitor 1.1 (figure 1):

At the same time, at the output of the fourth programmer 9 (P 4), a capacitor value of 1.2 is obtained (FIG. 1):

Thus, the utility model allows you to measure the active resistance 1.1 (figure 1) and the capacitance 1.2 (figure 1) of a sequential equivalent circuit of a power capacitor using integrated capacities.

Claims (1)

A device for determining the parameters of a sequential equivalent capacitor circuit using integrated capacities, characterized in that an active resistance and capacitance calculation unit in which the first and second sampling and storage devices are connected in series to the power capacitor in the places of its connection to the power line through the emergency recorder connected to the emergency recorder, and the first programmer and the second a grammer, the output of which is connected to a computer, and a third programmer is connected to the output of the first fetch-storage device, to which a fourth programmer is connected, the output of which is connected to a computer, and the first, third programmers and programmer of effective values are connected to the output of the second fetch-storage device, to the output of which the second and fourth programmers are connected, while a clock generator is connected to each sampling-storage device.