RU76185U1 - FREQUENCY FILTER - Google Patents

Abstract

The utility model relates to digital signal processing technology, and specifically to frequency filtering, and can be used in digital signal processing systems. The technical result consists in reducing the “leakage” of interference from the delay band into the filter passband by reducing the “spreading of the spectrum” effect when performing the discrete Fourier transform (DFT) operation. To achieve a technical result, a well-known frequency filter, which contains a control unit, a memory matrix, a filter coefficient memory, a data switching unit, an output data generation unit, a tabular search unit for cyclic factors, and one common high-speed arithmetic device, additionally, a weighting unit for the coefficients of the weighting data window . The coefficient memory block of the weighting data window is used to weight the input signal before the DFT operation by the data window and to weight the data filtered out in the frequency domain of the signal after the inverse DFT operation by the return window. 5 ill.

Description

The utility model relates to digital signal processing technology, specifically to a frequency filter, and can be used in digital signal processing systems.

Digital signal processing systems often use filters to filter out interference, extract useful signals, generate signals, etc. Currently, discrete digital signals of a linear stationary system are processed mainly by two types of filters: time convolution and frequency multiplication. Since the signal convolution filter in the time domain uses computational capabilities more efficiently due to the highly efficient circuit variant of the table search, this type of filtering is often used in the development of microcircuits for a filter with a constant characteristic. At the same time, in some cases, a dynamic change in the shape of the filter response to a single pulse is required, so that a filter such as a temporary convolution causes design difficulties and requires additional resources. In these cases, filtering can be performed as follows: the signal from the time domain is converted to the frequency domain by means of a fast Fourier transform (FFT), then the signal in the frequency domain is multiplied by the frequency coefficient of the filter to perform filtering; and then the filtered frequency signal is converted into a signal in the time domain by an inverse FFT (IFFT) and is output.

Known digital filter according to patent RU 2123758 from 12.20.1998, containing a block of discrete Fourier transform (DFT), a multiplication block, a node for increasing spectral resolution, as well as a block of inverse discrete Fourier transform (ODPF).

Since in the aforementioned scheme the signal is directly processed using DFT and DFT, it is possible that the phase jumps in the data signal near the part of the header and the end of the data segment that underwent the Fourier transform after filtering the signal, which negatively affects the filtering and can lead to non-linearity of the filtered phase signal. In addition, during the DFT operation on the input signal, the “spreading of the spectrum” effect may occur, which negatively affects the correct transfer of the analyzed signal from the time domain to the frequency domain. Moreover, the frequency coefficient of the filter in this circuit cannot be dynamically changed externally.

The closest adopted for the prototype is the frequency filter according to patent RU 2308153 C2 of 10.10.2007. The principle of dynamic filtering in the frequency domain according to the prototype is shown in figure 1, and the filtering process includes the following steps:

Step 101: an input signal of a time domain, i.e. input data stream is blocked. More specifically: the input data stream is divided into many data segments with a certain degree of overlap.

Step 102: performing an FFT for each overlapping segment, respectively.

Step 103: each data segment in the frequency domain after the FFT is multiplied by a filter coefficient to perform filtering in the frequency domain, the filter coefficient being stored in a filter coefficient memory 106, which can be updated in real time programmatically or using an arithmetic circuit to dynamically update the characteristics filter in the frequency domain.

Step 104: performing an IFFT for each data segment that has been filtered in the frequency domain, respectively, to restore the data segment in the time domain.

Step 105: performing reverse overlap processing of the data segments in the time domain obtained in step 104 to obtain the output of the data stream in the time domain.

The principle of processing overlap and reverse overlap is shown in figure 2. Suppose that S1 is the input signal in the time domain, the arithmetic length S1 for the FFT is N and the overlap length is L, then, starting from the first sampling point S1, the sample data segment of length N is taken on the data interval (NL), for which data of length L, starting from the end of each data segment, are the same as the first data of length L of the next data segment, i.e. the overlap length is L. Therefore, S1 is successively divided into several segments, and each segment has a length N and an overlap length L. Thus, the overlap processing of the temporary signal S1 is performed.

After overlap processing, the data segments F1 are processed by FFT filtering in the time domain and IFFT, respectively. Then, the thus-processed temporary data segments F1 are output for inverse overlap processing, as described below.

The first L / 2 data and the last L / 2 data of each of the F1 segments that require reverse overlap processing are deleted, and the remaining (N-L) data of each segment is extracted and combined based on the overlap processing order for

obtaining the desired data after filtering in the frequency domain. Since the first L / 2 data and the last L / 2 data of each of the segments are deleted in the inverse overlap processing, data of the extreme parts of the segment are not output, and the filtering effect is significantly improved. With an increased overlap duration L, the filtering parameters become better, but the resources for implementation and the corresponding costs also increase significantly.

A diagram illustrating the implementation of a dynamic frequency filter according to the prototype is presented in figure 3. The prototype frequency filter contains a control unit, a memory matrix, filter coefficient memory, a data switching unit, a table search unit for cyclic factors, an output data generating unit, and at least one common high-speed arithmetic device.

The frequency filter prototype works as follows.

Time-domain data to be filtered in the frequency domain is inputted through an input data bus into a memory matrix; the memory matrix outputs the time-domain-filtered data through the data bus to the output data generating unit, and the finally-filtered time-domain data is output after level adjustment, wherein

the control unit is connected to the memory matrix through the line of the read / write signal and the line of the address signal;

the control unit is connected to the time-domain data clock input from the outside;

the control unit outputs a data combining control signal to an output data generating unit for controlling the strobe and combining the filtered data of the time domain;

the control unit outputs the table search control signal to the table search unit of cyclic factors for controlling the table search synchronized with the Fourier transform and the inverse Fourier transform, and supplies the corresponding cyclic factor to a common high-speed arithmetic device;

a control unit outputs a data switching control signal to a data switching unit for controlling a data input / output strobe of a memory matrix and switching between data for a Fourier transform operation and data for a frequency filtering operation in a general high-speed arithmetic device; moreover, the memory matrix and the data switching unit are connected via a bi-directional bus,

and the data switching unit and the common high-speed arithmetic device are also connected via a bi-directional data bus;

the control unit outputs the state control signal to a common high-speed arithmetic device for controlling the switching between the Fourier transform and the filtering operation in the frequency domain;

the filter coefficient memory receives the control clock from the outside and sends the filter coefficient value to the general high-speed arithmetic device, or receives the coefficient update signal from the outside to update the autosaved filter coefficient.

A disadvantage of the known frequency filter prototype is the ability to "leak" interference from the delay band into the passband of the filter, which occurs due to the presence of the phenomenon of "spreading of the spectrum" when performing a discrete Fourier transform.

The technical result to which the invention is directed is to reduce the “leakage” of interference from the delay band into the passband of the filter by reducing the effect of “spreading of the spectrum” by using weighting windows.

When calculating the signal spectrum using the discrete Fourier transform, the following undesirable effect is possible. When expanding a function in a Fourier series, it is assumed that the function is periodic, with a period equal to the size of the DFT. Moreover, if the values of the initial and final samples of the signal are very different, during periodic repetition, jumps occur at the joints of the segments, due to which the signal spectrum expands. This phenomenon is called "spreading of the spectrum."

Since the signal at the input of the filter is segmented for the Fourier transform, it is convenient to consider it as some part of the corresponding infinite signal visible through the applied window. For example, the segment of the analyzed signal s [i] from N samples can be mathematically written as the product of a rectangular function of unit amplitude

and infinite signal S1 [i]:

s [i] = S1 [i] · rect [i],

where i is the reference number of the analyzed signal.

In this case, the obvious assumption is made that all the signal samples that do not fall into the segment under consideration are equal to zero, regardless of the fact

matter or not. The discrete Fourier transform of the window-weighted segment, expressed through transformations of the signal S1 [i] and the rectangular rect [i] window, is equal to the convolution of these transformations:

G _s (f) = G _S1 (f) * D _N (f),

where G _s (f) is the spectrum of the segment of the analyzed signal,

G _S1 (f) is the spectrum of the analyzed signal,

D _N (f) - discrete function sinc, or Dirichlet kernel, is a DFT of a rectangular function.

The transformation of the analyzed end segment is a distorted version of the transformation of the infinite signal S1 [i]. The minimum width of the spectral peaks of the signal-weighted window segment of the signal is limited by the width determined by the main lobe of the conversion used window, and does not depend on the original signal data. The side lobes of the window transform will change the amplitudes of the neighboring harmonics. Since the DFT is a periodic function, the superposition of side lobes from neighboring spectral harmonics can lead to additional bias.

Leakage to adjacent frequencies through the side lobes of the data window leads not only to the appearance of amplitude errors, but can also mask the presence of weak signals, which is especially important, for example, when using a frequency filter in problems of suppressing narrow-band interference.

To eliminate this effect, weighting functions (data windows) are used, for example, Hamming, Blackman, Henning, Nuttall, etc. (See Marpl.-ml. S.L. Digital Spectral Analysis and its Applications / Transl. From English M. : World, 1990.584 s.). The input samples of the analyzed segment are multiplied by the corresponding window function, which entails a decrease in the signal amplitude at the edges of the segment. Different data windows have different characteristics, such as the bandwidth of the main lobe, the peak level of the side lobes, the decay rate of the side lobes, and should be selected depending on the problem being solved by the frequency filter. The choice of the function of the data window is, above all, a compromise between increasing the bandwidth of the main lobe and the size of the side lobes, leading to "spreading of the spectrum." So, when processing a signal with a small dynamic range of the spectrum, it is desirable to use data windows with a small bandwidth of the main lobe (data windows with high resolution in frequency) and with a satisfactory level of leakage through the side lobes, such as a rectangular window, a Hamming, Hanning window, etc. signal processing with a high dynamic range of the spectrum,

for example, in the presence of powerful narrowband interference, it is desirable to use data windows with a low peak level of the side lobes, but with a wider band of the main lobe, such as the Nuttall, Blackman-Harris, and others. Moreover, it is desirable that the data window used in the DFT could change by software or hardware method depending on the problem being solved by the filter and the characteristics of the input signal.

To achieve a technical result, a memory block is additionally introduced into a known frequency filter containing a control unit, a memory matrix, a filter coefficient memory, a data switching unit, an output data generating unit, a table search unit for cyclic factors, and at least one common high-speed arithmetic device coefficients of the weighting data window, and

time-domain data to be filtered in the frequency domain is inputted through the data bus into the memory matrix; the memory matrix outputs the time-domain-filtered data through the data bus to the output data generating unit, and the finally-filtered time-domain data is output to the frequency filter;

the control unit is connected to the memory matrix through the line of the read / write signal and the line of the address signal;

the control unit is connected to the time-domain data clock input from the outside;

the control unit outputs a data combining control signal to an output data generating unit for controlling the strobe and combining the filtered data of the time domain;

the control unit outputs a table search control signal to a table search unit of cyclic factors for controlling a table search synchronized with the Fourier transform and the inverse Fourier transform, and supplying the corresponding cyclic factor to a common high-speed arithmetic device;

the control unit outputs a data switching control signal to a data switching unit for controlling a data input / output strobe of a memory matrix and switching between data for weighting operations by a data window, data for a Fourier transform and data for a frequency filtering operation in a general high-speed arithmetic device; moreover, the memory matrix and the data switching unit are connected via a bi-directional bus, and the data switching unit and

a common high-speed arithmetic device is also connected via a bi-directional data bus;

the control unit outputs a state control signal to a common high-speed arithmetic device for controlling the switching between the weighing operation of the data window, the Fourier transform and the filtering operation in the frequency domain;

the filter coefficient memory receives the control clock signal from the outside and sends the filter coefficient value to the general high-speed arithmetic device, or receives the coefficient coefficient update signal from the outside to update the autosaving filter coefficient;

the control unit outputs the control clock signal to the filter coefficient memory to bring the memory into a write-protected state when the memory is running, and output from the write-protected state when the memory is waiting for the filter coefficient to be updated;

the coefficient block of the data weighting window coefficients receives the control clock signal from the outside and sends the coefficient of the data weighting window coefficient to the general high-speed arithmetic device, or receives the coefficient update signal from the outside to update the autosaving coefficient of the data window;

the control unit outputs the control clock signal to the coefficient memory block of the data weighting window to bring the memory into a write-protected state when the memory is running, and output from the write-protected state when the memory is waiting for the update of the weighting data window coefficient.

A diagram illustrating the principle of dynamic filtering in the frequency domain using a weighting data window according to a utility model is shown in Fig. 4, and the filtering process includes the following steps:

Step 401: time-domain input, i.e. input data stream is blocked.

Step 402: each data segment in the time domain is multiplied by a weighting data window, the coefficients of which are stored in the coefficient memory 409 of the weighting data window and can be updated in real time.

Step 403: performing an FFT for each overlapping data segment weighted by the window, respectively.

Step 404: each weighted data segment in the frequency domain after the FFT is multiplied by a filter coefficient to perform filtering in the frequency domain, the filter coefficient being stored in a filter coefficient memory 408 that can be updated in real time.

Step 405: IFFT is performed for each weighted data segment that has been filtered in the frequency domain to recover the weighted data segment in the time domain.

Step 406: each weighted data segment obtained in step 405 is multiplied by a reverse weighting data window, the coefficients of which are stored in the coefficient memory 409 of the data weighting window.

Step 407: performing reverse overlap processing of data segments in the time domain obtained in step 406 to obtain an output data stream in the time domain.

Aiming at eliminating the disadvantages of the frequency filtering scheme described in the prototype, characterized by the possibility of "leakage" of interference from the delay band into the passband of the filter, which occurs due to the presence of the phenomenon of "spreading of the spectrum" during the FFT operation, this useful model reduces the "leakage" of interference by introducing the operation of weighing the data segment before performing the FFT and the operation of weighing the return data window after performing filtering in the frequency domain and IFFT. In addition, the utility model provides a memory of the coefficients of the weighting data window, which provides a convenient, fast and dynamic update of the coefficients of the weighting data window, which will have many applications in systems that require adaptive filtering.

The analysis of the prior art made it possible to establish that analogues that are characterized by a combination of features identical to all the features of the claimed technical solution are absent, which indicates the compliance of the claimed device with the patentability condition of "novelty".

The claimed device is illustrated by drawings:

figure 1 is a diagram illustrating the principle of dynamic filtering in the frequency domain according to the prototype;

figure 2 is a diagram illustrating the principle of signal processing with overlap and reverse overlap according to the prototype;

figure 3 is a diagram illustrating the implementation of a dynamic frequency filter according to the prototype;

4 is a diagram illustrating the principle of dynamic filtering in the frequency domain using a weighting data window according to a utility model;

5 is a diagram illustrating an implementation of a dynamic frequency filter using a weighting data window according to a utility model;

6 is a diagram illustrating the structure of a data switching unit.

As shown in FIG. 5, the frequency filter proposed by the present utility model comprises a control unit 501, a memory matrix 502, a filter coefficient memory 503, a data switching unit 504, an output data generating unit 506, a cyclic factor table search unit 507, a weighting coefficient memory unit 508 data windows and at least one common high-speed arithmetic device 505. The control unit 501 outputs seven control signals supplied to a memory matrix 502, a filter coefficient memory 503, a switching unit 504 data, a common high-speed arithmetic device 505, an output data generating unit 506, a cyclic multiplier tabular search unit 507, a coefficient weighting unit 508 of the data weighting window, respectively. In addition, an input control signal is externally sent to control unit 501.

The control signal 12 of the control unit 501 provides read / write and strobe control signals for the memory matrix to control the read and write operations during input, output, overlap, reverse overlap, weighting by the data window, weighting by the data back window, convergent calculation and data filtering in the frequency domain. The control signal 13 is a control signal for generating output data, which controls the strobe and generating the final output in the time domain from various memory blocks. The control signal 14 is a synchronizing control signal of the filter coefficient memory, which controls the filter coefficient memory by sending the filter coefficient to a common high-speed arithmetic device, thereby providing write protection for the filter coefficient memory when the filter coefficient is used, but cancels the write protection in the standby state so that the filter coefficient can be updated. The control signal 15 is a table search control signal that synchronizes the table search with FFT / IFFT operations and controls the table search unit of cyclic factors to derive the corresponding cyclic factor when performing FFT and IFFT. The control signal 16 is a state control signal of a common high-speed arithmetic device that controls the switching between the weighing states of the data window,

convergent computation and filtering in the frequency domain. The control signal 17 is a data switching control signal that controls the data input / output strobe of the memory blocks and the common high-speed arithmetic device for implementing time division multiplexing of the common high-speed arithmetic device in the data operations of the plurality of memory blocks, and also controls the input data switching between operations weighting by a data window, convergent calculation and filtering operation in the frequency domain. The external control signal 18 is a clock signal of external data in the time domain, introduced to synchronize in time the control unit and the input of external data. The control signal 19 is a synchronizing control signal of the coefficient of the data weighting window of the coefficients of the data window, which controls the block of memory coefficients of the weighting window of the data, sending the coefficient of the weighting window of data to a common high-speed arithmetic device, thereby providing write protection for the block of memory coefficients of the weighting window of data when the coefficient a data weighting window is used but will invalidate the write protection in the standby state so that the weighting factor data windows can be updated.

The memory matrix contains at least two independent memory blocks and is used to save overlapping data segments, as well as the intermediate result of the weighting operation of the data window, FFT and filtering operation. The matrix may consist of a matrix of RAM. Each memory block in the RAM matrix is referred to as a RAM group. Each RAM group contains at least two RAMs with a local save function for data operations. At any given time, one of the two RAMs is in the read state, and the other RAM is in the write state. That RAM, which is in the read state, reads the data calculated as a data stream, and sends the data to the arithmetic device, and the calculation result can be stored in the RAM of the same group of RAM in the write state. The filter coefficient memory contains at least one RAM cell. The coefficient memory of the weighting data window contains at least one RAM cell. RAM circuits are known and described, for example, in the book of V.N. Veniaminov, O.N. Lebedev, A.I. Miroshnichenko "Microcircuits and their application" (M .: Radio and communications, 1989, p.146, Fig.5.2 ) In particular, RAM can be implemented on K565 series chips. The tabular search unit for cyclic factors is a read-only memory (ROM) that stores the values of the cyclic factors for performing FFT and IFFT operations. ROM circuit

known and described in the same book on p.156, Fig.5.8. In particular, ROM can be implemented on K555 series chips.

A common high-speed arithmetic unit is a butterfly computing device. Schemes of convergent computing devices are known and described, for example, in the book by E. Ayficher, B. Jervis “Digital Signal Processing: A Practical Approach” (M .: Publishing House “Williams”, 2004. p. 850, fig. 12.40). In particular, such a scheme can be implemented on complex multipliers PDSP16112A (Mitel) and complex drives PDSP16318A (Mitel).

The data switching unit comprises an input data selector, an output data selector, an input melon distributor, an output data distributor, and at least two input / output data switching units; the number of input / output data switching blocks is equal to the number of memory blocks in the memory matrix; input / output data switching blocks uniquely correspond to memory blocks; each input / output data switching unit is connected to a corresponding memory unit via a bi-directional data bus; the output of each input / output switching unit is connected to an input data selector, and the input of each input / output switching unit is connected to an output data distributor; the output of the output data selector is connected to the input data distributor; three outputs of the input data distributor are connected to a common high-speed arithmetic device; three inputs of the output data selector are connected to a common high-speed arithmetic device, and the output of the output data selector is connected to the output data distributor. The output data generating unit is designed to perform the reverse overlap operation and is a data selector. Data selectors, as well as input / output data switching units, are multiplexers. Distributors of input and output data are demultiplexers. Schemes of multiplexers and demultiplexers are known and described, for example, in the book of ON N. Lebedev, A. M. Sidorov “Pulse and digital devices. Digital nodes and their design on microcircuits ”(BAC, 1980, p.55, fig.2.36). In particular, multiplexers and demultiplexers can be implemented on K155 series chips.

The control unit is designed to generate control signals for other filter units and is a distributor. Distributor circuits are known and described, for example, in the book of I. N. Bukreev "Microelectronic circuits of digital devices" (M .: Sov. Radio, 1975, p. 264, Fig. 6.2). In particular, the control unit can be implemented on K561 series chips.

The device depicted in figure 5, operates as follows. The control module 501 sends a control signal 12 to the memory matrix 502. By controlling this signal with the write address of each memory block, the overlap processing shown in FIG. 2 is performed during the input procedure 2 when the input data 1 in the time domain is input into the memory matrix 502 through the input data bus, and each of the data segments in the time domain created during the overlap processing is stored sequentially in each memory block of the memory matrix 502. The memory space required during the entire processing procedure of each data segment is provided by the RAM group in which the data segment is located.

Then, based on the control signals 12, 16, 17, and 19, which are sent to the memory matrix 502, a common high-speed arithmetic device 505, a data switching unit 504, a data weighting coefficient coefficient memory unit 508 using the control unit 501, respectively, each memory unit can be exchanged the data stored in it with the high-speed arithmetic device 505 at high speed through the data switching unit 504, i.e. data in the memory unit is read and entered into the data switching unit 504 via a bi-directional bus 5; switched in the data switching unit 504, data for the weighing operation by the data window is input to the common high-speed arithmetic device 505 via a bi-directional data bus 6; and then, the data multiplication operation is performed with the corresponding coefficient of the data weighting window, output synchronously from the coefficient block 508 of the data weighting window coefficients. After the weighing operation, the data is output to the data switching unit 504 via the bi-directional bus 6 for distribution, and then written to the corresponding memory unit in the memory matrix 502 via the bi-directional bus 5. The above procedure is performed until all the data of the input signal segment is weighted accordingly data window.

Then, based on the control signals 12, 15, 16 and 17 that are sent to the memory matrix 502, the cyclic multiplier tabular search unit 507, the general high-speed arithmetic device 505, the data switching unit 504, using the control unit 501, respectively, each memory unit can be exchanged data stored therein with a high-speed arithmetic device at high speed through the data switching unit 504, i.e. data in the memory unit is read and entered into the data switching unit 504 via a bi-directional bus 5; switched in the data switching unit 504, data for converging calculation is input into the general high-speed arithmetic device 505 through

bidirectional data bus 6; and then converging data computation is performed with the corresponding cyclic factor output synchronously from the table search block 507. After converging, the data is output to the data switching unit 504 via a bi-directional bus 6 for distribution, and then written to the corresponding memory unit in the memory matrix 502 via a bi-directional bus 5. Based on the FFT principle, the above procedure is repeated until all input data is temporary areas will not be transformed into the corresponding data in the frequency domain, thus completing the FFT.

Based on the control signals 12, 14, 16 and 17 that are sent to the memory matrix 502, filter coefficient memory 503, a common high-speed arithmetic device 505, data switching unit 504 using the control unit 501, respectively, data in the frequency domain in the respective memory units and the corresponding filter coefficient in the filter coefficient memory 503 is synchronously sent to a common high-speed arithmetic device 505; they are multiplied in a common high-speed arithmetic device 505 to perform a filtering operation. The result is sent to the corresponding memory block in the memory matrix 502 through the data switching unit 504 and is ready to perform IFFT.

Then, based on the control signals 12, 15, 16 and 17 that are sent to the memory matrix 502, the cyclic multiplier tabular search unit 507, the general high-speed arithmetic device 505, the data switching unit 504 using the control unit 501, respectively, each memory unit can exchange stored therein with data with a common high-speed arithmetic device 505 at high speed through the data switching unit 504, i.e. data in the memory unit is read and entered into the data switching unit 504 via a bi-directional bus 5; data for converging calculations switched in data switching unit 504 is input to a common high-speed arithmetic device 505 via a bi-directional data bus 6; and then a convergent calculation is performed on said data with a corresponding cyclic factor for which the pairing operation was performed and which was deduced synchronously from the table search unit 507. After converging the calculation, the data is output to the data switching unit 504 via the bi-directional bus 6 for distribution, and then written to the corresponding memory unit in the memory matrix 502 via the bi-directional bus 5; the above procedure is repeated until all input data in the frequency domain is transformed into the corresponding data in the time domain, thus completing the IFFT operation.

Then, based on the control signals 12, 16, 17, and 19, which are sent to the memory matrix 502, a common high-speed arithmetic device 505, a data switching unit 504, a coefficient weighting unit data memory unit 508 using the control unit 501, respectively, each memory unit can be exchanged the data stored in it with the high-speed arithmetic device 505 at high speed through the data switching unit 504, i.e. data in the memory unit is read and entered into the data switching unit 504 via a bi-directional bus 5; data for weighting by the reverse data window switched in the data switching unit 504 is input to the high-speed arithmetic device 505 via a bi-directional data bus 6; and then, the operation of multiplying said data with the coefficient of the weighting data window is performed, for which the operation of taking the inverse value was performed and which was synchronously output from the coefficient memory block 508 of the weighting data window. After the weighting operation by the reverse data window, the data is output to the data switching unit 504 via the bi-directional bus 6 for distribution, and then written to the corresponding memory unit in the memory matrix 502 via the bi-directional bus 5. The above procedure is performed until all the data of the weighted segment of the time domain , filtered in the frequency domain, will not be weighted by the corresponding return data window, thereby removing the influence of the weighting data window on the output filtered signal.

Based on the control signals 12 and 13, which are sent to the memory matrix 502 and the output data generating unit 506 using the control unit 501, respectively, the output data 3 for inverse overlap processing is read from the corresponding memory units, and the inverse overlap processing is performed on each of the read segments 2, as shown in FIG. 2, in an output data generating unit 506, the output of which is data 4 in the time domain after filtering in the frequency domain.

The filter coefficient memory 503 of FIG. 5 contains at least one RAM, and the filter coefficient in the memory can be updated externally so that the filter parameters can be dynamically updated, and the update can be provided in software or hardware. The updated filter coefficient 8 is written to the filter coefficient memory when there is no filtering operation, and is ready for use in the next filtering operation.

5, the coefficient block of the weighting data window of FIG. 5 contains at least one RAM, and the coefficient of the data window of the data in memory may be

updated externally so that the parameters of the weighting data window can be dynamically updated, and the update can be provided by software or hardware. The updated coefficient 10 of the data weighting window is written to the memory block of the data weighting window when there is no weighing operation, and is ready for use in the next weighing operation.

The data switching unit 504 of FIG. 5 is described in detail with an example in which the memory matrix 502 connected to the unit 504 contains three independent RAM groups, as shown in FIG. 6.

In Fig.6, each group of RAM has two RAMs: RAM1 and RAM2; at each moment of time, only one RAM is in the read state, while the other is in the write state. The RAM in the read state reads the data for calculation as a data stream and sends the data to the arithmetic device, and the calculation result is stored in another RAM, which is in the write state in the same RAM group.

As shown in FIG. 6, the data switching unit 504 includes an input / output switching unit 601, an input data selector 602, an output data distributor 603, an input data distributor 604, and an output data selector 605. The number of input / output data switching blocks 601 corresponds to the number of memory blocks in the memory matrix, and the switching blocks uniquely correspond to memory groups. In this embodiment, there are three memory groups in the memory matrix 502, so that there are three input / output data switching units 601, each of which uniquely corresponds to three memory groups in the memory matrix 502; the task of the input / output switching unit is to perform data exchange between the RAM group and the selector, as well as to ensure that two RAM from the RAM group are in the correct read / write state. The input selector 602 is a multi-input unit with one output. If there are three input / output data switching units 601 in the data switching unit 504, then the input data selector 602 may be a unit with three inputs and one output. The rest can be inferred logically. For example, consider an input selector 602 with three inputs and one output (“three-one”). Based on the time division multiplexing state of the general arithmetic device, the control signal 17 controls the input data selector 602 to select data from one of the three RAMs transmitted through the three input / output data switching blocks 601 and sends the data to the input data distributor 604. Based on the control signal 17, the input data distributor 604 determines whether the data is intended to be weighted by a data window, a convergent calculation, or to filter in the frequency domain, and then sends the data

to a corresponding device in a common arithmetic device 505. The output data selector 605 is a three-one selection unit; based on the control signal 17, it determines the state of the general arithmetic device 505, and then selects window-weighted data, filtered output data in the frequency domain or output data of convergent calculations as its output data for output data distributor 603. Based on the control signal 17, the output data distributor 603 determines the time division multiplexing state of the general arithmetic device 505, and then distributes the data to the corresponding input / output data switching unit 601 connected to the RAM group in the read and write state. By switching the input / output data using the corresponding input / output data switching unit 601, the data is written to the corresponding RAM, which is in a write state in the corresponding RAM group. In the above procedure, the control signal 17 controls the data switching unit 504 to perform data switching for time division multiplexing and provides a time sequence for switching between operating states.

The above description of the data switching unit relates to an example in which the memory matrix is a RAM matrix containing three groups of RAM. If the RAM matrix contains two or more than three groups of RAM, then the method described above is still applicable, but the corresponding changes must be made to the structure of the data switching unit, taking into account the different requirements for data switching.

When implementing a utility model for the Fourier transform, the Base 2 FFT algorithm is used. However, in practical applications, the Base 4 algorithm and other FFT algorithms, as well as some other suitable settings of the internal structure of the corresponding block of convergent calculations, can be used. Although in the present embodiment, a convergent computing unit is used as a general high-speed arithmetic device, other types of arithmetic devices can also be used. In addition, based on different data transfer rates in the time domain, different resolution requirements in the frequency domain, different degrees of overlap and different rates of convergent calculations, etc., the data length for the FFT and overlap can be changed, may be greater than the general high-speed ones arithmetic devices providing a satisfactory compromise between the cost of implementation and the quality of filtration. The utility model is applicable to various cases of digital signal processing, including signal reception and transmission in communication systems.

Claims (1)

A frequency filter comprising a control unit, a memory matrix, a filter coefficient memory, a data switching unit, an output data generating unit, a table search unit for cyclic factors and at least one common high-speed arithmetic device, while the first input of the memory matrix is the first, information , the input of the frequency filter, and the first output of the memory matrix is connected to the first input of the output data former, the output of which is the information output of the frequency filter, the second output One memory matrix is connected to the first input of the data switching unit, the first output of which is connected to the second input of the memory matrix, while the second output of the data switching unit is connected to the first input of a common high-speed arithmetic device, the output of which is connected to the second input of the data switching unit, the first the second, third, fourth, fifth and sixth outputs of the control unit are connected respectively to the third input of the memory matrix, the second input of the output driver, the first memory input coefficient filter, the output of which is connected to the third input of the common high-speed arithmetic device, the input of the table search unit of cyclic factors, the output of which is connected to the second input of the common high-speed arithmetic device, the fourth input of the general high-speed arithmetic device and the third input of the data switching unit, the second input of the coefficient memory the filter is the second, control, input of the frequency filter, and the input of the control unit is the third, control, input one filter, characterized in that it additionally introduced a memory block of coefficients of a weighting data window, the output of which is connected to the fifth input of a common high-speed arithmetic device, while the seventh output of the control block is connected to the first input of the memory block of the coefficients of the data window, the second input of which is the fourth, control , the input of the frequency filter.