RU74253U1 - KEY SEMICONDUCTOR DEVICE - Google Patents

Abstract

The utility model is aimed at improving the dynamic parameters of the switching device. The specified technical result is achieved in that the key-type semiconductor device includes an electrostatic control thyristor (TEU), a control n-channel MOS transistor and an auxiliary n-channel MOS transistor containing each source, drain and gate, interconnected in such a way that the drain of the TEU is connected to the first power output, the source of the TEU is connected to the drain of the control MOS transistor, the source of which is connected to the second power output, which serves as a common bus, and is connected with the source of the auxiliary An OP transistor, wherein the gate of the MOS transistor is connected to the third control terminal, the gate of the auxiliary MOS transistor is connected to the gate of the TEU, and a diode is inserted into the device, the anode of which is connected to the drain of the auxiliary MOS transistor, while the cathode of this diode is connected to shutter TEU. 4 ill.

Description

The proposal relates to the field of semiconductor instrumentation, in particular, to the design of powerful key semiconductor devices and power integrated circuits that combine the advantages of field control and a bipolar current transfer mechanism (the English name is MOS-Controlled Power Switches) and can be used in circuits and devices of power electronics.

Semiconductor switches are known in which a high-voltage thyristor with electrostatic control (TEU) is switched by a low-voltage MOS transistor connected in series with it (cascade key circuit) (see US5323028 A, June 21, 1994).

The disadvantage of these devices is the relatively slow inclusion due to the incomplete discharge of the gate-source capacitance of the TEU through an open MOS transistor and a Zener diode connected between the gate of the TEU and the source of the MOS transistor.

The closest in technical essence to the claimed solution is a semiconductor key device, including a thyristor with electrostatic control (TEU), a control n-channel MOS transistor and an additional n-channel MOS transistor containing each source, drain and gate, interconnected by such so that the drain of the TEU is connected to the first power output, the source of the TEU is connected to the drain of the control MOS transistor, the source of which is connected to the second power output, which serves as a common bus, and is connected to the source MOS transistor, while the gate of the control MOS transistor is connected to the third control terminal (see RU 2268545 C2, 01.20.2006).

In the specified device, the drain of the additional MOS transistor is connected to the gate of the TEU, and the gate of the additional MOS transistor is connected to the drain of the control MOS transistor. In this case, the antiphase switching of the control and additional MOS transistors occurs. The gate-to-source capacitance of a TEU in the transition process of turning on this device is discharged through an open MOSFET and an internal diode in the structure of an additional MOSFET. In this case, the discharge of the indicated capacitance is also incomplete, and the residual negative gate-source voltage of the TEU is equal to the direct voltage on the internal diode plus the voltage drop on the open control MOS transistor. In turn, this leads to a slower switching on of the semiconductor device, and the front of the rise in the output current at the level of tens of amperes is several hundred nanoseconds. Problem

becomes more significant with an increase in the voltage class of a semiconductor device, since this significantly increases the resistivity of the base layer of the thyristor with electrostatic control. For quick switching on, not only a discharge of the gate-source capacitance of a TEU is required, but also an additional boost charge in its input circuit for effective initial modulation of the indicated base layer. For this reason, in the known device it is proposed to introduce a boost chain, and the capacitor of this chain is connected between the gates of the TEU and the control MOS transistor. However, the effectiveness of this solution is significantly reduced due to the final shutdown speed of the additional MOS transistor, which shunts the input circuit of the TEU just at the stage of charging the boost capacitor. Another disadvantage of this solution is that the boost capacitor connected in this way turns out to be practically parallel to the input circuit of the key, which significantly increases its input capacity, leads to additional overload of the control pulse shaper, and worsens the switching dynamics.

The technical result of the proposed device is to improve the dynamic switching parameters of the semiconductor device:

1. The input gate-source capacitance of the auxiliary MOS transistor, charged during the transition process of turning off the device, is discharged into the input circuit of the TEU in the transition process of turning on the device, ensuring its quick inclusion and the initial modulation of the base layer of the TEU by connecting the gate of the additional MOS transistor to the gate TEU.

2. The input gate-source capacitance of the auxiliary MOS transistor does not increase the input capacitance of the device itself.

3. The necessary boost charge for quickly turning on the device and modulating the base layer of the TEU is accumulated in the input gate-source capacitance of the auxiliary MOS transistor in the transient process of turning off the device, due to the diode introduced into the device, the anode of which is connected to the drain of the auxiliary MOS transistor, the cathode of the diode is connected to the gate of the TEU.

4. In the process of turning off the device, the auxiliary MOS transistor is in saturation mode, while the minimum dynamic overload of the control MOS transistor is ensured by voltage due to the fixation of the voltage at the required level by the diode introduced into the device.

5. The device circuit does not use an additional element-boosting capacitor, because its role is played by the input gate-source capacitance of the auxiliary MOS transistor.

The technical result is achieved in that in a power semiconductor key device including a thyristor with electrostatic control (TEU), a control n-channel MOS transistor and an auxiliary n-channel MOS transistor containing each source, drain and gate, interconnected in such a way that the drain of the TEU is connected to the first power output, the source of the TEU is connected to the drain of the control MOS transistor, the source of which is connected to the second power output, which serves as a common bus, and is connected with the source of the auxiliary MOSFET ranzistora, wherein the shutter control MOS transistor is connected to the third control terminal, the gate of the auxiliary MOSFET transistor connected to the gate TEU, a device introduced diode, the anode of which is connected to the drain of the auxiliary MOS transistor, the cathode of said diode connected to the gate TEU.

Figure 1 presents a semiconductor device of a key type.

Figure 2 presents the oscillogram of the device switching current (gate-source voltage of the device and the output current of the drain of the device).

Figure 3 - waveform switching device voltage (voltage drain-source device and voltage drain-source control MOS transistor).

Figure 4 is an oscillogram of the control voltage (gate-source voltage of the device and gate-source voltage of the auxiliary MOS transistor).

The semiconductor device comprises a high-voltage thyristor 1 with electrostatic control (TEU), a low-voltage control MOS transistor 2 connected in series with it, an auxiliary low-voltage MOS transistor 3, while the TEU contains a source region 4, a drain region 5, and a gate 6, a control MOS transistor contains a source region 7, a drain region 8 and a gate 9, an additional MOS transistor contains a source region 10, a drain region 11 and a gate 12. Between the source 10 and drain 11 of the auxiliary MOS transistor 3, a dotted line shows it Cored oil wheeling diode 13.

TEU, control and additional MOS transistors are interconnected as follows. The drain 5 of the TEU is connected to the first power terminal "C" (the drain of the device), the source 4 of the TEU is connected to the drain 8 of the control MOSFET 2, the source 7 of which is connected to the second power terminal "I" (the source of the device), which serves as a common bus, and connected to the source 10 of the auxiliary MOS transistor 3, while the gate 9 of the control MOS transistor 2 is connected to the third control terminal "3" (device shutter).

The gate 12 of the auxiliary MOS transistor 3 is connected to the gate 6 of the TEU, a diode 14 is introduced into the device, the anode 15 of which is connected to the drain 11

auxiliary MOS transistor 3, while the cathode 16 of the specified diode 14 is connected to the gate 6 of the TEU.

The inventive device operates as follows.

The device is an asymmetric key and provides current transmission and power regulation in the load with a positive potential at the first power terminal "C" relative to the second power terminal "And", that is, provided

where U _SI is the output voltage of the device between the terminals "C" and "And", V.

The locked state of the key is realized when the control signal is zero at the third control terminal "Z" connected to the gate 9 of the control MOS transistor.

Let us designate the external voltage applied to the claimed key device and the load connected in series with it, the symbol E. When the key device is closed:

where U _{DS TEU} - voltage drain-source TEU, V.

U _{DS MOS1} - drain-source voltage of the control MOS transistor, V. Denote the blocking coefficient of TEU by μ. Then, the drain-source voltage of the MOSFET can be written as:

where U _{GS TEU} - voltage gate-source TEU, V.

U _{GS MOS2} - gate-source voltage of an additional MOS transistor, V.

The voltage U _{GS MOS2 is} installed in the input circuit of the additional MOS transistor when the device is turned off and is equal to the sum of the voltage drops: reverse on the diode 14 and the voltage at the drain-source resistance of the open auxiliary MOS transistor 3, when a pulse flows through the diode 14 and the additional MOS transistor reverse shutter current 6 TEU. In this way:

where U _KA is the reverse voltage to the diode 14, V.

I _З - gate current of TEU, A.

R _{DS (on) 2} is the drain-source resistance of the open additional MOS transistor, Ohm.

The diode 14, introduced into the device, is a semiconductor voltage limiter (Suppressor), which, when the reverse current of the TEU gate flows, is located in the reversible breakdown region, which is similar in principle to the Zener diode or Zener diode. A distinctive feature of such diodes is the ability to absorb relatively high power at the Zener breakdown stage (several thousand watts), high speed (units ns), low differential resistance (units mOhm), and reliable voltage fixing.

Denote the voltage recorded by the diode 14, as U ₀ . The auxiliary MOS transistor used in the TEU input circuit is low-voltage, and its resistance K _{DS (on) 2 is} relatively small (units of mOhm). At load currents equal to tens of amperes, the voltage I _З · R _{DS (оn) 2} is not more than 0.1 V and can be neglected in comparison with U ₀ (units V). In this way:

Therefore, equation (3) can be rewritten as:

In existing technologies for the implementation of the structure of TEU there are no physical and technological reasons that impede the achievement of almost any necessary value of the blocking coefficient μ. This allows, according to equation (6), to apply also a low-voltage control MOS transistor with a low drain-source resistance in the open state - of the order of a few milliom.

T.O. in the locked state of the device, almost all the external voltage E according to equation (2) is applied to the high-voltage TEU, the auxiliary MOS transistor is open (U _{0 is} higher than its unlock threshold), and the voltage on the closed control MOS transistor is relatively small.

The device is turned on by applying a positive voltage pulse to the third control terminal "Z". In this case, the input capacitance of the control MOS transistor is charged, which ensures its inclusion.

The capacity of the control pn junction gate 6 - source 4 of the TEU is charged before switching on to a negative voltage, determined in accordance with equation (3):

To achieve the required speed on the device you need to quickly discharge this capacity. When the control MOS transistor is turned on, the gate-source capacitance of the TEU will be forcedly discharged using the gate-source capacitance of the auxiliary MOS transistor. As noted above, it is also necessary to ensure the supply of an additional charge to the input circuit of the high-voltage TEU after the discharge of the gate-source capacity of the TEU when the control p-n junction of the TEU is displaced in the forward direction.

Denote the value of the additional charge as Q _D , then it is necessary to require that the charge accumulated in the input capacitance of the gate 12 - source 10 of the auxiliary MOS transistor satisfy the condition:

where C _{ZI MOS2} is the gate-source capacitance of the auxiliary MOS transistor, nF.

With _{ZI TEU} - gate-source capacity of TEU, nF.

Inequality (8) allows for a given TEU to select the appropriate parameters of the auxiliary MOS transistor 3 and diode 14.

At the end of the switching on process, the gate-source capacitance of the auxiliary MOS transistor is discharged, this transistor is locked, and the forward voltage drops on the device:

where U _{(Оn) ТЭУ} - voltage drop on an open ТЭУ, V.

R _{DS (on) 1} is the drain-source resistance of the open MOSFET, in ohms.

I _C - current power device in the open state, A.

The current I _C is determined by the parameters of the load and the external circuit. The device is turned off by switching the voltage at the control terminal "3" to zero. In this case, the input capacitance of the control MOS transistor is discharged, after which this transistor is locked. The drain potential 8 of the control MOS transistor begins to increase, while the negative voltage in the input gate-source circuit of the TEC increases (at the initial instant of time, the gate potential of the TEC is determined by the almost zero gate-source voltage of the auxiliary MOS transistor). In this case, a space charge region is formed in the base layer of the TEU, and the voltage on the device increases.

In this case, a reverse current pulse appears in the TEU gate circuit in amplitude almost equal to the load current I _C. This current pulse begins to charge the gate-source capacitance of the auxiliary MOS transistor, and when the voltage in the input circuit of the specified MOS transistor increases above the threshold, the latter is unlocked. However, the drain current of the auxiliary MOSFET appears only after switching on the limiting diode 14, when the voltage U _{GS MOS2} becomes equal to the value of U ₀ . Since the voltage at the gate-source capacitance of the auxiliary MOS transistor is further fixed by the diode 14 at the level of U ₀ , the energy stored in this capacitance is . The auxiliary MOS transistor is in a saturated state (since the voltage U ₀ exceeds its threshold switching voltage). Therefore, another part of the energy from the flow of the reverse current gate pulse of the TEU, equal to the product of the charge of the current passing through the diode 14 by the voltage U ₀ , is almost completely absorbed by the diode 14. So the choice of the diode 14 must be carried out both by the required value of U ₀ , and taking into account its ability to absorb the energy of the reverse current pulse remaining after the charge of the capacitance C _{MOS MOP2} .

The proposed key device also maintains its operation in the mode of short-term current overloads. When the load current increases above a certain value determined by the output characteristic of the control MOS transistor, the latter switches from the saturation mode with a small resistance R _{DS (on) 1} to the active region of operation, which means an increase in its output voltage, drain 8 is source 7. This is in its queue leads to

increase the negative voltage at the control pn junction of the TEU and then similar to the processes when locking the device. The difference is that part of the overload current begins to flow in the TEU gate circuit, the value of which is determined by the current transfer coefficient of the internal pnp transistor in the structure of the TEU. Another part of the overload current is limited by the maximum current of the control MOS transistor, the value of which in turn depends on the magnitude of the control voltage and the slope of the transistor.

When the device is first turned on (start-up mode), the gate-source capacitance of the auxiliary MOS transistor is not charged and has a zero voltage. In this case, the discharge of the gate-source capacitance of the TEU passes along the circuit: open control MOS transistor 2 — internal reverse diode 13 of the auxiliary MOS transistor 3 — diode 14. Thus Voltage limiting diode 14 must be selected as Unidirectional.

An example of a specific implementation. The device is a hybrid power circuit, made in accordance with Figure 1, in which all the elements in the form of separate crystals (TEU, control and auxiliary MOS transistors, a diode) are soldered to a common insulating substrate made of alumina ceramic coated with copper metallization. In this case, a high-voltage TEU 1 with a maximum allowable drain-source voltage of 1200 V, a blocking coefficient of up to 100 units, and a maximum allowable current of 50 A was used. The size of the TEU crystal is 7 × 7 mm. As transistors 2 and 3, crystals of n-channel MOS transistors with a maximum allowable drain-source voltage of 55 V, a threshold voltage of 2.1 ... 4.0 V, a maximum allowable drain current of 100 A, and drain-source resistance in open state not more than 3.0 mOhm, input gate-source capacitance of 20 nF. The diode used in the device has the following parameters: pulse dissipated power of 1500 W, maximum pulse current of 100 A, limiting voltage of 7 V, differential resistance in the limiting region of 4.3 mOhm, leakage current of not more than 50 μA. All electrical connections of the elements are made by ultrasonic welding using an aluminum wire with a diameter of 300 microns attached to the contact pads of the corresponding elements.

The inventive device in this design provides current switching up to 50 A at a voltage of 1200 V. The voltage drop across an open device at a current of 50 A is 1.5 V. The rise time of the current is 40 ns (up to 20 A), the current fall time is 50 ns, the duration residual current 1000 ... 1500 ns.

This device can be used in electronics, power control and regulation equipment, converting technology, secondary power sources.

Figure 2, 3, 4 shows the waveforms of the prototypes of this key device, taken using a Tektronix digital oscilloscope company TDS 3054 series.

The operating mode of the device in all cases:

- inductive load of 100 μH in continuous current mode, shunted by the counter diode HFA08TB60 of IR company;

- output circuit: E = 300 V, rated continuous load current 20 A;

- input circuit: Er = 15 V, the switching pulse of the control pulses is <15 ns, the output resistance of the generator circuit is not more than 0.2 Ohms, the resistance connected in series to terminal “Z” is 2.2 Ohms.

Figure 2 shows the current switching device:

- channel 1: gate-source voltage of the device;

- channel 3: drain current of the device.

Vertical scale (amplitude scale):

- channel 1:10 V per division;

- channel 3: 5 A per division.

Horizontal Scale (Sweep Scale):

- 200 ns per division.

The arrow on the left with the number of the corresponding channel shows the level of zero vertical values for this channel.

Figure 3 shows the switching device voltage:

- channel 1: voltage drain-source control MOS transistor;

- channel 2: drain-source voltage of the device.

Vertical Scale:

- channel 1:20 V per division;

- channel 2: 100 V per division.

Horizontal Scale:

- 200 ns per division.

Figure 4 shows the control voltage:

- channel 1: gate-source voltage of the control MOS transistor;

- channel 2: gate-source voltage of the auxiliary MOS transistor.

Vertical Scale:

- channel 1:10 V per division;

- channel 2: 5 V per division.

Horizontal Scale:

- 200 ns per division.

Claims (1)

A semiconductor device of a key type, characterized in that it includes a thyristor with electrostatic control (TEU), a control n-channel MOS transistor, and an auxiliary n-channel MOS transistor containing each source, drain, and gate, interconnected so that the drain The TEU is connected to the first power terminal, the source of the TEU is connected to the drain of the control MOS transistor, the source of which is connected to the second power terminal serving as a common bus, and is connected to the source of the auxiliary MOS transistor, while the gate of the MOS transistor is connected to the third control terminal, the gate of the auxiliary MOS transistor is connected to the gate of the TEU, and a diode is introduced into the device, the anode of which is connected to the drain of the auxiliary MOS transistor, while the cathode of the indicated diode is connected to the gate of the TEU.