RU74534U1 - KEY SEMICONDUCTOR DEVICE - Google Patents

Abstract

The utility model is aimed at improving the dynamic parameters of the switching device. A key type semiconductor device includes an electrostatic controlled thyristor (TEU), an n-channel MOS transistor, and an auxiliary n-channel MOS transistor, each source, drain, and gate connected together so that the drain of the TEU is connected to the first power conclusion, the source of the TEU is connected to the drain of the control MOS transistor, the source of which is connected to the second power output, which serves as a common bus, and is connected with the source of the auxiliary MOS transistor, while the gate of the control MOS trans the resistor is connected to the third control terminal, and the gate of the auxiliary MOS transistor is connected to the drain of the control MOS transistor, and a boost circuit consisting of a parallel connection of the capacitor and the diode is introduced into the device, the first common point of connection of one capacitor plate and the anode of the diode is connected to the drain of the auxiliary MOS transistor, and the second common point of connection of the second plate of the capacitor and the cathode of the diode is connected to the gate of the TEU. 3 ill.

Description

The invention relates to the field of semiconductor instrumentation, in particular, to the design of powerful key semiconductor devices and power integrated circuits that combine the advantages of field control and a bipolar current transfer mechanism (English name MOS-Controlled Power Switches) and can be used in circuits and devices of power electronics.

Semiconductor switches are known in which a high-voltage thyristor with electrostatic control (TEU) is switched by a low-voltage MOS transistor connected in series with it (cascode key circuit) (see US 5323028 A, June 21, 1994).

The disadvantage of these devices is the relatively slow inclusion due to the incomplete discharge of the gate-source capacitance of the TEU through an open MOS transistor and a Zener diode connected between the gate of the TEU and the source of the MOS transistor.

The closest in technical essence to the claimed solution is a semiconductor key device, including a thyristor with electrostatic control (TEU), a control n-channel MOS transistor and an additional n-channel MOS transistor containing each source, drain and gate, interconnected by such so that the drain of the TEU is connected to the first power output, the source of the TEU is connected to the drain of the control MOS transistor, the source of which is connected to the second power output, which serves as a common bus, and is connected to the source MOS transistor, while the gate of the MOS transistor is connected to the third control terminal, and the gate of the additional MOS transistor is connected to the drain of the control MOS transistor (see RU 2268545 C2, 01.20.2006).

In the specified device, the drain of the additional MOS transistor is connected to the gate of the TEU, and the gate of the additional MOS transistor is connected to the drain of the control MOS transistor. In this case, the antiphase switching of the control and additional MOS transistors occurs. The gate-to-source capacitance of a TEU in the transition process of turning on this device is discharged through an open MOSFET and an internal diode in the structure of an additional MOSFET. In this case, the discharge of the indicated capacitance is also incomplete, and the residual negative gate-source voltage of the TEU is equal to the direct voltage on the internal diode plus the voltage drop on the open control MOS transistor. In turn, this leads to a slower inclusion of the semiconductor device, and the front

the increase in the output current at the level of tens of amperes is several hundred nanoseconds. The problem becomes more significant with an increase in the voltage class of a semiconductor device, since this significantly increases the resistivity of the base layer of the thyristor with electrostatic control. For quick switching on, not only a discharge of the gate-source capacitance of a TEU is required, but also an additional boost charge in its input circuit for effective initial modulation of the indicated base layer. For this reason, it is proposed in the known device to introduce a boost chain consisting of a series connection of a capacitor and a diode, the capacitor of this chain being connected between the gates of the TEU and the control MOS transistor. However, the effectiveness of this solution is significantly reduced due to the final shutdown speed of the additional MOS transistor, which shunts the input circuit of the TEU just at the stage of charging the boost capacitor. Another disadvantage of this solution is that the boost capacitor connected in this way turns out to be practically parallel to the input circuit of the key, which significantly increases its input capacity, leads to additional overload of the control pulse shaper, and worsens the switching dynamics.

The technical result of the invention is to improve the dynamic switching parameters of a semiconductor device.

1. The capacitor of the boost chain charged in the transition process of turning off the device, in the transition process of turning on the device, is discharged into the input circuit of the TEU, ensuring its quick inclusion and initial modulation of the base layer of the TEU by connecting this capacitor between the gate of the TEU and the drain of the auxiliary MOS transistor.

2. The necessary charge to quickly turn on the device and modulate the base layer of TEU is accumulated in the capacitor of the boost chain during the transient turn-off of the device at a fixed voltage on the capacitor due to the diode connected in parallel to this capacitor, the anode of which is connected to the drain of the auxiliary MOS transistor, and the cathode of the diode is connected with shutter TEU. This does not require additional energy from the control circuit of the device.

3. In the transition process of turning off the device, the auxiliary MOS transistor is in saturation mode, while the minimum dynamic overload of the control MOS transistor is ensured by voltage due to fixing at the required level of this voltage by the diode of the boost chain introduced into the device.

4. The capacitor used in the device does not increase the input capacitance of the device.

The technical result is achieved in that in a power semiconductor key device including a thyristor with electrostatic control (TEU), a control n-channel MOS transistor and an auxiliary n-channel MOS transistor containing each source, drain and gate, interconnected in such a way that the drain of the TEU is connected to the first power output, the source of the TEU is connected to the drain of the control MOS transistor, the source of which is connected to the second power output, which serves as a common bus, and is connected with the source of the auxiliary MOSFET a transistor, while the gate of the MOS transistor is connected to the third control terminal, and the gate of the auxiliary MOS transistor is connected to the drain of the control MOS transistor, a boost circuit consisting of a parallel connection of a capacitor and a diode is introduced into the device, the first common point connecting one plate the capacitor and the anode of the diode is connected to the drain of the auxiliary MOS transistor, and the second common point of connection of the second plate of the capacitor and the cathode of the diode is connected to the gate of the TEU.

In figure 1. a key type semiconductor device is presented.

Figure 2. The oscillogram of switching the device by current (gate-source voltage of the device and the output current of the drain of the device) is presented.

In figure 3. - an oscillogram of the device switching by voltage (the gate-source voltage of the device and the drain-source voltage of the control MOS transistor).

Power semiconductor key device contains a high-voltage thyristor 1 with electrostatic control (TEU), a low-voltage control MOS transistor 2 connected in series with it, an auxiliary low-voltage MOS transistor 3, while the TEU contains a source region 4, a drain region 5 and a gate 6, the control MOS transistor contains a region source 7, drain region 8 and gate 9, the auxiliary MOS transistor comprises a source region 10, drain region 11 and gate 12. Between the source 10 and drain 11 of the auxiliary MOS transistor 3, its internal reverse diode 13 is shown by dashed lines.

The TEU, the control and auxiliary MOS transistors are interconnected as follows: drain 5 of the TEU is connected to the first power terminal "C" (drain of the device), the source 4 of the TEU is connected to the drain 8 of the control MOS transistor 2, the source 7 of which is connected to the second power the output "And" (the source of the device), which serves as a common bus, and is connected to the source 10 of the auxiliary MOS transistor 3, while the gate 9 of the control MOS transistor 2 is connected to the third control terminal "3" (the shutter of the device), and the gate 12 of the auxiliary MOS

the transistor 3 is connected to the drain 8 of the control MOS transistor, a boost chain is introduced into the device, consisting of a parallel connection of the capacitor 17 and the diode 14, and the first common point of connection of one plate 18 of the capacitor 17 and the anode 15 of the diode 14 is connected to the drain 11 of the auxiliary MOS transistor 3, and the second common point of connection of the second plate 19 of the capacitor 17 and the cathode 16 of the diode 14 is connected to the gate 6 of the TEU.

The inventive key device operates as follows. The device is an asymmetric key and provides the flow of current and power regulation in the load with a positive potential at the first power output "C" relative to the second power output "I", that is, provided

where U _SI is the output voltage of the device between the terminals "C" and "I", V.

The locked state of the key is realized when the control signal is zero at the third control terminal "Z" connected to the gate 9 of the control MOS transistor. Moreover, the latter is in the closed state and the current through it, and, accordingly, through the TEU 1 practically does not flow.

We denote the external voltage applied to the claimed key device and the load connected in series with it, the symbol E. In the absence of current in this circuit (the key device is locked):

where U _{DS TEU} - voltage drain-source TEU, V.

U _{DS MOS1} - voltage drain-source control MOS transistor, V.

The ratio of the drain-source voltage of a TEU to the gate-source voltage of a TEU at a given leakage current through a closed TEU is called the blocking coefficient. Denote it by the symbol μ.

Then, the drain-source voltage of the MOSFET can be written as:

where U _{DS MOS2} - voltage drain-source auxiliary MOS transistor, V.

U _C - voltage across the capacitor 17, V.

U _{GS TEU} - voltage gate-source TEU, V.

If the voltage U _{DS MOS1} becomes greater than the threshold voltage of the gate U _{02 of the} auxiliary MOS transistor (which is practically implemented in the device under consideration), the latter is in the open state. Because the absence of current through the TEU also means the absence of current in the circuit of its gate (up to a leakage current of a fraction of mA), we can put:

where R _{DS (on) 2} is the drain-source resistance of the open auxiliary MOS transistor, Ohm.

I _D2 is the drain current of the auxiliary MOS transistor, A. Therefore, formula (3), taking into account (4), can be rewritten:

which allows us to formulate the requirements for the maximum permissible output voltage of the control MOS transistor.

In existing technologies for the implementation of the structure of TEU there are no physical and technological reasons that impede the achievement of almost any necessary value of the blocking coefficient μ. The voltage U _{C is} limited by the fixing voltage of the diode 14, which is not more than 10 V. in the device, it is possible to use a low-voltage control MOS transistor with a small open resistance R _{DS (on) 1} .

Since in this device the voltage U _{DS MOS1} is equal to the input gate-source voltage of the auxiliary MOS transistor, the voltage class of the control MOS transistor will not be higher than the voltage limit for the input circuit of insulated gate transistors, i.e. no more than 20-30 V. With this voltage class, R _{DS (on) 1} for modern technologies of power low-voltage MOS transistors is one milliom.

T.O. in the locked state of the device, almost all of the external voltage E is applied to the TEU, the auxiliary MOS transistor is open, and the voltage on the control MOS transistor is relatively small, however, it is higher than the threshold voltage for unlocking the auxiliary MOS transistor.

The inclusion of the device is achieved by applying a positive voltage pulse to the third control terminal "Z". In this case, the input capacitance of the control MOS transistor is charged, which leads to its inclusion.

The capacity of the control pn junction gate 6 - source 4 of the TEU is charged before switching on to a negative voltage, determined in accordance with equation (3):

To obtain the required speed on the device must quickly discharge this capacity. When the control MOS transistor is turned on, the auxiliary MOS transistor is locked, however, the gate-source capacitance of the TEU is forcedly discharged using a capacitor 17 along the circuit: the included control MOS transistor 2 is the inverse diode 13 of the auxiliary MOS transistor 3 — a capacitor 17. Used in the boost chain the diode is a semiconductor voltage limiter (suppressor) and has a current-voltage characteristic,

a similar characteristic of the zener diode. However, this diode allows you to absorb significant energy (dissipated pulsed power up to several thousand watts), has a short response time (a few nanoseconds), a small differential resistance in the voltage stabilization section (a few milliohms) and reliably fixes the voltage.

It is also necessary to provide an additional charge to the input circuit of the high-voltage TEU after a full discharge of the gate-source capacity of the TEU, when the control pn junction of the TEU is shifted in the forward direction.

If we denote the value of the additional charge Q _d , then it should be required that the charge stored by the capacitor 17 in the transient shutdown of the device satisfy the condition:

where C is the capacitance of the capacitor 17, nF.

With _{ZI TEU} - gate-source capacity of TEU, nF.

U ₀ - fixing voltage of the diode 14, Century

Inequality 7 allows for the given parameters of the TEU to select the appropriate parameters of the limiting diode 14 and the capacitor 17.

At the end of the switching on process, the capacitor 17 is completely discharged, and the forward voltage is established on the device:

where U _{(Оn) ТЭУ} - voltage drop on an open ТЭУ, V.

R _{DS (on) 1} - resistance drain-source control MOS transistor, Ohm.

I _C - current power device in the open state, A.

The current I _C is determined by the parameters of the load and the external circuit.

The device is turned off by switching the voltage at the control terminal "3" to zero. In this case, the input capacitance of the control MOS transistor is discharged, after which this transistor is locked. The drain potential 8 of the control MOS transistor begins to increase, while the input voltage of the gate 12 — source 10 of the auxiliary MOS transistor increases. When this voltage reaches the unlock threshold U _{02 of the} auxiliary MOS transistor, the latter is unlocked. At the same time, a negative voltage is applied to the gate-source circuit of the TEU, which is practically equal to the voltage drop at the MOS transistor (at the initial time, the voltage across the capacitor 17 is zero).

In this case, a powerful reverse current pulse in amplitude almost equal to the load current I _C appears in the TEU gate circuit. This current pulse begins to charge the capacitor 17. Since the voltage U _{C is} then fixed by the diode 14 at the level of U ₀ , the energy stored in this capacitor 17 is . The other part of the energy from leaking

the reverse gate current of the TEU is absorbed by the diode 14, since the auxiliary MOS transistor is in a saturated state. T.O. the choice of the diode 14 must be carried out both according to the required value of U ₀ , and taking into account its ability to absorb the energy of the reverse current pulse remaining after the charge of the capacitor C, equal to the product of the charge of the gate current of the TEU passing through the diode 14 by the voltage U ₀ .

The proposed key device remains operational also in the mode of short-term current overloads. When the load current increases above a certain value determined by the output characteristic of the control MOS transistor, the latter switches from the saturation mode with a small resistance R _{DS (on) 1} to the active region of operation, which means the growth of its output voltage, drain 8 - source 7, while increasing input voltage gate 12 is the source 10 of the auxiliary MOS transistor. When this voltage reaches the unlock threshold U _{02 of the} auxiliary MOS transistor, the latter is unlocked. In this case, a negative voltage is applied to the gate-source circuit of the TEU and then similarly to the processes when locking the device. The difference is that part of the overload current begins to flow in the TEU gate circuit, the value of which is determined by the current transfer coefficient of the internal pnp transistor in the structure of the TEU. Another part of the overload current is limited by the maximum current of the control MOS transistor, the value of which in turn depends on the magnitude of the control voltage and the slope of the transistor.

When the device is first started up (start-up mode), the boost chain capacitor has zero voltage. In this case, the gate capacitance 6 - source 4 of the TEU is discharged along the circuit: open control MOS transistor 2 - internal reverse diode 13 of the auxiliary MOS transistor 3 - diode 14. Thus voltage limiting diode 14 must be selected unidirectional.

An example of a specific implementation. The device is a hybrid power circuit, made in accordance with Figure 1, in which all the elements in the form of individual crystals (TEU, control and auxiliary MOS transistors, a diode and a chip capacitor) are soldered to a common insulating substrate made of alumina ceramic, plated with copper plating. In this case, a high-voltage TEU 1 with a maximum allowable drain-source voltage of 1200 V, a blocking coefficient of up to 100 units, and a maximum allowable current of 50 A was used. The size of the TEU crystal is 7 × 7 mm. As transistors 2 and 3, crystals of n-channel MOS transistors with a maximum allowable drain-source voltage of 30 V, a threshold voltage of 2.1 ... 4.0 V, a maximum allowable drain current of 80 A, and drain-source resistance in open state not more than 4.5 mOhm, input

gate-source capacitance 5 nF. The diode used in the device has the following parameters: pulse dissipated power of 1500 W, maximum pulse current of 100 A, voltage limitation of 7 V, differential resistance in the region of limitation of 4.3 mOhm. The capacitor has a capacitance of 22 nF at a maximum permissible voltage of 25 V. All electrical connections of the elements are made by ultrasonic welding using an aluminum wire with a diameter of 300 μm connected to the contact pads of the corresponding elements.

The inventive device in this design provides current switching up to 50 A at a voltage of 1200 V. The voltage drop across an open device at a current of 50 A is 1.5 V. The rise time of the current is 80 ns (up to 20 A), the current fall time is 50 ns, duration residual current 1000 ... 1500 ns.

This device can be used in electronics, power control and regulation equipment, converting technology, secondary power sources.

Figure 2, 3 shows the waveforms of the prototypes of this key device, taken using a Tektronix digital oscilloscope company TDS 3054 series.

The operating mode of the device in all cases:

- inductive load of 100 μH in continuous current mode, shunted by the counter diode HFA08TB60 of IR company;

- output circuit: E = 300 V, rated continuous load current 20 A;

- input circuit: Eg = 15 V, the switching front of the control pulses <15 is not, the output resistance of the generator circuit is not more than 0.2 Ohms, the resistance connected in series to the output "3" 2.2 Ohms.

Figure 2 shows the current switching device:

- channel 1: gate-source voltage of the device;

- channel 3: drain current of the device.

Vertical scale (amplitude scale):

- channel 1: 10 V per division;

- channel 3: 5 A per division.

Horizontal Scale (Sweep Scale):

- 200 ns per division.

The arrow on the left with the number of the corresponding channel shows the level of zero vertical values for this channel.

Figure 3 shows the switching device voltage:

- channel 1: gate-source voltage of the device.

- channel 2: voltage drain-source control MOS transistor;

Vertical Scale:

- channel 1: 10 V per division;

- channel 2: 5 V per division.

Horizontal Scale: - 200 ns per division.

Claims (1)

A semiconductor device of a key type, characterized in that it includes a thyristor with electrostatic control (TEU), a control n-channel MOS transistor, and an auxiliary n-channel MOS transistor containing each source, drain, and gate, interconnected so that the drain The TEU is connected to the first power terminal, the source of the TEU is connected to the drain of the control MOS transistor, the source of which is connected to the second power terminal serving as a common bus, and is connected to the source of the auxiliary MOS transistor, while the gate of the control MOS transistor is connected to the third control terminal, and the gate of the auxiliary MOS transistor is connected to the drain of the control MOS transistor, and a boost chain consisting of a parallel connection of the capacitor and diode is introduced into the device, the first common point of connection of one capacitor plate and the anode of the diode connected to the drain of the auxiliary MOS transistor, and the second common connection point of the second capacitor plate and the cathode of the diode is connected to the gate of the TEU.