RU57016U1 - DEVICE FOR DETERMINING THE CURRENT ELECTRIC MODE OF THE ELECTRIC TRANSMISSION LINE - Google Patents

Abstract

The utility model relates to the field of information processing systems and can be used to control the transmission line (transmission line), based on its adaptive model, tunable according to current information about the parameters of the electric mode of the transmission line. Allows measuring longitudinal active , and reactive , line resistance, as well as transverse active R ₀ and reactive X ₀ line resistance. The device for determining the current parameters of the electric mode of the power line contains three parallel-connected units for calculating the active and reactive resistance of the longitudinal and transverse branches of the T-shaped equivalent circuit of the power line, the inputs of which are connected to the beginning of the power line and through the communication channel to its end, and the outputs of the calculation units connected to a computer. Moreover, in two identical calculation units, the first and second sampling and storage devices are connected to the input of the device, and the inverter and adder are connected in series to the first sampling and storage device. An adder, a programmer, a third retrieval-storage device, a fourth retrieval-storage device, a second inverter, a second adder, the output of which is connected to a multiplier to which an integrator is connected in series, a multiplier-divider, the output of which is connected to COMPUTER. In addition, the input of the fifth sample-storage device is connected to the input of the device, and the sixth sample-storage device, the third adder, the output of which is connected to the first multiplier, are connected in series to the output of the fifth sample-storage device. A clock is connected to each sample-storage device. The inputs of the third and fifth sampling-storage devices are connected to the second multiplier, the output of which is connected to the second integrator, the output of which is connected to the second multiplier -

divider connected to a computer. At the same time, the third adder and the converter of effective values are connected to the output of the fifth sampling-storage device, the outputs of which are connected to the third multiplier connected to the inputs of the first and second multipliers-dividers. The third block for calculating the active and reactive resistances of the transverse branch of the T-shaped equivalent circuit of the power line contains the seventh and eighth sampling and storage devices, the inputs of which are connected to the input of the device. At the same time, the third inverter, the fourth adder, are sequentially connected to the seventh sample-storage device. The fourth adder, the second programmer, the fourth inverter, and the fifth adder are connected in series to the eighth sample-storage device. The input of the ninth sample-storage device is connected to the input of the device. The fifth adder, the tenth sampling-storage device, the eleventh sampling-storage device, the fifth inverter, the sixth adder, the output of which is connected to the fourth multiplier, to which the third integrator, the third multiplier divider is connected, are connected in series to the output of the ninth sampling and storage device which is connected to the computer. The inputs of the twelfth and thirteenth sampling-storage devices are connected to the input of the device. The sixth inverter is connected to the output of the twelfth sampling and storage device, the output of which is connected to the seventh adder. The seventh adder, the fourteenth sample-storage device, the fifteenth sample-storage device, the eighth adder, the output of which is connected to the fourth multiplier, are connected in series to the output of the thirteenth sample-storage device. A second clock is connected to each sample-storage device. The inputs of the tenth and fourteenth sampling-storage devices are connected to the fifth multiplier, the output of which is connected to the fourth integrator, the output of which is connected to the fourth multiplier-divider connected

to the computer. The eighth adder and the second converter of effective values are also connected to the output of the fourteenth sample-storage device, the outputs of which are connected to the sixth multiplier connected to the inputs of the third and fourth multipliers-dividers. 5 ill.

Description

The utility model relates to the field of information processing systems and can be used to control the transmission line (power line), based on its T-shaped adaptive model, tunable according to current information about the parameters of the electric mode of the power line.

Currently, there are no devices for determining the current parameters of the electric mode of the power line.

The objective of the utility model is to create a device for determining the current parameters of the electric mode of the power line.

The device for determining the current parameters of the electric mode of the power line contains three parallel-connected units for calculating the active and reactive resistances of the longitudinal and transverse branches of the T-shaped equivalent circuit of the power line, the inputs of which are connected to the beginning of the power line and through the communication channel to its end, and the outputs of the calculation units connected to a computer.

Moreover, in two identical calculation units, the first and second sampling and storage devices are connected to the input of the device, and the inverter and adder are connected in series to the first sampling and storage device. An adder, a programmer, a third retrieval-storage device, a fourth retrieval-storage device, a second inverter, a second adder, the output of which is connected to a multiplier to which an integrator is connected in series, a multiplier-divider, the output of which is connected to COMPUTER. In addition, the input of the fifth sample-storage device is connected to the input of the device, and the sixth sample-storage device, the third adder, the output of which is connected with the first

multiplier. A clock is connected to each sample-storage device. The inputs of the third and fifth sampling-storage devices are connected to the second multiplier, the output of which is connected to the second integrator, the output of which is connected to the second multiplier-divider, connected to the computer. At the same time, the third adder and the converter of effective values are connected to the output of the fifth sampling-storage device, the outputs of which are connected to the third multiplier connected to the inputs of the first and second multipliers-dividers.

The third block for calculating the active and reactive resistances of the transverse branch of the T-shaped equivalent circuit of the power line contains the seventh and eighth sampling and storage devices, the inputs of which are connected to the input of the device. At the same time, the third inverter, the fourth adder, are sequentially connected to the seventh sample-storage device. The fourth adder, the second programmer, the fourth inverter, and the fifth adder are connected in series to the eighth sample-storage device. The input of the ninth sample-storage device is connected to the input of the device. The fifth adder, the tenth sampling-storage device, the eleventh sampling-storage device, the fifth inverter, the sixth adder, the output of which is connected to the fourth multiplier, to which the third integrator, the third multiplier divider is connected, are connected in series to the output of the ninth sampling and storage device which is connected to the computer. The inputs of the twelfth and thirteenth sampling-storage devices are connected to the input of the device. The sixth inverter is connected to the output of the twelfth sampling and storage device, the output of which is connected to the seventh adder. The seventh adder, the fourteenth sample-storage device, the fifteenth sample-storage device, the eighth adder, the output of which is connected to the fourth multiplier, are connected in series to the output of the thirteenth sample-storage device. To each

a second clock is connected to the fetch-storage device. The inputs of the tenth and fourteenth sampling-storage devices are connected to the fifth multiplier, the output of which is connected to the fourth integrator, the output of which is connected to the fourth multiplier-divider, connected to the computer. The eighth adder and the second converter of effective values are also connected to the output of the fourteenth sample-storage device, the outputs of which are connected to the sixth multiplier connected to the inputs of the third and fourth multipliers-dividers.

Using the proposed device circuit, you can determine the current parameters of the electric mode of the T-shaped equivalent circuit of the power line (figure 4):

1) longitudinal active , and reactive , line resistance;

2) transverse active R ₀ and reactive X ₀ line resistance.

Figure 1 presents a diagram of the inclusion of a device for determining the current parameters of the electric mode of the power line in the transmission line and to the system (computer).

Figure 2 shows the hardware circuit of the calculation unit and .

Figure 3 shows the hardware circuit of the calculation unit R ₀ and X ₀ .

Figure 4 presents the T-shaped equivalent circuit of the power line.

The device (figure 1) contains three parallel connected calculation unit: calculation unit , calculation unit , and a calculation unit R ₀ , X ₀ , the inputs of which are connected to the beginning of the power line and through the communication channel (CS) with its end, and the outputs of the calculation units are connected to a computer.

Calculation Blocks , (figure 2) and , each of the first 1 (UVX 1) and second 2 (UVX 2) sampling and storage devices, the inputs of which are connected to the input of the device, are similar and consist. To the first device

sample-storage 1 (UVX 1), the first inverter 3, the first adder 4 are connected in series. To the second device of sample-storage 2 (UVX 2) the first adder 4, programmer 5, the third sample-storage device 6 (UVX 3) are connected in series, the fourth a sampling-storage device 7 (UVX 4), a second inverter 8, a second adder 9, the output of which is connected to the first multiplier 10. The first integrator 11 is connected in series to the first multiplier 10, the first multiplier divider 12, the output of which is connected to a computer. In addition, the second input of the second adder 9 is connected to the output of the third sampling and storage device 6 (UVX 3). The input of the fifth sampling and storage device 7 (UVX 5) is connected to the input of the device. The fifth sampling-storage device 13 (UVX 5) is connected in series to the sixth sampling-storage device 14 (UVX 6), the third adder 15, the output of which is connected to the first multiplier 10. A clock generator 16 (TG) is connected to each sampling-storage device. The inputs of the third 6 (UVX 3) and fifth 13 (UVX 5) of the sampling and storage devices are connected to the second multiplier 17. The output of the second multiplier 17 is connected to the second integrator 18, the output of which is connected to the second multiplier divider 19 connected to the computer. The third adder 15 and the current value converter 20 (PDZ) are connected to the output of the fifth sampling-storage device 13 (UVX 5), the outputs of which are connected to the third multiplier 21 connected to the inputs of the first 12 and second 19 multiplier divisors.

The calculation unit R ₀ , X ₀ (figure 3) consists of the seventh 22 (UVX 7) and the eighth 23 (UVX 8) sampling and storage devices, the inputs of which are connected to the input of the device. The third inverter 24, the fourth adder 25 are connected in series to the seventh sampling-storage device 22 (UVX 7). The fourth adder 25, the second programmer 26, the fourth inverter 27, and the fifth adder 29 are connected in series to the eighth sampling-storage device 23 (UVX 7). Ninth device input

sample-storage 28 (UVX 9) is connected to the input of the device. The fifth adder 29, the tenth sampling and storage device 30 (UVX 10), the eleventh sampling and storage device 31 (UVX 11), the fifth inverter 32, the sixth adder 33, the output of which are connected in series to the output of the ninth sampling and storage device 28 (UVX 9) connected to the fourth multiplier 34, to which a third integrator 35, a third multiplier divider 36, the output of which is connected to a computer, are connected in series. The inputs of the twelfth 37 (UVX 12) and thirteenth sampling-storage devices 38 (UVX 13) are connected to the input of the device. The sixth inverter 39 is connected to the output of the twelfth sampling and storage device 37 (UVX 12), the output of which is connected to the seventh adder 40. The seventh adder 40, the fourteenth sampling and storage device 41 are connected in series to the output of the thirteenth sampling-storage device 38 (UVX 12) UVX 14), the fifteenth sampling-storage device 42 (UVX 15), the eighth adder 43, the output of which is connected to the fourth multiplier 34. A second clock 44 (TG 2) is connected to each sampling-storage device. The inputs of the tenth 30 (UVX 10) and fourteenth 41 (UVX 14) of the sample-storage device are connected to the fifth multiplier 45, the output of which is connected to the fourth integrator 46, the output of which is connected to the fourth multiplier-divider 47 connected to the computer. The eighth adder 43 and the second RMS converter 48 (PDZ 2), the outputs of which are connected to the sixth multiplier 49 connected to the inputs of the third 36 and fourth 47 multiplier divisors, are also connected to the output of the fourteenth sample-storage device 41 (UVX 14).

All sampling and storage devices of each calculation unit can be implemented on 1100SK2 microcircuits. Programmers and programmers of actual values are made on the microcontroller of the 51 series atmel AT89S53. Inverters, combiners and integrators

implemented on operational amplifiers 140UD17A. As multipliers and multipliers-dividers can be used chip 525PSZ. Clock generators are implemented on the AT80C2051 microcontroller.

The device operates as follows. To the inputs of the calculation unit , calculation unit , and the calculation unit R ₀ , X _{0 of the} device that implements the considered method of determining the current parameters of the power transmission line to build its T-shaped adaptive model, simultaneously the following signals of the load mode and the idle mode of the line were applied:

one) , , to the input buses of the calculation unit , ,

2) , , to the input buses of the calculation unit , ,

3) , , , to the input buses of the calculation unit R ₀ , X ₀ .

In load mode on the calculation unit , nA input of the first sample and hold device 1 (SHA 1) receives a signal u ₂ (t _j), the input of the second sample and hold device 2 (SHA 2), the signal u ₁ (t _j), and the input of the fifth sample-and-hold device 13 (UVX 5) signal i ₁ (t _j ),

where t _j = t ₁ , t ₂ , ..., t _N - time instants,

- the number of partitions on the period T,

Δt = 1 · 10 ^-3 s is the discretization step of arrays of instantaneous values of currents and voltages at the beginning and at the end of power lines.

The signal values were recorded in the sample-storage blocks 1 (UVX 1), 2 (UVX 2) and 13 (UVX 5) and stored there as current ones, then from the output of the device

sample-storage 1 (UWX 1), the signal u ₂ (t _j ) was fed to inverter 3. Using inverter 3, the negative value of the previous signal u ₂ (t _j ) was converted to positive. From the output of the inverter 3, the value of the signal u ₂ (t _j ) was fed to the input of the adder 4. At the same time, from the output of the sampling-storage device 2 (UVX 2), the value of the signal u ₁ (t _j ) was fed to the second input of the adder 4. C using the adder 4 was determined by the difference in the values of the signals u ₁ (t _j ) -u ₂ (t _j ). From the output of the adder 4, the difference in the values of the signals u ₁ (t _j ) -u ₂ (t _j ) was sent to the programmer 5. Using the programmer 5, the difference in the values of the signals u ₁ (t _j ) -u ₂ (t _j ) was changed in proportion to the coefficient k = 0; 0, 1 ... 1. From the output of the programmer 5 signal entered the sampling-storage device 6 (UVX 3) and to the input of the multiplier 17. At the same time, the signal value i ₁ (t _j ) entered the sampling-storage block 13 (UVX 5) and to the second input of the multiplier 17. The values of the signals recorded in the blocks storage samples 6 (UVX 3) and 13 (UVX 5) were stored there as current ones. From the output of the device sampling-storage 6 (UVX 3) signal arrived at the input of the adder 9 and into the device fetch-storage 7 (UVX 4), in which it became the previous value, and from the output of the device fetch-storage 13 (UVX 5), the value of the signal i ₁ (t _j ) was fed to the first and second inputs the programmer of effective values of 20 (PDZ), then it entered the sampling-storage device 14 (UVX 6) and became the previous value. At the outputs of the programmer of the effective values of 20 (PDZ) received twice the actual value of the signal .

From the outputs of the programmer of the actual values of 20 (PDZ), the effective values of the signals I ₁ and I ₁ were fed to the inputs of the multiplier 21. Using the third multiplier 21, the values of the signals I ₁ and I _{1 were} multiplied and applied to the inputs of the first 12 and second 19 multiplier divisors. From the output of the fourth sampling-storage device 7 (UVX 4) the previous signal value entered the second inverter 8, through which the negative value of the previous signal transformed into positive. From the output of the second inverter 8 signal value received at the input of the second adder 9. At the same time, from the output of the third sampling-storage device 6 (UVX 3), the current signal value received at the input of the second adder 9, with which the difference between the current and previous signal values was determined . Simultaneously with the process described above, from the output of the sixth sampling-storage device 14 (UVX 6), the previous value of the signal i ₁ (t _j ) was fed to the input of the third adder 15 and from the output of the fifth sampling-storage device 13 (UVX 5) the current value of the signal i ₁ (t _j ) was received at the input of the third adder 15. Using the third adder 15, the sum of the current and previous values of the signal i ₁ (t _j ) was determined. From the output of the second adder 9, the difference between the current and previous signal values was fed to the input of the first multiplier 10, and from the output of the third adder 15, the sum of the current and previous values of the signal i ₁ (t _j ) was fed to the second input of the first multiplier 10. Using the first multiplier 10, the difference values and the sum of the signals were multiplied and fed to the input of the first integrator 11. Using the first integrator 11 summarized

the product of the difference and the sum of the signals and determined the value of the reactive power loss .

From the output of the first integrator 11, the value of the reactive power loss was fed to the input of the first multiplier-divider 12. At the same time, the products of the current signal values were determined using the second multiplier 17 and i ₁ (t _j ), which were fed to the input of the second integrator 18. Using the second integrator 18, the losses of active power were determined .

From the output of the second integrator 18, the value of the active power loss was fed to the input of the second multiplier divider 19. Using the first multiplier divider 12, the longitudinal reactance of the power line was determined (Fig. 4) .

Using the second multiplier divider 19, the value of the longitudinal active resistance of the line was determined (figure 4) .

The work of another block calculation , similar to the operation of the first calculation unit , But on the input of the first sample and hold device 1 (SHA 1) of the incoming signal u ₂ (t _j), the input of the second sample and hold device 2 (SHA 2), the signal u ₁ (t _j), and the input device of the fifth sample- storage 13 (UVX 5) signal i ₂ (t _j ).

The signal values were recorded in the sampling-storage units 1 (UVX 1), 2 (UVX 2) and 13 (UVX 5) and stored there as current, then from the output of the sampling-storage device 1 (UVX 1) the signal u ₂ (t _j ) entered the first inverter 3. Using the first inverter 3, the negative value of the previous one

signal u ₂ (t _j ) was converted to positive. From the output of the first inverter 3, the value of the signal u ₂ (t _j ) was fed to the input of the first adder 4. At the same time, from the output of the second sampling-storage device 2 (UVX 2), the value of the signal u ₁ (t _j ) was fed to the second input of the first the adder 4. Using the first adder 4 was determined by the difference in the values of the signals u ₁ (t _j ) -u ₂ (t _j ). From the output of the first adder 4, the difference in the values of the signals u ₁ (t _j ) -u ₂ (t _j ) entered the programmer 5. Using the programmer 5, the difference in the values of the signals u ₁ (t _j ) -u ₂ (t _j ) changed proportionally (1 -k), and the coefficient k = 0; 0, 1 ... 1. From the output of the programmer 5 signal entered the sampling-storage device 6 (UVX 3) and to the input of the multiplier 17. At the same time, the signal value i ₂ (t _j ) entered the fifth block of sampling-storage 13 (UVX 5) and to the second input of the second multiplier 17. Otherwise, the second calculation unit , similar to the operation of the calculation unit , and consisted in the fact that they determined the twice current value of the current .

Then each digital readout was saved as the current and previous, the difference and the sum of each pair of the current and previous values were determined, their difference and the sum were multiplied, these products were summarized.

Next, reactive power losses were determined on longitudinal reactance power lines: .

Multiplied the current samples of the signals and determined the loss of active power on longitudinal resistance power lines:

Options and (figure 4) was determined by the formulas:

In the block calculating R _0, X ₀ nA input sample and hold seventh apparatus 22 (SHA 7) receives a signal u ₂ (t _j), the input of the sample-and-hold eighth device 23 (SHA 8), the signal u ₁ (t _j), on the the input of the ninth sampling-storage device 28 (UVX 9) signal u ₁ (t _j ) to the input of the twelfth sampling-storage device 37 (UVX 12) signal i ₂ (t _j ), and the input of the thirteenth sampling and storage device 38 (UVX 13 ) signal i ₁ (t _j ).

The signal values were recorded in sampling and storage units 22 (UVX 7), 23 (UVX 8), 28 (UVX 9), 37 (UVX 12) and 38 (UVX 13) and stored there as current ones, then from the output of the sampling device storage 22 (UVX 7), the signal u ₂ (t _j ) was supplied to the third inverter 24. Using the third inverter 24, the negative value of the previous signal u ₂ (t _j ) was converted to positive. From the output of the third inverter 24, the signal value u ₂ (t _j ) was fed to the input of the fourth adder 25. At the same time, from the output of the eighth sampling-storage device 23 (UWX 8), the signal value u ₁ (t _j ) was fed to the second input of the fourth the adder 25. Using the fourth adder 25, the difference between the values of the signals u ₁ (t _j ) -u ₂ (t _j ) was determined. From the output of the fourth adder 25, the difference in signal values

u ₁ (t _j ) -u ₂ (t _j ) entered the programmer 26. Using the programmer 26, the difference in the values of the signals u ₁ (t _j ) -u ₂ (t _j ) was changed in proportion to the coefficient k = 0; 0, 1 ... 1. From the output of the programmer 26 signal entered the fourth inverter 27. Using the fourth inverter 27, the negative value of the previous signal transformed into positive. The output of the fourth inverter 27 signal value received at the input of the fifth adder 29. At the same time, from the output of the ninth sampling-storage device 28 (UVX 9), the signal value u ₁ (t _j ) was fed to the second input of the fifth adder 29. Using the fifth adder 29, the difference in signal values was determined . From the output of the fifth adder 29, the difference in signal values arrived at the tenth sampling-storage device 30 (UVX 10), into the fifth multiplier 45. At the same time, from the output of the twelfth sampling-storage device 37 (UVX 12), the signal i ₂ (t _j ) was fed to the sixth inverter 39. Using the sixth inverter 39, negative the value of the previous signal i ₂ (t _j ) was converted to positive. From the output of the sixth inverter 39, the value of the signal i ₂ (t _j ) was fed to the input of the seventh adder 40. At the same time, from the output of the thirteenth sampling-storage device 38 (UVX 13), the value of the signal i ₁ (t _j ) was fed to the second input of the seventh the adder 40. Using the seventh adder 40 was determined by the difference in the values of the signals i ₁ (t _j ) -i ₂ (t _j ). From the output of the seventh adder 40, the difference in the values of the signals i ₀ (t _j ) = i ₁ (t _j ) -i ₂ (t _j ) entered the fourteenth sampling device -

storage 41 (UVX 14) and to the second input of the multiplier 45. Otherwise, the work of the third calculation unit R ₀ , X _{0 is} similar to the operation of the calculation unit , and calculation unit , and consisted in the fact that they determined the twice current value of the current .

Then each digital readout was saved as the current and previous, the difference and the sum of each pair of the current and previous values were determined, their difference and the sum were multiplied, these products were summarized. Next, the reactive power loss ΔQ _{0 was} determined on the transverse reactance X _{0 of} the power line: .

We multiplied the current samples of the signals and determined the loss of active power ΔP ₀ on the transverse resistance R _{0 of} the power line:

The parameters R ₀ and X ₀ (figure 4) were determined by the formulas:

Thus, the utility model allows to measure longitudinal active , and reactive , line resistance, as well as transverse active R ₀ and reactive X ₀ line resistance.

Claims (1)

A device for determining the current parameters of the electric mode of the power line, characterized in that it contains three parallel-connected units for calculating the active and reactive resistances of the longitudinal and transverse branches of the T-shaped equivalent circuit of the power line, the inputs of which are connected to the beginning of the power line and through the communication channel to its end and the outputs of the calculation blocks are connected to a computer, while in two identical calculation blocks the first and second sampling and storage devices are connected to the input of the device, and to vomu sample-and-hold device are connected in series inverter, an adder; an adder, a programmer, a third access-storage device, a fourth access-storage device, a second inverter, a second adder, the output of which is connected to a multiplier to which an integrator is connected in series, a multiplier-divider, the output of which is connected to A computer, in addition, the input of the fifth sample-storage device is connected to the input of the device, and the sixth sample-storage device is connected in series to the output of the fifth sample-storage device, t ety adder whose output is connected to the first multiplier; a clock is connected to each sample-storage device; the inputs of the third and fifth sampling and storage devices are connected to a second multiplier, the output of which is connected to a second integrator, the output of which is connected to a second divider multiplier connected to a computer; at the same time, the third adder and the converter of effective values are connected to the output of the fifth sampling-storage device, the outputs of which are connected to the third multiplier connected to the inputs of the first and second divider multipliers; the third unit for calculating the active and reactive resistances of the transverse branch of the T-shaped equivalent circuit of the power line contains the seventh and eighth sampling and storage devices, the inputs of which are connected to the input of the device; at the same time, the third inverter, the fourth adder are connected in series to the seventh sample-storage device, the fourth adder, the second programmer, the fourth inverter, the fifth adder are connected in series to the eighth sample-storage device, the input of the ninth sample-storage device is connected to the input of the device, to the output of the ninth the sampling and storage devices are connected in series with the fifth adder, the tenth sampling-storage device, the eleventh sampling-storage device, the fifth inverter, the sixth adder, output for which it is connected to the fourth multiplier, to which the third integrator is connected in series, the third multiplier-divider, the output of which is connected to a computer, the inputs of the twelfth and thirteenth sampling and storage devices are connected to the input of the device, the sixth inverter is connected to the output of the twelfth sampling and storage device, the output which is connected with the seventh adder, the seventh adder, the fourteenth sample-storage device, the fifteenth must be connected in series to the output of the thirteenth sample-storage device roystvo sample and hold eighth adder, the output of which is connected to the fourth multiplier; a second clock is connected to each sample-storage device; the inputs of the tenth and fourteenth sampling-storage devices are connected to the fifth multiplier, the output of which is connected to the fourth integrator, the output of which is connected to the fourth multiplier-divider connected to the computer, the eighth adder and the second converter of effective values are also connected to the output of the fourteenth multiplier-storage device, the outputs of which are connected to the sixth multiplier associated with the inputs of the third and fourth multiplier divisors.