RU56683U1 - AUTOMATED SYSTEM FOR COLLECTING AND PROCESSING DATA OF THE INFORMATION ANALYTICAL CENTER OF THE AIRLINE - Google Patents

Abstract

The invention relates to computing, in particular, to an automated system for collecting and processing data of an information-analytical center of an airline. The technical result is to simplify the system and increase its speed by eliminating buffer memory blocks and a time interval selector and implementing an asynchronous mode of interaction between client and server. The technical result is achieved by the fact that the system contains three registers, an address identification device for updated data records, a client request data address identification device, a decoder, a data reading control signal generating unit and a data output channel switching unit. 5 ill.

Description

The invention relates to computing, in particular, to an automated system for collecting and processing data of an information-analytical center of an airline.

The peculiarity of the technical task to be solved is that customers who use the real-time information system that collects and processes data from distributed remote information sources can receive information collected and processed on the server in the form of relevant help documents in real time time.

Known systems that could be used to solve the problem (1, 2).

The first of the known systems contains data reception and storage units connected to control and data processing units, search and selection units connected to data storage and display units, the synchronizing inputs of which are connected to the outputs of the control unit (1).

A significant drawback of this system is the impossibility of solving the problem of updating data stored in memory in the form of relevant documents at the same time as solving the problem of delivering the contents of these documents to clients in real time.

Another system is known that contains a database server, the information input of which is connected to the output of the data output unit, the address input of the database server is connected to the output of the unit for generating data write and read addresses, memory units whose inputs are connected to the control unit and input and output units data, a processor, the inputs of which are connected to the control unit, and the outputs are connected to the inputs of the data input, data output, memory blocks, and the unit for generating data write and read addresses. (2).

The last of the above technical solutions is closest to the described.

Its drawback is, firstly, in the structural complexity due to the fact that in addition to the available server memory, it uses two buffer memory blocks to implement the procedure for updating data in the client-server information network, and, secondly, the hard mode implemented in the device clock synchronization using the time interval selector leads to an unjustified loss of time, which, in turn, reduces the speed of the system when serving user requests.

The purpose of the invention is to simplify the system and increase its speed by eliminating buffer blocks of memory and the selector time intervals and implementing an asynchronous mode of interaction between the client and server.

This goal is achieved in that the system containing the first register, the information input of which is the first information input of the system, the synchronizing input is the first synchronizing input of the system, one output is the information output of the system, and the other is connected to the information input of the device identifying the address of the updated records, the second a register, the information input of which is the second information input of the system, the synchronizing input is the second synchronizing input of the system, and one output is connected to the input of the decoder, the third register, the information input of which is the third information input of the system, the synchronizing input is the third synchronizing input of the system, and the switching unit of the data output channels, the control inputs of which are connected to the corresponding outputs of the decoder, the information input is connected to the output of the third register , and the inputs are the information outputs of the group, a device for identifying the address of the client request data is introduced, the information input of which is connected with another information output of the second register, the synchronization input is connected to the second synchronizing input of the system, and the control input is connected to the control output of the device for identifying the address of the updated records, the synchronizing input of which is connected to the first synchronizing input of the system, and the block for generating control signals for reading data, the first information and the first

the synchronizing inputs of which are connected to the information and synchronizing outputs of the identification device of the address of the updated records, respectively, the second information and second synchronizing inputs are connected to the information and synchronizing outputs of the identification device of the address of the client request data, respectively, the first and second control inputs of the data reading control signal generation block are the first and second control inputs of the system, the address output is the address output of the system we, the first synchronizing output is the first synchronizing output of the system, the second synchronizing output is the second synchronizing output of the system, and the installation output is connected to the installation inputs of the first register and the device for identifying the address of the updated records, while the synchronizing input of the switching unit of the data output channels is connected to the third synchronizing input system, and the installation output is connected to the installation input of the third register.

The invention is illustrated by drawings, in which Fig. 1 shows a structural diagram of a system, Fig. 2 is a structural diagram of a device for identifying an address of updated data records, Fig. 3 is a structural diagram of a device for identifying client request data, and Fig. 4 is a block diagram of a block generating control signals for reading data, Fig. 5 is a structural diagram of a block for switching data output channels.

The system (figure 1) contains the first 1, second 2 and third 3 registers, block 4 identifying the address of the updated data records, block 5 identifying the address of the data of the client request, decoder 6, block 7

the formation of control signals for reading data and block 8 switching channels for issuing data.

Figure 1 shows the first 11, second 12 and third 13 information inputs of the system, the first 14, second 15 and third 16 synchronizing inputs of the system, the first 17 and second 18 control inputs of the system, as well as information output 20, address output 21, first 22 and the second 23 information outputs and a group of information outputs 24-26 of the system.

The device for identifying the address of updated records (Fig. 2) contains a memory unit 30 made in the form of read-only memory, a decoder 31, a trigger 32, AND elements 33-35, OR element 36, delay elements 37, 38. The drawing shows information 40, synchronizing 41 and installation 42 inputs of the device, as well as information 43, synchronizing 44 and control outputs of the device.

The client request data address identification device (FIG. 3) comprises a memory unit 50 made in the form of read-only memory, a decoder 51, AND elements 53-56, OR element 57, delay elements 58, 59. The drawing shows information 60, synchronizing 61 and controlling 62 inputs of the device, as well as information 63 and synchronizing 64 outputs of the device.

The data-reading control signal generating unit (Fig. 4) contains a reversible counter 70, OR elements 71, 72, a group of OR elements 73, delay elements 74, 75, 76. The drawing shows the first 77 and second 78 information inputs, the first 79 and second 80 clock inputs, the first 17 and second 18 control inputs, and

also address 21, first 22 and second 23 synchronizing and installation 81 outputs of the device.

The switching unit of the data output channels (Fig. 5) contains groups of 90-92 AND elements, delay elements 93, 94. The drawing shows information 95 input, control 96-98 inputs and synchronizing 99 block input, as well as a group of 24-26 information outputs and installation 100 output block.

All nodes and elements of the system are made on standard potential-impulse elements.

The system operates as follows.

Information input 11 of the system along the data transmission path of the IAC KB information network consistently receives messages (codograms) from information source objects containing indicative and information parts.

The structure of the codogram is as follows:

Characteristic part of the codogram Information part of the codogram Citizen Identifier Case ID Code Code for the content of information about a citizen, grouped into thematic groups

The codogram code from input 11 enters the information inputs of register 1, where it is entered by the synchronizing pulse supplied to the synchronizing input of register 1 from input 14.

The content part of the codogram from one of the information outputs of the register 1 goes to the output 20 of the system, and the feature part of the codogram from other information outputs of the register 1 goes to the information input 40 of device 4, from where the message identifier code is input to the decoder 31, which decrypts the code of the identifier of the encoding and outputs potential for one of its exits. For definiteness, we assume that the high potential of the decoder 31 is received at one input of the element 33 I.

Unlike the prototype, the system is synchronized upon receipt of the codogram at the system input 11 by the synchronizing pulse from input 14, which, through the synchronizing input 41 of the device 4, enters both the input of the delay element 37 and the direct input of the trigger 32, setting it to a single state in which a negative potential will be issued from the inverse output 45 of the trigger 32.

The delay element 37 delays the synchronization pulse for the time the codogram code is entered in register 1. After that, the delayed synchronization pulse from the output of element 37 goes to the polling state of elements 33-35 I.

Since only the And element 33 will be opened by the high potential of the decoder 31, then, after passing through this And element, the delayed synchronizing pulse, firstly, enters the read input of the fixed memory cell of the permanent storage device 30, where the base address of the server database memory cell is stored, where it is necessary to write down the information received by register 1 and reads it through the information output 43 of the device 4, the information input 77 of block 7 and the elements OR of the group 73 to the information input of the reverse counter 70.

Secondly, the same synchronizing read pulse at the output of the OR element 36 of device 4 is delayed by the delay element 38 while reading the contents of the fixed cell ROM 30 and then through the output 44 of the device 4, the synchronizing input 79 of block 7 and the OR element 71 is fed to the synchronizing input of the reverse counter, fixing in it the code of the base address of the memory cell of the server database, where you need to record the substantial part of the received codogram.

As a result of this, a code of the base address of the server database memory cell will appear on the address output of the system 21, where the contents of the received codogram should be written.

Thirdly, the same synchronization pulse from the input 79 of block 7 is delayed by the element 75 for the time the code of the base address is entered in the counter 70 and through the system output 22 is issued to the input of the first server interrupt channel. By this signal, the server goes to the subroutine for recording the content of the codogram from the output 20 of the system at the address that is generated at the output of the 21 system.

In parallel, the pulse from the output of element 75 is delayed by the delay element 76 for the time of recording the content of the codogram from output 20 to the address generated at output 21, and then from output 81 of device 4 it is output to the installation inputs of register 1 and trigger 32 of device 4, returning them in the initial state and thereby preparing for a new cycle of work.

The trigger 32 of the device 4 is designed to block the chain of passage of signals of client requests during the update of the server database.

If this trigger is in its initial state, then the high potential from its inverse output 45 through the input 62 of the device 5 goes to one of the inputs of the element 56 AND of the device 5 and opens it one at a time, allowing the system to work in the mode of issuing data on customer requests.

Codes of requests of specialists come from input 12 to the information inputs of register 2, where they are entered by synchronizing pulses from input 15.

The structure of the user request codogram is as follows:

The code The code social worker request id social worker workstation addresses

The code of the request identifier of the social worker from one of the outputs of the register 2 through the input 60 of the device 5 is fed to the input of the decoder 51, which decrypts the code of the request identifier of the client and gives a high potential to one of its outputs. For definiteness, we assume that the high potential of the decoder 51 entered one input of element 55 I.

Unlike the prototype, synchronization of the system’s operation in this mode is also carried out upon receipt of a codogram of a request for input to the system 12 by a synchronizing pulse from input 15, which, through the synchronizing input 61 of device 5, goes to another input of element 56 I.

If element 56 AND is closed by the low potential of trigger 32, then the server database is being updated and the request signal chain will be blocked.

If the And 56 element is opened, then the synchronizing pulse from the input 61 of the device 5 passes to the input of the delay element 58, which delays it while the request code is entered into the register 2. After that, the delayed synchronization pulse from the output of the element 58 goes to the polling of the element status 53-55 I.

Since only the 55 And element will be opened by the high potential of the decoder 31, then, after passing through this And element, the delayed synchronizing pulse, firstly, enters the read input of the fixed memory cell of the permanent storage device 50, where the base address of the server database memory cell is stored, whence it is necessary to give out the requested information and reads it through the information output 63 of the device 5, the information input 78 of block 7 and the elements OR of the group 73 to the information input of the reverse counter 70.

Secondly, the same synchronizing read pulse at the output of the OR element 56 56 is delayed by the delay element 59 while reading the contents of the fixed cell ROM 50 and then through the output 64 of the device 5, the synchronizing input 80 of block 7 and the OR element 71 goes to the synchronizing input of the reverse counter 70, fixing in it the code of the base address of the memory cell of the server database.

As a result of this, at the address output of the system 21, the code of the base address of the server database memory cell will appear, from where it is necessary to select the requested information.

Thirdly, the same synchronization pulse from the input 80 of block 7 passes through the OR element 72, is delayed by the element 74 for the time the base address code is entered into the reverse counter 70 and, through the system output 23, is issued to the input of the second server interrupt channel. By this signal, the server goes to the subroutine for reading the content of the codogram from the memory cell of the server database at the address that is generated at the output of the system 21.

The information read from the memory cell of the server database is fed to input 13 of register 3, where it is entered by the synchronizing pulse of the server from input 16.

From the output of register 3, the data upon request through the input 95 of block 8 is supplied to the inputs of each of the groups of 90-92 AND elements, the outputs of which are connected to the inputs of the corresponding workstations of the clients through the corresponding outputs 24-26 of the system.

The client’s workstation is selected by the code of his address coming from other information outputs of register 2 to the input of decoder 6. Decoder 6 decodes the address code and gives a high potential to one of its outputs, for example, to its first output. High potential from the first output through the input 96 of block 8 is supplied to one of the inputs of elements 90 I.

In parallel with this, the synchronizing pulse from input 16 through the input 99 of block 8 is fed to the input of the delay element 93, which delays it while the content of the codogram is being written to register 3, and then passes to the other inputs of the 90 And elements, rewriting the data from the output of register 3 to the input the corresponding workplace of the client through exit 24 of the system.

In addition, the synchronizing pulse from the output of the element 93 is delayed by the time of issuing the request data to the client’s workplace by the delay element 94 and is then issued from the output 100 to the installation inputs of the register 3, returning it to its original state.

In addition, unlike the prototype, in this system there is no need for the client to re-type the request code if the identifiers of the data attributes are close to each other.

In this case, after receiving the requested data at the address generated in the reverse counter 70 of block 7, it is enough for the client at his workplace to press one of the Forward or Back buttons.

For example, when you press the Forward key, an impulse is received at the system input 17, which is fed to the counting input of the reverse counter 70, increasing its contents by one, and therefore the address code at the system output 21 also increases by one.

The same pulse passes through the OR element 72, is delayed by the element 74 for the duration of the operation of the reverse counter 70, and is transmitted to the input of the second channel of the server interrupt through the output 23 of the system. By this signal, the server goes to the subroutine for reading the content of the codogram from the next memory cell of the server database at the address that is generated at the system output 21.

If the client presses the "Back" button at his workplace, then the pulse goes to the input 18 of the system and then to the subtracting input of the reverse counter. With the arrival of this pulse, the reverse counter 70 decreases the base address of the memory cell by one.

In addition, the same pulse passes through the OR element 72, is delayed by the element 74 for the duration of the operation of the reverse counter 70, and through the system output 23 is issued to the input of the second server interrupt channel. By this signal, the server goes to the subroutine for reading the content of the codogram from the next memory cell of the server database at the address that is generated at the system output 21.

Thus, the exclusion of buffer blocks of memory and the time interval selector made it possible to significantly simplify the system, and the implementation of the asynchronous mode of interaction between the client and server made it possible to significantly increase its speed.

Sources of information taken into account when drawing up the description of the application:

1. US Patent No. 5713014, 1998.

2. US Patent No. 5136708, 1992 (prototype)

Claims (1)

An automated data collection and processing system of the airline’s information and analytical center, containing the first register, the information input of which is the first information input of the system, the synchronizing input is the first synchronizing input of the system, one output is the information output of the system, and the other is connected to the information input of the address identification device updated records, the second register, the information input of which is the second information input of the system the input is the second synchronizing input of the system, and one output is connected to the input of the decoder, the third register, the information input of which is the third information input of the system, the synchronizing input is the third synchronizing input of the system, and the switching unit of the data output channels, the control inputs of which are connected to the corresponding outputs of the decoder , the information input is connected to the output of the third register, and the inputs are the information outputs of the group, characterized in that it contains an ide the address of the request data of the client, the information input of which is connected to another information output of the second register, the synchronization input is connected to the second synchronizing input of the system, and the control input is connected to the control output of the device for identifying the address of the updated records, the synchronizing input of which is connected to the first synchronizing input of the system, and a unit for generating data reading control signals, the first information and first synchronizing inputs of which are connected to inform respectively, the second information and second synchronizing inputs are connected to the information and synchronizing outputs of the client request data address identification device, respectively, the first and second control inputs of the data reading control signal generation block are the first and second control inputs of the system, the address output is the address output of the system, the first synchronizing output is the first with the system’s synchronizing output, the second synchronizing output is the second system synchronizing output, and the installation output is connected to the installation inputs of the first register and the device for identifying the address of the updated records, while the synchronizing input of the data output channel switching unit is connected to the third synchronizing input of the system, and the installation output is connected to installation input of the third register.