RU56653U1 - RADAR STATION - Google Patents

Abstract

The utility model relates to the field of radar and can be used for lighting with increased stealth of the surface situation in the interests of ensuring navigational safety of navigation and the issuance of target designation data. The objective of the utility model is to expand the functionality of the radar while increasing the noise immunity, information content and reliability of detection in a wide dynamic range of target signals. The essence of the utility model is that a radar station containing an antenna kinematically connected through a rotary connector with an antenna drive, an emitter of signals, a controlled power amplifier, a receiving device, a primary processing device and a secondary processing, control and display device, additionally input protection and amplification device, control unit of the operating modes of the transmitting device, the controller of the communication and control channels and the controller of the antenna drive, this receiving device contains a series-connected amplification block at an ultra-high frequency and double conversion to an intermediate frequency (microwave block), the input of which is connected to the output of the input protection and amplification device, a preliminary amplifier of an intermediate frequency (AMP) and the main amplifier, made with the possibility of manual gain control (RRU) or temporary automatic gain control (VARU) and with the possibility of noise automatic gain control (BAR), as well as the signal conditioning unit is controlled as a receiving device, the primary processing device contains a synchronization and interface unit, a radar processor (RP) of the channel of the circular viewing indicator (IKO) and RP of the channels of the indicator of exact coordinates (ITC) and the target extractor (EC), information outputs and control inputs of which are connected through controllers Ethernet local area network (LAN) with a secondary processing, control and display device through the corresponding LAN backbones, as well as interacting via the information exchange interface channel to a digital receiving device, the input of which is connected to the output of the intermediate frequency signals of the main frequency converter, and a device for generating and processing complex signals, the information output of which is connected via the radar data input line to the inputs of the digital interfaces of the radar processors of the IKO channel and the channels ITK and ETs, interface inputs channel controller outputs

communication and control are connected via the corresponding highways of RS-422 serial channels to a secondary processing, control and display device, to a complex signal generation and processing device, to radar processors of the IKO channel and to the ITK and EC channels, to the synchronization and pairing unit and to the output of the drive controller antennas, the information inputs and outputs of the control signals of which are connected to the antenna drive, and the interface input-output of the control and monitoring signals is connected via a serial line RS-422 channel with a secondary processing, control and display device, in addition, additionally introduced the first and second circulators, a waveguide switch, the antenna input-output of which is connected to the antenna through a rotating connector, and the antenna equivalent channel output is connected to the antenna via the first directional coupler matched load, pulse transmitter, redundant receiver, control and synchronization unit, power attenuation switch, switch control unit and second directional a coupler, wherein the input-output of the signals of the main receive-transmit channel of the waveguide switch through the first circulator is connected to the signal output of the controlled power amplifier and the signal input of the input protection and amplification device, the input-output of the signals of the backup receive-transmit channel through the second circulator is connected to the output power attenuation switch and with the signal input of the backup receiving device, and the control input, to which the signals of setting the waveguide switch to the corresponding The position and the control output of the state signals of the waveguide switch through the control unit of the transmitting device are connected to the corresponding outputs and inputs of the discrete signals of the controller of the communication and control channels, the signal output of the pulse transmitter is connected to the input of the second directional coupler, one output of which is connected to the signal input of the attenuation switch power, and the other with the input of automatic frequency adjustment of the backup receiving device, the control input of the switch power attenuation switch is connected to the output of the control unit by a switch, the inputs of which are supplied by signals specifying the level of attenuation, and the outputs of the control signals are connected to the corresponding outputs and inputs of the control and synchronization unit, which is connected to the controller of the communication and control channels via two RS-422 serial lines , on one of which control and control signals are transmitted, and on the other - codes of the current bearing of the antenna.

Description

The utility model relates to the field of radar and can be used for lighting with increased stealth of the surface situation in the interests of ensuring navigational safety of navigation and the issuance of target designation data.

Known radar stations (radar) [1], pp. 95-105, using simple pulsed signals with high duty cycle and relatively high pulsed power (units and tens of kilowatts per pulse), constructed according to an incoherent scheme - with a transmitter based on a magnetron generator and a receiver superheterodyne type with a local oscillator based on a reflective klystron, the oscillation frequency of which is adjusted manually or using the automatic frequency adjustment circuit (AFC).

The disadvantage of such radars is low noise immunity with respect to natural and organized interference, associated with both low stealth of the probing signals and the impossibility of quickly tuning parameters, primarily the carrier frequency, as well as the impossibility of organizing an operating mode with high coherence.

Known radar [2], which uses signals with intrapulse phase shift keying (FM) with significantly lower duty cycle than pulsed, with lower pulse power and the same pulse energy and allowing random tuning of the carrier frequency from pulse to pulse over a wide range. The known radar is built on a coherent principle and contains a serially connected synchronizer, transmitter, antenna switch and antenna connected to the third arm of the antenna switch, a receiver and an output display device, the transmitter being based on a series-connected pathogen, phase manipulator and power amplifier controlled by a frequency tuner , a code generator and a pulse modulator, respectively, and the receiver contains a high-frequency amplifier that decodes the device the first mixer and the second mixer (phase detector), and the frequency tuning unit is connected to the control input of the pathogen, the code generator is connected to the control inputs of the phase manipulator and the decoding device, the output of the local oscillator frequency of the exciter is connected to the heterodyne input of the mixer, and the output of the reference frequency of the exciter with the input of the reference frequency of the phase detector.

Due to the use of complex FM signals with carrier frequency tuning

from pulse to pulse, this radar has a higher noise immunity and stealth. However, the disadvantage of the radar is the inclusion of a device for compressing FM signals directly behind the high-frequency amplifier, so that the compression of the FM signals in the prototype is performed at the frequency of the received signals, which limits the possibility of its implementation by the relatively short durations of complex signals (up to 10-15 μs).

Another disadvantage of the known radar, which also does not allow the use of FM signals with long pulse durations, is the lack of accounting for both the speed of the ship-carrier radar and the speeds of the detected targets. Meanwhile, as you know, the mutual movement of the radar and the target along the line connecting them leads to a shift in the frequency of the received signals by the Doppler frequency.

In addition, the known radar does not provide for the possibility (to further increase the secrecy of radiation) to reduce the power of probing signals when detecting signals from closely located or highly reflective targets.

A radar is also known [3], which provides adaptation to an interference environment due to the fact that simultaneously with the reception of FM signals reflected from targets, interference in the radio channel is controlled and in case of their high level, the radar carrier frequency is changed with simultaneous reduction of the processed signal flow and threshold correction detection, and beyond the range of the active radio channel, it is used in the passive mode with the conclusion to the indicator of generalized information received in the active and passive modes.

The disadvantage of radar is the lack of compensation for Doppler frequency offset.

The closest analogue adopted for the prototype of the proposed utility model is a radar [4], which implements the radiation of probing signals with low duty cycle and low pulsed power with an in-pulse FM, with adjustable power and pulse duration, with processing of the received FM signals at the video frequency in quadrature channels, compensation for the Doppler frequency shift resulting from the intrinsic speed of the radar carrier in the directions to the observed targets, and the search by Doppler frequency for speed detection purposes.

The prototype radar comprises serially connected synchronizer, transmitter, antenna switch and antenna connected to the third arm of the antenna

an echo signal receiver, the transmitter comprising a series-connected frequency tuner, an exciter, a phase manipulator and a power amplifier, as well as a phase-shift code generator and a pulse modulator, and an echo signal receiver comprising a high-frequency amplifier, a mixer, an intermediate frequency amplifier and connected in series through two lines block phase detectors and a block of video amplifiers, and the output of the intermediate frequency amplifier is connected to the signal input ohm of the phase detector unit, as well as a control unit for processing and displaying information, serially connected control unit, a code-frequency converter, a frequency offset unit and an intra-period processing unit, the exciter reference frequency output being connected to the reference frequency input of the phase detector unit through the unit frequency offsets, information inputs of the control unit are connected, respectively, the first - with the information output of the frequency adjustment unit, the fourth - with the output of the antenna angular position code, and the second the third and third are the input of the input of the own speed of the carrier of the radar station and the input of the speed setting of the detected target, respectively, the outputs of the control signals of the control unit are connected, respectively, the second is connected to the power control input of the power amplifier, the third is connected to the synchronizer input and the block passband control input video amplifiers, the fourth with the antenna drive control input, the fifth with combined switching inputs of the frequency channels of the control unit, processing and from braces, the first and second quadrature outputs of the video amplifier unit are connected to the corresponding inputs of the intra-period processing unit, the signal output of which is connected to the first signal input of the control unit, processing and displaying information, the output of the phase-shift code generator is also connected to the input of the codes of the intra-period processing unit, and the clock outputs the repetition frequencies and pulses of the clock frequency of the synchronizer are also connected to the corresponding inputs of the intra-period processing unit and the unit board, processing and display.

The disadvantage of the prototype radar is the limited ability to reconfigure the parameters of the probing signal, the lack of protection of the receiving path from the penetrating radiation of the transmitting path and gain control devices of the receiving device, as well as the low bandwidth of the information processing devices, which together reduces the reliability of detection and determination

goal settings.

The task to be solved by the utility model is to expand the radar's functional capabilities while increasing the noise immunity, information content and reliability of detection in a wide dynamic range of target signals.

To achieve the claimed technical result, the proposed radar provides the formation of pulsed sounding signals, pulsed phase-shift keyed (IFM) signals and quasi-continuous phase-shift keyed (CPM) signals with tuning of the carrier frequency, FM code and amplitude of the sounding signals, the power amplifier is made two-channel with the ability to adjust parameters and phase control of all cascades of amplification, a controlled input protection and amplification unit is introduced, in the receiving device it is provided as manual, t and a temporary automatic gain (TVG) and the noise level automatic adjustment (ball).

In addition, in the proposed radar, correlation-spectral primary processing of signals at an intermediate frequency is carried out using digital signal processors, and information is processed and processed by a multi-machine digital computer system using standard interfaces and programmable logic integrated circuit (FPGA) technology.

The essence of the utility model is that in the radar station, containing an antenna kinematically connected to the antenna drive, a shaper of radiated signals, a controlled power amplifier, a receiving device, a primary processing device and a secondary processing, control and display device, an input protection device is additionally introduced and amplification, the control unit of the operating modes of the transmitting device, the controller of the communication and control channels and the controller of the drive antenna, while the receiving device contains there is a series-connected amplification block at an ultra-high frequency and double conversion to an intermediate frequency (microwave block), the input of which is connected to the output of the input protection and amplification device, an intermediate frequency preamplifier (IFA) and the main amplifier made with the possibility of manual gain control (RRU) or temporary automatic gain control (VARU) and with the possibility of noise automatic gain control (BAR), as well as a unit for generating control signals of the receiving device primary GUSTs

the processing unit contains a synchronization and conjugation unit, a radar processor (RP) of the channel of the circular viewing indicator (IKO) and RP of the channels of the indicator of exact coordinates (ITC) and the target extractor (EC), information outputs and control inputs of which are connected through external communication modules to the secondary processing device , control and display by means of the corresponding trunks of the local Ethernet network, as well as a digital receiving device interacting via the interface channel of information exchange, the input of which connected to the output signal of the intermediate frequency of the main amplifier, and the device for generating and processing complex signals, the information output of which is connected via the input line of radar data with the inputs of the digital interfaces of the radar processors of the IKO channel and the channels ITK and EC, the outputs of the device for generating and processing complex signals, on which a VARU trigger signal is generated, a BALL gate signal and a blanking signal of the main IF amplifier are connected to the corresponding control units via the synchronization and pairing unit the main inputs of the amplification amplifier, and the output on which the signal of the blanking of the input stages of the amplification of the receiving path is generated is connected via the synchronization and conjugation unit to the corresponding control input of the control signal generation unit of the receiving device, at the corresponding outputs of which blanking pulses are formed, which block the input protection and amplification device and a microwave unit for the duration of the radiation of the probe signal, the control input of the microwave unit by the signal for switching on additional attenuation through the block of the control signals of the receiving device is connected to the corresponding output of discrete signals of the controller of communication channels and control, and the outputs of the controller of communication channels and control, which form the voltage manual gain control, adjust the depth of the gain and adjust the threshold of the ball, the outputs of the discrete shutdown signals of the bar and the ball and input the health signal of the receiving device is connected to the corresponding control inputs and the output of the main amplifier, in addition, the driver of the emitted signals contains it consists of four master oscillators, three frequency conversion units (BFC), an amplification-multiplier cascade, a two-channel frequency multiplier, an amplitude modulation and phase manipulation unit (AM-FM block) and a driver control unit, the output of the first master oscillator being connected through an amplification-multiplier cascade with the first input of the first BPC, the second input of which is connected to the output of the second master oscillator, the first output of the first BPC is connected to the input of the first

a channel of a two-channel frequency multiplier, at the output of which a signal of the first heterodyne frequency is generated, which arrives at the first heterodyne input of the microwave unit, the second heterodyne input of which receives a signal of the second heterodyne frequency from the first output of the fourth master oscillator, the second output of the first LPC is connected to the first input of the second LPC, the second input of which is connected to the first output of the third master oscillator, and the output is connected to the input of the second channel of the two-channel frequency multiplier, the output of which is connected to the input channel of the AM-FM unit, the inputs of the third BPF are connected to the second outputs of the third and fourth master generators, and the output on which the reference frequency signal is generated is connected to the reference input of the digital receiver, the control inputs of the AM-FM unit, to which the intrapulse signals arrive phase manipulation, connected through the synchronization and pairing unit to the corresponding outputs of the device for generating and processing complex signals, the output of the pulse blanking of the shaper of which through the synchronization unit the interface and the driver control unit is connected to the control input of the third master oscillator, the outputs of the synchronization and interface unit, on which the carrier frequency codes are generated, are connected to the corresponding switching inputs of the carrier frequency setting of the first and second master generators and to the corresponding inputs of the driver control unit, to which also connects the outputs of the control signals generated in the AM-FM unit, a two-channel frequency multiplier, a fourth master oscillator and a third LFB, and in the path of the control unit of the shaper, on which the health signal of the shaper is generated, is connected to the corresponding input of discrete signals of the controller of communication channels and control, in addition, the controlled power amplifier contains a preliminary amplifier, the input of which is connected to the signal output of the AM-FM unit, and the output through a diode switch connected to the input of the first transistor terminal amplifier and to the input of the second terminal amplifier, made on a pulse amplification klystron, as well as a pulse mode an amplifier whose output is connected to the modulating input of the second terminal amplifier, a synchronizer, a signal processing unit, a switching and control unit, a power amplifier circulator, a waveguide switch of a power amplifier, a directional coupler with a detector section, and a ferrite switch, the first control input of a diode switch to which a signal is received that controls the switching of channels, is connected to the corresponding output of the switching and control unit, and the second control

input - with the output of the signal processing unit, on which the control current of the attenuator of the diode switch is generated, depending on the carrier frequency code, which is fed to the first input of the signal processing unit from the synchronization and pairing unit through the switching and control unit, to the inputs of the signal processing units from second to the fourth is connected to the control outputs of the envelopes of the signals of the pre-amplifier, the first terminal amplifier and the detector section of the directional coupler, and the second output of the signal processing unit, on which the signals of operability of the input and output of the controlled power amplifier are generated, through the control unit of the transmitting device modes are connected to the corresponding inputs of discrete signals of the communication and control channel controller, the output of the first terminal amplifier is connected to the first input of the waveguide switch of the power amplifier, the second input of which is through the power amplifier circulator connected to the output of the second terminal amplifier, the control input is connected to the corresponding output of the switching and control unit la, and the output is connected through a directional coupler to the detector section with the input of the ferrite switch, the output of which forms the signal output of the controlled power amplifier, and the control input is connected to the output of the switching and control unit, on which the signals of stepwise adjustment of attenuation of the output power are generated, the first synchronizer input is connected with the output of the enable signal of the synchronizer of the switching and control unit, its second input through the synchronization and pairing unit is connected to the output of the device complex signal processing and, on which the driving amplitude modulation signal is generated, and the first synchronizer output, on which the amplitude modulation pulses are generated, is connected through the driver control unit to the amplitude-modulation control input of the AM-FM unit of the emitter of the emitted signals, to the outputs from the second to the fourth synchronizer connected to the synchronization inputs of the pre-amplifier, the first terminal amplifier and the pulse modulator, the inputs of the switching and control unit, which are received at control signals for powering on, turning on the channels of the first or second terminal amplifiers and signals specifying the level of attenuation of the output power, as well as the outputs of the control signals of readiness and status through the control unit of the operating modes of the transmitting device are connected to the corresponding outputs and inputs of discrete signals of the controller of the communication and control channels, the interface inputs and outputs of which are connected by means of the corresponding RS-422 serial trunk lines

with a device for secondary processing, control and display, with a device for generating and processing complex signals, with radar processors of the IKO channel and channels of ITK and ETs, with a synchronization and pairing unit and with the output of the antenna drive controller, on which the codes of the current bearing of the antenna, the controller inputs are generated the antenna drive, which receives information signals from the antenna drive and the outputs of the drive control signals are connected to the corresponding outputs and inputs of the antenna drive, and the interface input-output signal management and control line is connected through a serial RS-422 channel to the secondary processing apparatus, and display control.

In addition, the first and second circulators are added to the radar station, a waveguide switch, the antenna input-output of which is connected to the antenna through a rotating connector, and the antenna equivalent channel output is connected to the matched load through the first directional coupler, a pulse transmitter, a backup receiving device, a unit control and synchronization, power attenuation switch, switch control unit and a second directional coupler, while the input-output of the main the receive-transmit channel of the waveguide switch through the first circulator is connected to the signal output of the controlled power amplifier and to the signal input of the input protection and amplification device, the input-output of the signals of the backup receive-transmit channel through the second circulator is connected to the output of the power attenuation switch and to the signal input of the backup receive devices, and the control input, to which the signals of setting the waveguide switch to the corresponding position, and the control output of the status signals the waveguide switch through the control unit of the modes of the transmitting device is connected to the corresponding outputs and inputs of the discrete signals of the controller of the communication and control channels, the signal output of the pulse transmitter is connected to the input of the second directional coupler, one output of which is connected to the signal input of the power attenuation switch, and the other to the input of the automatic frequency adjustment of the backup receiving device, the control input of the power attenuation switch is connected to the output of the unit The pressure switch whose inputs are the signals that specifies attenuation level, and outputs the control signals are connected to respective inputs and outputs and a synchronization control unit, which is connected with the controller communication channels and control lines through two consecutive RS-422 channels, one of which is transmitted

control and control signals, and, on the other hand, the codes of the current bearing of the antenna, the outputs of the control and synchronization unit, on which the start-up pulses of the transmitter, the radiation pulses and signals for adjusting the duration of the radiation pulse, as well as the inputs to which the blanking pulses of the transmitter and its readiness signals are generated and health, connected to the corresponding inputs and outputs of the pulse transmitter, the outputs of the control and synchronization unit, on which the pulses of blanking the backup receiver devices for the time of emission of probing pulses, VARU start-up pulse, VARU depth and duration adjustment voltage, VARU voltage, manual frequency adjustment signal, switching signal from manual to automatic frequency adjustment, switchgear voltage and switching signal from manual to automatic noise level adjustment, as well as input to which receives the intermediate frequency capture signal, connected to the corresponding control inputs and the control output of the backup receiving device, and the signal output of the backup reception th device on which video pulses formed by the sweep range and the received reflected signals and the output unit managing timing at which pulses are formed by initial reference scan range through the synchronizing unit and the interface are connected to the inputs of analog interface radar PPI channel processors and the CTI and the EC channels.

The essence of the utility model is illustrated by a further description and drawings, which show:

figure 1 is a structural diagram of a radar station,

figure 2 - structural diagram of the shaper of the emitted signals;

figure 3 is a structural diagram of a controlled power amplifier;

figure 4 is a structural diagram of a control unit operating modes of the transmitting device;

5 is a structural diagram of a receiving device;

6 is a structural diagram of a backup receiving device;

7 is a structural diagram of a control and synchronization unit;

Fig. 8 is a structural diagram of a radar processor;

Fig.9 is a structural diagram of a device for generating and processing complex signals;

figure 10 is a structural diagram of a controller of communication channels and control;

11 is a structural diagram of an antenna drive controller;

12 is a block diagram of a secondary processing, control, and display device.

In figure 1, the following notation:

1 - antenna, made in the form of a mirror antenna with a paraboloid reflector. A pyramidal horn powered by a rectangular waveguide was used as an irradiator;

2 - antenna drive,

3 - rotating connector,

4 - waveguide switch, made in the form of an electromechanical device in which two unconnected waveguide channels are formed, connecting four waveguide inputs and outputs of the switch in pairs. Bringing the switch to the selected state, in which one (main or backup) receive-transmit channel is connected to the antenna and the other is automatically connected to the matched load acting as an antenna equivalent, is supplied by ± 27 V to the corresponding contacts of the low-frequency switch connector;

5 - matched microwave load (antenna equivalent);

6, 7 - the first and second circulators, respectively,

8 - the first directional coupler,

9 - shaper of the emitted signals (hereinafter referred to as shaper), a detailed structural diagram of which is presented in figure 2;

10, 11, 12, 13 - the first, second, third, fourth master oscillators, respectively,

14 - amplification and multiplication cascade,

15, 16, 17 - the first, second, third frequency conversion blocks (BFC), respectively,

18 - two-channel frequency multiplier,

19 is a block of amplitude modulation and phase shift keying (AM-FM),

20 - control unit shaper,

21 is a controlled power amplifier, the structural diagram of which is presented in figure 3;

22 - control unit of the operating modes of the transmitting device (hereinafter referred to as the mode control unit), the structural diagram of which is presented in Fig.4;

23 - input protection and amplification device, which is both a low-noise amplifier and a device for protecting the receiver from penetrating pulses from the output of a controlled power amplifier 21. The device includes a cyclotron protective device (CZU), a low-noise microwave amplifier (LNA) with a built-in controlled attenuator, and a LNA power supply. The cyclotron protective device is a low-noise electrostatic amplifier based on the cyclotron resonance of the electron beam, the principle of which, the structural diagram and calculation of the characteristics are given in [5].

24 - receiving device (PU), a detailed structural diagram of which is presented in figure 5;

25 - microwave amplification unit and double conversion to an intermediate frequency, hereinafter referred to as the microwave unit;

26 - pre-amplifier intermediate frequency (UPCH),

27 - the main OCHR,

28 is a unit for generating control signals of the receiving device,

29 is a block of secondary power sources (IVEP) of the receiving device,

30 - block switching control signals (PKS),

31 - noise generator

32 - IVEP backup transceiver device,

33 - pulse transmitter,

34 - backup receiving device, a structural diagram of which is shown in Fig.6,

35 - the second directional coupler,

36 - power attenuation switch, made in the form of a ferrite switch;

37 - control unit switch

38 - control unit and synchronization, the structural diagram of which is presented in Fig.7;

39 - primary processing device,

40 - block synchronization and pairing,

41 - radar processor (RP) channel circular viewing indicator (PPI), a structural diagram of which is shown in Fig.8,

42 - radar channel processor indicator of the exact coordinates (ITC) and the target extractor (EC), made similar to RP IKO,

43, 44 - controllers of a local area network (LAN) Ethernet,

45 is a digital receiving device (CPU),

46 is a device for generating and processing complex signals (FOS), the structural diagram of which is shown in Fig.9;

47 is a controller of communication and control channels, the structural diagram of which is shown in FIG. 10;

48 is an antenna drive controller, the structural diagram of which and the generalized structural diagram of the antenna drive 2 are shown in FIG. 11;

49 - a device for secondary processing, control and display, a structural diagram of which is shown in Fig 12;

M1, ..., M7 - lines of serial channels RS-422 (hereinafter - lines of serial channels),

M8 - the highway of the digital 14-bit specialized interface for entering radar data (hereinafter referred to as the highway for entering radar data),

E1, E2 - Ethernet LAN backbones.

According to figure 1, the signal input-output of the antenna 1 through a rotary connector 3, kinematically connected with the electromechanical drive 2 of the antenna, is connected to the second (antenna) input-output of the waveguide switch 4, the third output (channel of the antenna equivalent) of which is connected through a directional coupler 8 to matched load 5. The second output of the directional coupler 8 in the functional control mode of the radar is connected through a waveguide-coaxial junction and a coaxial cable with a delay line of the reflective type (LZ), distributed Proposition 24 in the receiving device.

The first input-output (main transceiver channel of the radar) of the waveguide switch 4 through the first circulator 6 is connected to the signal output of the controlled power amplifier 21 and to the signal input of the input device 23 of protection and amplification. The fourth input-output (backup transceiver channel of the radar) of the waveguide switch 4 through the second circulator 7 is connected to the output of the power attenuation switch 36 and to the signal input of the backup receiver 34, and the control input of the waveguide switch 4 by the channel switching signal and the control signal output of the waveguide switch (indicated by one two-way communication line) are connected to the corresponding output and input of the mode control unit 22.

The composition of the base transceiver channel radar includes driver 9 radiated signals, signal output «f _c" is connected to the signal input of a controlled amplifier 21, the power mode control unit 22 and input device 23, the protection and amplification, to the output of which is connected to the signal input "microwave Rin. "Receiving device 24.

The inputs of the controlled power amplifier 21, which receive the control signal to turn on the power of the main (complex) transceiver channel of the radar ("Channel Slave On"), turn on signals of the first or second amplification channel ("On channel 1", "Prev. on channel 2 "," On channel 2 ") and signals that establish the level of attenuation of the output power (" Slack 10 dB "," Slack 20 dB "), as well as the control signal outputs of the state of the controlled power amplifier 21 ( indicated by one two-way communication line) connected to the respective outputs and inputs of the control unit 22 modes, and the inputs to which the carrier frequency code “LF ₁ ”, ..., “LF ₇ ” and the amplitude modulation signal “AM2” are connected are connected to the corresponding outputs of the synchronization and pairing unit 40, which is part of the primary device 39 processing.

The output of the mode control unit 22, on which the “Channel Imp. On” signal is generated to turn on the power of the backup (pulse) transceiver channel of the radar, is connected to the input of the IEPP 32 of the backup transceiver and to the ± 27 V power supply inputs of the pulse transmitter 33 and backup receiving device 34. To the corresponding outputs of the IVEP 32, on which direct current voltages of various ratings are formed (indicated by a single communication line), the power inputs of the power attenuation switch 36, control unit 37 are connected eklyuchatelem unit 38 and the control and synchronization.

The input of the mode control unit 22, to which the corresponding control signals are received by a serial eight-digit code, as well as the synchronization, read and write inputs, and the control signal outputs (indicated by a single two-way communication line for simplicity) are connected, as will be shown below, with the corresponding discrete outputs and inputs signals of the controller 47 communication and control channels.

The structure of the shaper 9 of the emitted signals, a more detailed structural diagram of which is shown in figure 2, includes four master oscillators 10, ..., 13, three frequency conversion blocks 15, 16, 17, block 19 AM-FM, amplification multiplier cascade 14, a dual-channel frequency multiplier 18 and a control unit 20

shaper.

The inputs of the first and second master generators 10, 11, forming the switching inputs of the carrier frequency setting of the driver 9, as well as the corresponding control inputs of the driver control unit 20, are connected to the outputs of the synchronization and interface unit 40, on which the carrier frequency codes from first to fourth (LF ₁ , ... LF ₄ ) and codes of the carrier frequency from the fifth to the seventh (LF ₅ , LF ₆ , LF ₇ ).

The output of the first master oscillator 10 through the amplification multiplier stage 14, in which the frequency is multiplied by 8, is connected to the first input of the first BPC 15, the second input of which is connected to the output of the second master oscillator 11.

The first output of the first BCH 15 is connected to the input of the first channel of the two-channel frequency multiplier 18, the input of the second channel of which is connected to the output of the second frequency conversion unit 16, the first and second inputs of which are connected respectively with the second output of the first BPC 15 and with the first output of the third master oscillator 12.

The output of the first channel of the two-channel multiplier 18, on which the signal of the first heterodyne frequency is generated (f _ГЕТ1 ), is connected to the first heterodyne input of the block 25 of the microwave receiver 24, the second heterodyne input (f _ГЕТ2 ) of which is connected to the first output of the fourth master oscillator 13.

The output of the second channel of the two-channel frequency multiplier 18, on which the carrier frequency signal is generated, is connected to the signal input of the AM-FM unit 19, the control inputs of which, according to the signals "F1", "F2" of intrapulse phase shift keying (in Fig. 1, are indicated by one communication line " F1, F2 ") are connected to the corresponding outputs of the synchronization and conjugation unit 40, and the amplitude modulation control input, to which the AM2-1 sequence of amplitude modulation pulses arrives, is connected to the corresponding m output amplifier 21 power-managed, capable of forming an aforementioned pulses corresponding to drive signals "AM2" amplitude modulation originating from a synchronization unit 40 and interface. The output of the block 19 AM-FM forms a signal output "f _with " the shaper 9 of the emitted signals.

The inputs of the third block 17 of the frequency conversion are connected respectively to the second outputs of the master oscillator 12 and the master oscillator 13, and its output,

forming the output signal "f _op " the reference frequency of the shaper 9, is connected to the reference input of the digital receiving device 45.

The control input of the third master oscillator 12, to which the shaper blanking pulses “H” are supplied during the operation of the receiving path, is connected through the shaper control unit 20 to the corresponding output of the synchronization and pairing unit 40.

The output of the AM-FM block 19, on which the control signal “f _c-k ” is generated, as well as the outputs of the two-channel frequency multiplier 18, the fourth master oscillator 13 and the third frequency conversion unit 17, on which the control signals “f _ГЕТ1-К ” are respectively generated , “F _Get2-K ” and “f _OP-K ”, are connected to the corresponding inputs of the driver control unit 20, and the output of the unit 20, on which the generalized signal “Repair form” of the health of the driver is generated, is connected to the corresponding input of discrete controller signals 47 communication channels and board.

The signal input of the receiving device 24 is the input of the microwave unit 25, the output of which is connected through a preliminary UPCH 26 to the signal input of the main UCH 27.

The output of the main amplifier 27, on which the received reflected signals are generated at an intermediate frequency (“IF2”), is connected to the signal input of a digital receiving device 45, which is structurally designed as a mezzanine module of the device 46 for generating and processing complex signals and is connected with it by an information exchange channel based on a specialized digital interface.

The output of the main UCH 27, where during the functional control of the pulse operating modes of the radar the video pulses “VIa” of the scan along the distance of the reflected signals are generated, is connected through the synchronization and interface unit 40 to the inputs of the analog interfaces of the radar processor 41 channel of the circular viewing indicator and radar processor 42 channel of the indicator exact coordinates and extractor targets. The inputs of the digital specialized interfaces of the radar processors 41, 42 via the M8 line for inputting radar data are connected to the information output of the device 46 for generating and processing complex signals, and the inputs of the interfaces of the serial channels are connected to the controller 47 of the communication and control channels via the M2 highway, which transfers 12-bit code of the current bearing of the antenna.

The information outputs and control inputs of the radar processors 41, 42 via Ethernet LAN controllers 43, 44 are connected via LAN lines E1 and E2 to the secondary processing, control and display device 49, which is connected via RS-422 serial channels M5 and M7, respectively, to controller 47 communication and control channels and with the controller 48 of the drive of the antenna, and the controller 48 of the drive of the antenna is connected to the controller 47 of the channels of communication and control via line M6 of the serial channel RS-422.

The interface inputs and outputs of the RS-422 serial channels of the synchronization and pairing unit 40 and the complex signal generation and processing device 46 are connected to the communication and control channel controller 47 via the RS-422 serial channels M3 and M4.

The control input of the control signal generation block 28 of the control unit, to which the “Blank” signals of blanking the microwave amplification stages of the receive path are received, is connected to the corresponding output of the synchronization and conjugation block 40, the outputs of which are by the blanking signals of the main amplifier (“BI”), the ballast gate («) The STBU gate ”) and the VARU start (“ IZV ”- the VARU start pulse) are connected to the corresponding inputs of the main UCH 27.

The outputs of the control unit 28 for generating control signals of the control unit, on which the signals “Form 1”, “Form 2” are generated, are connected to the blanking input of the cyclotron protective device and to the blanking input of the microwave LNA (disconnecting its power source) of the input device 23 protection and amplification, and the output on which the signal “UHF Form” is generated is connected to the blanking input of the microwave unit 25.

The inputs of the synchronization signals “SI”, the gating of the recording “Strobe Rec.” And the control input of the control signal generation block 28, to which the attenuator control signal of the input device 23, the signal “DO” of additional attenuation enable, attaches an attenuator, a signal The “FC” for switching on the functional control mode and the “On GSh” signal for turning on the noise generator are connected to the corresponding discrete outputs of the controller 47 of the communication and control channels.

The output of the control unit for generating control signals of the control unit, on which the control signals of the attenuator “AttrAtt.” Are generated, is connected to the corresponding control input of the LNA of the microwave input protection and amplification device 23, the output on which the additional attenuation signals “DO (Us)” are generated, connected to

the corresponding control input of the microwave unit 25, and the output on which the noise generator “On GSh” signal is generated is connected, as will be shown below, to the control input of the power supply current stabilizer of the noise generator, which is part of the IWEP unit 29 of the receiving device 24 and the feeding the voltage to the noise generator 31, which in the functional control mode is connected to the signal input of the input device 23 protection and amplification instead of the output of the antenna path.

The input of the control signals of the preliminary amplifier 26 is connected to the output of the control signal switching unit 30, the control input of which is connected to the corresponding output of the discrete signals of the controller 47 of the communication and control channels by the signal “On Immit.” And the signal input to which the control signals intermediate frequency "IF (KS)" is connected to the corresponding output of the digital receiving device 45.

The output of the “Repair PMR” signal of the operability of the receiving device, which is formed at the control output of the main control unit 27, is connected to the corresponding input of the discrete signals of the controller 47 of the communication and control channels, the outputs of the discrete signals are “Open SHARU”, “Off Var.” And “Signal 1 ”(switching the bandwidth of the video amplifier) which, as well as the outputs of the analog signals of manual gain control (“ RRU ”), threshold adjustment of the BALL (“ P-BALL ”) and the depth adjustment of the BAR (“ BAR-G ”), are connected to the corresponding inputs main UHF 27.

The output of the pulse transmitter 33, which is part of the backup transceiver device, is connected to the input of a directional coupler 35, the first output of which is connected to the input of the power attenuation switch 36, and the second to the input of the automatic frequency control (AFC) of the backup receiver 34. Control inputs of the switch 36 power attenuation by the signals “0Р”, “1Р”, setting the level of attenuation of the output power, and the outputs of the control signals “0РК”, “1РК” (indicated by one communication line) are connected to the corresponding passages and input unit 38 and the synchronization control connected arteries M1, M2 serial RS-422 channel to the controller 47 and the control communication channels. Control and control signals are transmitted along the M1 highway, and a 12-bit code of the current antenna bearing is transmitted along the M2 highway.

The outputs of the control and synchronization unit 38, on which the “IZP” transmitter trigger pulse, the “IZL” radiation pulse, and the duration adjustment signals “RD1”, “RD2” of the probe signal, are connected to the corresponding

the inputs of the pulse transmitter 33, the outputs of the blanking pulses "BIP" which, as well as the outputs of the control signals of readiness "Got." and serviceability "Isp." are connected to the corresponding inputs of the block 38 of the control and synchronization.

The outputs of the control and synchronization unit 38, on which the receiver blanking pulses (“Blank”), the VARU start pulses (“VZV”), the VARU shutdown signal, and other control signals of the receiving device, as will be shown below, are connected to the corresponding inputs of the backup receiving device 34, the control output of which is connected to the corresponding input of the control and synchronization unit 38 by the intermediate frequency capture signal “IF Capture."

The outputs of the backup receiving device 34, on which the scan video pulses are generated by the distance of the received reflected signals ("Video-R"), as well as the outputs of the control and synchronization unit 38, on which the "NOD-R" pulses of the initial scan range count and pre-emptive start pulses are formed "UIZP" connected to the corresponding inputs of block 40 synchronization and pairing.

The information outputs of the electromechanical drive 2 of the antenna, on which the signals q _a and q of the _two angular positions of the antenna and the rotor of the electric motor are generated, and its inputs of the drive control signals are connected to the corresponding inputs and output of the antenna drive controller 48.

Shaper 9 emitted signals provides the formation of the carrier frequency of the emitted signals, which is performed by direct synthesis at one of 12 operating points depending on the control signals of the code of the carrier frequency (LF ₁ ..., LF ₇ ), the formation of the output "f _with " depending from the selected (one of three) radiation regimes defined by the AM2-1 modulating pulses and the F1, F2 signals of the intra-pulse phase shift keying or a sequence of simple pulse signals (IMP), or a sequence of single phase pooled pulses (IMP) or quasi-continuous PSK signals (SPS) and forming at respective outputs signals with a frequency of the first and second local oscillators ( «f _{Het 1»,} «f _GET2") and the reference frequency signal «f _OP".

Figure 2 of the structural diagram of the shaper 9 of the emitted signals adopted the following notation:

KG ₁ , ..., KG ₉ - crystal oscillators from first to ninth, respectively,

DM ₁ , ..., DM ₉ - diode modulators from first to ninth, respectively,

DKm ₁ , DKm ₂ - the first and second diode switches, respectively,

M ₁ , ..., M ₅ - modulators from first to fifth, respectively,

At ₁ , ..., At ₉ - amplifiers from first to ninth, respectively,

BU ₁ , ..., BU ₉ - balanced amplifiers from first to ninth, respectively,

CM ₁ , cm ₂ , cm ₃ - the first, second, third mixers, respectively,

HO ₁ , HO ₂ , HO ₃ - the first, second, third directional couplers, respectively,

B ₁ , B ₂ - the first and second valves, respectively,

Pr ₁ , Pr ₂ , Pr ₃ - the first, second, third amplifiers-converters designed to convert input pulse signals of a logic level into bipolar currents and voltages,

Usk ₁ , Usk ₂ , Usk ₃ - the first, second, third accelerators that accelerate the recharge of the input capacitance of the microwave diodes during the decay of the output pulses and, accordingly, reduce the switching time of the phase manipulator and diode switch,

FM - phase manipulator,

PF - band-pass filter,

Det - transistor detector

x2 - frequency multipliers by 2,

x3 - frequency multipliers by 3,

x4 - frequency multipliers by 4,

50 - block threshold voltage control, including four threshold devices made on operational amplifiers and comparators. The threshold voltage setting for the monitored signals is carried out by resistors. If the amplitude of the monitored signal exceeds a threshold voltage, a signal with a logic level of “1” is generated at the output of the corresponding threshold device.

51 - block logical signal processing, designed to control the presence of signal code carrier frequency ("LF ₁ , ..., LF ₇ "). The block is made on the basis of Schmidt triggers, generators, and logic elements I. In the absence of one of the controlled control signals, the signal “Absent SS” is generated at the output of the block, and if the input signal code is forbidden, the signal “SS failure” is generated.

52 - control unit for the presence of a blanking signal "H", made on the basis of the Schmidt trigger, generator and output inverter. If there is an input signal at the inverter output, the signal “Corr. H” is generated. In addition, the block contains an isolation element, the output of which forms the broadcasting output of the signal “H” of the block.

53 - the control unit for the presence of the amplitude modulation signal "AM2-1", performed similarly to block 52. In the presence of the input signal "AM2-1", the signal "AM2-1" is generated at the transmitting output of the block, and "Fix AM2" at the control.

54 is a block for generating a generalized health signal based on logic elements.

According to the scheme of figure 2, the first master oscillator 10 contains four chains of series-connected crystal oscillator KG ₁ (KG ₂ , KG ₃ , KG ₄ ), a diode modulator DM ₁ (DM ₂ , DM ₃ , DM ₄ ) and a frequency multiplier by 4 the output of which is connected to the corresponding signal input of the first diode switch DKm ₁ .

The inputs of the first and second modulators M ₁ , M ₂ connected to the inputs from the first to the fourth block 51 of the logical signal processing, form the switching inputs of the installation of the carrier frequency signals LF ₁ , LF ₂ and LF ₃ , LF _{4 of the} first master oscillator 10 and shaper 9 radiated signals.

The first and second outputs of the first modulator M _{1 are} connected to the control inputs of the first and second diode modulators DM ₁ and DM ₂ , and the third and fourth outputs are connected to the first and second control inputs of the diode switch DKm ₁ .

The first and second outputs of the second modulator M _{2 are} connected to the control inputs of the third and fourth diode modulators DM ₃ and DM ₂ , and the third and fourth outputs are connected to the third and fourth control inputs of the diode switch DKm ₁ .

A broadband amplifier-multiplier chain is connected to the output of the DKm ₁ diode switch, consisting of a 2-frequency multiplier connected in series, an amplifier U ₁ and a PF bandpass filter, the output of which is connected to the input of the amplifier-multiplier stage 14, which consists of two frequency multipliers connected in series 2, the balanced amplifier BU _1, a frequency multiplier is 2 and the _two balanced amplifier BU, whose output is connected to the first input of the first mixer See ₁ which is the first input of the first block 15, n eobrazovaniya frequency.

The second master oscillator 11 contains three chains of series-connected crystal oscillator KG ₅ (KG ₆ , KG ₇ ), a diode modulator DM ₅ (DM ₆ , DM ₇ ) and a frequency multiplier by 4, the output of which is connected to the corresponding signal input of the second diode switch DKm ₂ .

The inputs of the third modulator M ₃ connected to the fifth and sixth inputs of the block 51 of the logical signal processing, form the switching inputs of the installation of the carrier

frequency signals LF ₅ , LF ₆ , and the input of the fourth modulator M ₄ connected to the seventh input of the block 51 of the logical signal processing, forms the switching input of the installation of the carrier frequency signal LF ₇ .

The outputs of the block 51 of the logical signal processing, on which, in the absence or failure of the control signals of the carrier frequency code, the signals “Absent” and “Failure” are generated, are connected to the corresponding inputs of the unit 54 for generating a generalized health signal.

The first and second outputs of the third modulator M _{3 are} connected to the control inputs of the fifth and sixth diode modulators DM ₅ and DM ₆ , and the third and fourth outputs are connected to the first and second control inputs of the second diode switch DKm ₂ .

The first output of the fourth modulator M _{4 is} connected to the control input of the seventh diode modulator DM ₇ , and the second to the third control input of the second diode switch DKm ₂ .

A broadband amplifier-multiplier chain is connected to the output of the second diode switch DKm ₂ , consisting of a series-connected frequency multiplier by 2 and amplifier U ₂ , the output of which is through amplifier U ₃ , the input of which forms the second input of the first frequency conversion unit 15, connected to the second input of the first mixer cm ₁ at the output of which a signal is generated with a frequency equal to the frequency difference of the input signals of the frequency conversion unit 15. A two-stage balanced amplifier (BU ₃ , BU ₄ ) is connected to the output of the mixer Cm ₁ with an output power divider at the second amplification stage, the outputs of which form the first and second outputs of the first frequency conversion unit 15.

The first output of the first frequency conversion unit 15 is connected to the input of the first channel of the two-channel frequency multiplier 18, which is the input of one of the frequency multipliers by 2, the output of which through the balanced amplifier BU _{7 is} connected to the input of the directional coupler HO ₁ with the detector section. The first output HO ₁ forms the output of the first channel of the two-channel multiplier 18, on which the signal of the first heterodyne frequency "f _ГЕТ1 " of the _driver 9 is generated, and the second output HO ₁ , which forms the output of the control signals "f _ГЕТ1-К ", is connected to the corresponding input of the threshold block 50 voltage control, which is part of the block 20 control shaper.

The third master oscillator 12 is based on the eighth quartz oscillator KG ₈ , the output of which is connected through a frequency multiplier by 3 to the signal

the input of the eighth diode modulator DM ₈ , the output of which is connected to an amplifier-multiplier chain, consisting of two series-connected frequency multipliers by 2 and amplifier U ₄ , the output of which forms the first output of the third master oscillator 12.

The control input of the diode modulator DM _{8 is} connected to the output of the fifth modulator M ₅ , the input of which is connected to the transmitting output of the block 52 for monitoring the presence of the blanking signal "H".

In addition, the output of the eighth quartz oscillator KG ₈ through the amplifier U ₅ , the output of which forms the second output of the third master oscillator 12, is connected to the first input of the third frequency conversion unit 17, which is formed by the input of the multiplier chain from the series-connected frequency multiplier by 3 and the frequency multiplier by 2, the output of which is connected to the first input of the third mixer cm ₃ .

The fourth master oscillator 13 is based on the ninth quartz oscillator KG ₉ , the output of which is connected to an amplification-multiplier chain, consisting of a series-connected frequency multiplier by 4, a frequency multiplier by 2, amplifier U ₆ and a frequency multiplier by 2, the output of which is connected to the input second directional coupler HO ₂ . The first output of the directional coupler HO ₂ forms the output of the signal “f _HET2 ” of the second heterodyne frequency of the _driver 9, and the second output HO ₂ , on which the control signal “f _HET2-K ” is _generated , is connected to the corresponding input of the threshold voltage monitoring unit 50.

In addition, the input of the amplification-multiplier chain consisting of an amplifier U ₇ , a frequency multiplier by 4 and an amplifier U ₈ , the output of which, forming the second output of the fourth master oscillator 13, is connected to the second input of the third mixer, is connected to the output of the ninth crystal oscillator KG _{9 3} , forming the second input of the third frequency conversion unit 17.

To the output of the mixer cm ₃ , on which a signal is generated with a frequency equal to the sum of the frequencies of the input signals, an amplifier-multiplier chain is connected from a frequency multiplier by 4 and amplifier U ₁₀ , the output of which forms the output of the signal “f _OP ” of the reference frequency of the former 9. To the second the output of the amplifier U _{10 is} connected to a transistor detector (Det), the output of which, forming the control output "f _OP-K " of the third frequency conversion unit 17, is connected to the corresponding input of the threshold voltage monitoring unit 50.

The first output of the third master oscillator 12 through the amplifier U ₉ , the input of which

forms the second input of the second frequency conversion unit 16, connected to the second input of the second mixer Cm ₂ , the first input of which (and the first input of the unit 16) is connected to the second output of the first frequency conversion unit 15. A two-stage balanced amplifier (BU ₅ , BU ₆ ) is connected to the output of the second mixer, cm ₂ , on which a signal is generated with a frequency equal to the sum of the frequencies of the input signals, the output of which is connected to the input of the second channel of the two-channel frequency multiplier 18, including a second frequency multiplier by 2 and a two-stage balanced amplifier (BU ₈ , BU ₉ ), the output of which, forming the output of the second channel of the two-channel frequency multiplier 18, is connected to the signal input of the AM-FM block 19, formed by the input of the first valve B ₁ , the output of which is connected to the main input of the phase manipulator (FM).

The output of the phase manipulator through a series-connected ninth diode modulator DM ₉ and a second valve B _{2 is} connected to the input of the third directional coupler HO ₃ . The first output of HO ₃ forms the signal output “f _s ” of the driver 9, and its second, control, output (“f _s-k ”) is connected to the corresponding input of the threshold voltage monitoring unit 50.

Block 19 AM-FM contains three nodes converting control signals, each of which consists of a series-connected amplifier-converter Pr ₁ , (PR ₂ , Pr ₃ ), the input of which forms the input of the corresponding control signal of block 19 AM-FM, and accelerator Usk ₁ (Usk ₂ , Usk ₃ ). The input of the first amplifier converter Pr _{1 is} connected to the transmitting output of the amplitude control signal presence control unit 53 "AM2-1", and the inputs of the second and third amplifier converters Pr ₂ and Pr ₃ form the control inputs of the former 9 according to the in-phase phase shift signals "F1" and "F2". The output of the first accelerator Usk _{1 is} connected to the control input of the ninth diode modulator DM ₉ , and the outputs of the second and third accelerators Usk ₂ and Usk ₃ are connected to the control inputs of the phase manipulator FM.

The outputs of blocks 52, 53, which are formed on the serviceability of the signals "Ispr.Ch""Ispr.AM2", and block 50 outputs a threshold control voltages which are generated signals "Ispr.f _ck", "Ispr.f _{Het 1"} "Repair Img .f _get2 ”“ Corr.f _op ”is connected to the corresponding input of the generalized health signal generating unit 54, the output of which forms the output of the“ Corr.form. ”health condition of the emitter 9 of the emitted signals.

Guided power amplifier 21 for terminal amplification

the power of the output signals of the shaper 9 and transmitting them to the antenna path, is a complex multifunctional device containing electric vacuum and semiconductor microwave amplifiers, secondary low-voltage and high-voltage power supplies, a semiconductor pulse modulator, waveguide and ferrite elements, a synchronizer, signal processing, control and monitoring units . The units of the device are interconnected by waveguides, coaxial cables, low-frequency cables and are located on the heat sink base - a segmented plate. For heating structural elements that are not in contact with the base plate, there are intermediate heat-dissipating racks made of materials that are well heat-dissipating, which are simultaneously used to fasten the nodes and ensure the rigidity of the structure as a whole.

In figure 3 of the structural diagram of a controlled power amplifier 21, the following notation:

55 - transistor pre-power amplifier (hereinafter referred to as pre-amplifier);

56 - diode switch with controlled attenuator on pin diodes (hereinafter - diode switch);

57 - transistor terminal power amplifier (hereinafter referred to as the first terminal amplifier);

58 - the second terminal power amplifier, made on a pulse amplification klystron (hereinafter referred to as the second terminal amplifier);

59 is a synchronizer that provides the formation and timing in the necessary sequence of trigger pulses for all amplification stages, as well as the formation of amplitude modulation pulses (AM2-1) for the operation of the shaper 9;

60 is a signal processing unit for generating control currents for a pin attenuator of a diode switch depending on a code value of a carrier frequency, as well as generating health signals from envelopes of output signals of respective amplification stages;

61 is a switching and control unit containing switching elements providing for the inclusion of the units included in the controlled power amplifier 21, depending on external control signals, the inclusion of power supplies, the blocking of the inclusion of devices, as well as the delay circuit, protection and control circuits for current supply bias control circuit high voltage control circuit

and three temperature control circuits (base plate and terminal power amplifiers);

62 - pulse modulator

63 is a block of high-voltage power supplies, consisting of separate power supplies with independent stabilization for powering the elements of a pulse modulator and klystron,

64 - power amplifier circulator (UM circulator),

65 is a waveguide switch of the PA, carrying out the corresponding connection of the output waveguide microwave path to the first or second terminal power amplifiers;

66 - directional coupler with a detector section, forming the envelope of the output signal to control the health of the output;

67 - ferrite switch that performs step adjustment of the output microwave power,

68, 69 - the first and second matched loads of PA,

70 is a block of secondary power supplies, including low-voltage power supplies of various ratings, necessary for the operation of the respective blocks of a controlled power amplifier 21.

According to figure 3, the signal input of the controlled power amplifier 21, which receives the signal "f _with " generated at the output of the block 19AM-FM, is the input of the pre-amplifier 55, the output of which is connected through the diode switch 56 to the input of the first terminal amplifier 57 and to the input the second terminal amplifier 58, the modulating input of which is connected to the output of the pulse modulator 62.

The first control input (based on the “Control PC” signal of channel switching) of the diode switch 56 is connected to the first output of the switching and control unit 61, and the second control input is connected to the first output of the signal processing unit 60, on which the control current of the attenuator of the diode switch 56 is generated depending on the code of the carrier frequency "Code f", which is supplied to the first input of the signal processing unit 60 from the second output of the switching and control unit 61.

The second and third and fourth inputs of unit 60, signal processing connected to the control outputs of the envelopes preamp signal 55 (U _OG. PU), the first terminal of the amplifier 57 (U _OG. OU1) and the detector section of the directional coupler 66 (U _OG. DU), and the second output of block 60, on which

signals of serviceability of the input and output ("Correct input" and "Correct output"), forms the same output of the controlled power amplifier 21.

The output of the first terminal amplifier 57 is connected to the first input of the waveguide switch 65, the second input of which through the circulator 64, is connected to the output of the second terminal amplifier 58, and the control input is connected to the third output of the switching and monitoring unit 61 by the signal “Upr.”. The first matched load 68 is connected to the third arm of the circulator 64. The output of the waveguide switch 65 through a directional coupler 66 is connected to a ferrite switch 67, the first output of which forms the signal output of the controlled power amplifier 21, the second output is connected to the second matched load 69, and the control the input is connected to the fourth output of the switching and control unit 61, on which the signals “Slack 10 dB”, “Slack 20 dB” of step adjustment of attenuation of the output power are generated.

The high-voltage power inputs of the pulse modulator 62 and the second terminal amplifier 58 are connected to the corresponding outputs of the high-voltage power supply unit 63, the control input of which is connected to the fifth output of the switching unit 61 by the signals “Pre-On” and the high-voltage switch “Vkp.VN” and control.

The first input of the synchronizer 59 is connected to the sixth output of the switching and control unit 61, on which the synchronizer enable signal is generated, its second input, to which the amplitude modulation signal AM2 is supplied from the synchronization and conjugation unit 40, and the first output, on which the pulses are generated amplitude modulation "AM2-1" for the shaper 9 of the emitted signals, form the same input and output of the controlled power amplifier 21. The outputs of the second to fourth synchronizer 59 are connected to the synchronization inputs of the pre-amplifier 55, the first terminal amplifier 57 and the pulse modulator 62.

The first input of the switching and control unit 61 is a connector for receiving external control signals “On Channel 1” (to enable the channel of the first terminal amplifier), “Pre-On Channel. 2 "(preliminary switching on the channel of the second terminal amplifier)," On channel 2 "(turning on the second channel)," Slack 10 dB "," Slack 20 dB "coming from the mode control unit 22, as well as the frequency codes" LF1, ..., LF7 ”coming from the block 40 synchronization and pairing.

The second input of the block 61 switching and control, which receives a signal

"Chan. On.", Forms the power input of a controlled power amplifier 21. The input voltage ± 27 V through block 61 is fed to the input of block 70 of secondary power sources, which generates voltages of various ratings for power amplifiers 55, 57, as well as to the input of block 63 of high-voltage power sources.

The third input of the switching and control unit 61 is connected to the control signal output of the high-voltage power supply unit 63, and the seventh output is the output connector of the power amplifier 21, on which the control signals “Channel 2” are generated (readiness of the second channel), “VN On . ”(High voltage on),“ Overheating ”, Rt (temperature control signal of the base plate of the controlled power amplifier).

The control unit 22 of the operating modes of the transmitting device delivers a supply voltage of ± 27 V to the controlled power amplifier 21 and the backup transceiver device, generates control signals for the controlled power amplifier 21 and receives control signals from it, generates control signals for switching the waveguide transmission and reception radar channels with using the waveguide switch 4 and monitoring its position.

Figure 4 of the structural diagram of the block 22 control the operating modes of the transmitting device adopted the following notation:

71 - shaper input signals

72 - serial to parallel converter,

73 - decoder input signals

74 - address decoder,

75 - driver output signals,

76 - block amplification and conversion of signals Rt temperature control (hereinafter referred to as block amplification and conversion of signals),

77 - the register of the first word,

78 - the register of the second word,

79 is the first encoder,

80 - the second encoder,

81 - transistor switch,

82 - phase inverse cascade,

83 - block switching waveguide switch,

84 - decoupling cascade,

M ₁ , ..., And ₂₂ - elements And from the first to the twenty second, respectively,

OR ₁ , ..., OR ₇ - OR elements from first to seventh, respectively,

GP ₁ , ..., GR ₁₂ - cascades of galvanic isolation from the first to twelfth, respectively,

Cl ₁ , ..., Cl ₇ are the key cascades from the first to the seventh, respectively.

The first input of the input signal generator 71 forms a signal input of the mode control unit 22, to which the following signals are received by a serial eight-bit code from the controller 47 of the communication and control channels:

1p - turn on the power of the pulse (backup) channel,

2p - turn on the power channel complex (main),

3p - increased readiness (Pow.Goth.),

4p - attenuation of 1p (Osl. 1p),

5p - attenuation of 2p (Osl. 2p),

6p - attenuation of 3p (Osl. 3p),

7p - channel antenna-equivalent 1p (Channel Ant.1p),

8p - channel antenna-equivalent 2p (Can. Ant.2p).

The inputs from the second to the seventh shaper 71 form its synchronization inputs “Sync.”, Records “Zap.”, Addresses “Adr. 1r”, “Adr. 2r”, “Adr. 3r” and read “Count.”

The signal output, as well as the synchronization and recording outputs of the driver 71 are connected to the corresponding inputs of the serial code to 72 converter, the outputs of the address signals are connected to the inputs of the address decoder 74, and the output of the read signal is connected to the read inputs of the first and second word registers 77, 78, address inputs "100" and "101" which are connected to the corresponding outputs of the decoder 74 addresses.

Zero and first outputs of the serial to parallel converter 72, on which signals are generated to turn on the power of the pulse channel (standby transceiver) and turn on the power to the complex channel (controlled power amplifier 21), respectively, through the first and second stages of galvanic isolation of GR ₁ , GR _{2 are} connected to the control inputs of the first and second key cascades Kl ₁ , Kl ₂ , the outputs of which form the outputs of the signals “Channel imp. On” and “Channel complex on” of the mode control unit 22.

The second output of the serial to parallel converter 72, on which a high-readiness signal is generated ("Ready"), is connected to the first inputs of the elements And ₁ , And ₂ , And ₃ And ₄ , and the outputs from the third to the seventh, on which respectively

attenuation signals “Oslab.1r”, “Oslab.2r”, “Oslab.3r” and signals “Kan.ant.1r”, “Kan.ant.2r” are generated, indicating the positions of the waveguide switch at which the antenna transmits and receives signals of a pulse (standby) channel, or a complex (main) channel, are connected to the corresponding inputs of the decoder 73 of the input signal.

At the corresponding outputs of the decoder 73, eight gradations of attenuation signals “Oslab.0”, ..., “Oslab.7”, as well as signals “Kan.imp.ant.”, “Kan.imp.ekv”, “Kan.soln. .ant. ”,“ Chan.Eq. Equiv. ”, the combination of which determines the position of the waveguide switch 4.

The output signal "Weak 0" of the decoder 73 of the input signal is connected to the first input of the eight-input element OR ₄ , to the second input of the two-input element And ₈ and to the first input of the three-input element And ₉ .

The output signal "Slab.1" of the decoder 73 of the input signal is connected to the second input of the OR element ₄ , to the fourth input of the four-input element OR ₁ , to the second input of the two-input element And ₇ and to the first input of the four-input element And ₁₂ .

The output signal "Slab.2" of the decoder 73 of the input signal is connected to the third input of the OR element ₄ , to the fourth input of the four-input element OR ₂ , to the second input of the two-input element And ₆ and to the first input of the four-input element And ₁₃ .

The output signal "Slab.3" of the decoder 73 of the input signal is connected to the fourth input of the OR element ₄ , to the third inputs of the elements OR ₁ and OR ₂ , to the second input of the two-input element And ₅ and to the first input of the five-input element And ₁₆ .

The output signal "Slab.4" of the decoder 73 of the input signal is connected to the first input of the four-input element OR ₃ , to the second input of the two-input element AND ₄ and to the first input of the two-input element And ₁₄ .

The output signal "Slack.5" of the decoder 73 of the input signal is connected to the second inputs of the four-input elements OR ₁ and OR ₃ , to the second input of the two-input element And ₃ and to the first input of the three-input element And ₁₀ .

The output signal "Slab.6" of the decoder 73 of the input signal is connected to the second input of the OR element ₂ , to the third input of the OR element ₃ , to the second input of the two-input element And ₂ and to the first input of the three-input element And ₁₁ .

The output of the signal "Slack.7" of the decoder 73 of the input signal is connected to the first inputs of the elements OR ₁ and OR ₂ , to the fourth input of the element OR ₃ , to the second

the input of the element And ₁ and to the first input of the four-input element And ₁₅ .

The outputs of the elements OR ₁ and OR _2, respectively, through the third and fourth cascades of galvanic isolation of GR ₃ and GR _{4 are} connected to the control inputs of the third and fourth key stages of Cl ₃ and Cl ₄ , the output of the first of which forms the output of the signal “Dec 10 dB” block 22 control of the modes, and the output of the second is the output of the signal “Decrease. 20 dB”, while the output of the key stage Cl ₃ through the eighth cascade of galvanic isolation GR ₈ is also connected to the fifth input of the element And ₁₆ , with the fourth inputs of the elements And ₁₂ And And ₁₅ and the third input of the element And ₁₀ , and the output the cascade of Cl ₄ through the ninth cascade of galvanic isolation GR _{9 is} connected to the fourth inputs of the elements And ₁₃ and And ₁₆ and to the third inputs of the elements And ₁₁ And ₁₅ .

The output of the OR ₃ element through the fifth cascade of galvanic isolation of the GR _{5 is} connected to the control input of the key stage Kl ₅ , the output of which forms the output of the mode control unit 22 by the signal “On 1” of the first channel (with transistor terminal amplifier) of the controlled power amplifier 21 . In addition, the second inputs of the elements ₁₀ , ₁₁ , _14, and _{15 are} connected to the output of the key stage of Cl ₅ through the tenth cascade of galvanic isolation of GR ₁₀ .

The outputs of the elements And ₁ , And ₂ , And ₃ And And _{4 are} connected respectively to the inputs from the fifth to eighth eight-input element OR ₄ , the output of which through the decoupling stage 84 is connected to the control input of the sixth key stage Cl ₆ , the output of which forms the output of the mode control unit 22 by the signal “Prev.kan.kan.2” preliminary switching on of the second channel (on the pulse amplifying klystron) of the controlled power amplifier 21. In addition, to the trick of Cl ₆ through the eleventh cascade of galvanic isolation of GR ₁₁ , the third inputs of the elements And ₉ , And ₁₂ , And ₁₃ And And _{16 are} connected.

The first inputs of the elements And ₅ , And ₆ , And ₇ And And _{8 are} connected to the input of the mode control unit 22, to which the signal "Got.2 channels." The readiness of the second channel, which also comes to the corresponding input of the register 77 of the first words whose inputs are “VN on” (high voltage on), “Repair Input” (input health), “Repair Output” (output health) and “Overheat” form the inputs of the same name as mode control unit 22, and the inputs the signals "Oslab.1r", "Oslab.2r" and "Oslab.3r" are connected to the outputs of the first cipher 79 torus.

The outputs of the elements And ₅ , And ₆ , And ₇ And And _{8 are} connected to the corresponding inputs of the four-input element OR ₅ , the output of which is through the sixth cascade of galvanic

isolation GR _{6 is} connected to the control input of the key stage Kl ₇ , the output of which is connected to the input of the transistor switch 81, the output of which forms the output of the mode control unit 22 by the signal “On channel 2” of the second channel of the controlled power amplifier 21. In addition, the output of Cl ₇ through the twelfth cascade of galvanic isolation GR ₁₂ connected to the second inputs of the elements And ₉ , And ₁₂ , And ₁₃ And ₁₆ .

The outputs of the elements I9, ..., I16, on which the signals "Oslab.0", "Oslab.5", "Oslab.6", "Oslab.1", "Oslab.2", "Oslab.4" are respectively formed , “Oslab.7” and “Oslab.3” are connected to the corresponding inputs of the first encoder 79.

The outputs of the signals “Kan.imp.ekv.” And “Kan.sel.ant.ant.” Of the decoder 73 input signals are connected to the first and second inputs of the two-input element OR ₆ , the output of which is connected through the seventh galvanic isolation cascade GR ₇ and the phase-inverse cascade 82 connected to the corresponding inputs of the switching unit 83 of the waveguide switch, the outputs of which form the outputs of the control signals of the mode control unit 22, determining the position of the waveguide switch 4.

In addition, the first input of the two-input element And ₂₀ and the first input of the three-input element And ₂₂ are connected to the output of the signal “Can.imp.ekv” of the input signal decoder 73, the first input of the two-input element And _{19 is} connected to the output of the signal “Can.imp.ant” and the first input of the three-input element And ₂₁ , the first input of the two-input element And ₁₈ and the second input of the element of the three-input element And _{22 are} connected to the output of the signal "Ch. complex. And the first input of the two-input element And is connected to the output of the signal" Ch. ₁₇ and the second input of the three-input element That And ₂₁ .

The second inputs of the elements And ₁₇ , And ₁₈ and the first input of the element OR _{7 are} connected to the input of the mode control unit 22, to which the signal "I-IV-VP" of the position of the waveguide switch 4, which receives and transmits signals of a complex (main) channel The radar, and the backup receive-transmit channel is connected to the matched load 5. The second inputs of the elements And ₁₉ , And ₂₀ and OR ₇ form the input signal "I-II-VP" of the second position of the waveguide switch, at which the pulse (backup) channel of reception transmission, and the control output The current power amplifier 21 is transmitted to the matched load 5 (antenna equivalent).

The output of the OR element _{7 is} connected to the third inputs of the elements And ₂₁ and And ₂₂ , the outputs of which are signals of "off microwave ₂ " or "off CBCH ₁ " shutdown pulse or

a complex channel, connected to the inputs of the same name in the register 78 of the second word, whose inputs are connected to the outputs of the second encoder 80, the inputs of which are connected to the outputs of the elements And ₁₇ , And ₁₈ , according to the signals "Can.ant.1p" and "Can.ant.2p" And ₁₉ and I ₂₀ .

The input of the signal amplification and signal conversion unit 76 forms the input of the mode control unit 22 to which the temperature control signals “Rt” of the base plate are received, on which the blocks of the controlled power amplifier 21 are placed. The outputs of block 76, on which a four-digit binary code of temperature gradations Ut1p, Ut2p, Ut3p, Ut4p is generated, are connected to the corresponding inputs of the second word register 78.

The outputs of the first and second word registers 77, 78 are connected to the corresponding inputs of the output signal generator 75, at the corresponding outputs of which, forming the same outputs of the mode control unit 22, the control signals of the state of the controlled power amplifier and the waveguide switch are recorded, recorded in registers 77 and 78.

The receiving device 24 is intended for receiving, converting and amplifying the signals reflected from the targets generated in the transmitting device of the main radar transmit-receive channel.

In Fig.5, the structural diagram of the receiving device 24 adopted the following notation:

85 - block attenuators, providing the initial setting of the gain level of the receiving device,

86 - microwave amplifier limiter

87 - the first balanced mixer,

88 - discrete attenuator,

89 - block gain and bandpass filtering,

90 - the second balanced mixer,

91 - band-pass filter,

92 - selective amplifier,

93 - frequency divider 1: 1000,

94 - three-stage adjustable amplifier,

95 - three-stage amplifier-limiter,

96 - block noise automatic gain control (BALL),

97 - block temporary automatic gain control (VARU),

98 is an OR element,

99, 100 - electronic keys,

101 - selective amplifier

102 is an amplitude detector,

103 - video amplifier,

104 - block threshold voltage control,

105 - a unit for converting a four-bit serial code into a four-bit parallel code (hereinafter referred to as a block for converting a serial code to parallel);

106, 107, 108 - elements OR,

109 - block conversion of logic level signals into current control signals (hereinafter referred to as the first signal conversion unit),

110 - a block for converting logic level signals to control voltages (hereinafter referred to as the second block for signal conversion);

111 - electronic key,

112, 113, 114 - blocks the formation of blanking pulses, each of which contains serially connected Schmidt trigger and an electronic key,

115 - DC amplifier,

116 - relay

117 - electronic key,

118 - stabilized rectifier, the output of which forms a voltage of ± 6 V,

119 - stabilized rectifier, the output of which forms a voltage of 12 V,

120 - stabilized rectifier, at the output of which a voltage of ± 12 V is formed,

121 - stabilized rectifier, the output of which forms a voltage of +5 V,

122 - stabilized rectifier, the output of which forms a voltage of ± 27 V,

123 - noise current regulator

124 - integrated voltage regulator +9 V.

According to figure 5, the signal input "microwave input." Block 25 amplification on the microwave and double conversion to IF (and the receiving device 24) through the block 85 attenuators connected to the signal input of the amplifier-limiter 86 microwave.

The output of the microwave amplifier-limiter 86 is connected to the first input of the first balanced mixer 87, the second of which forms the first heterodyne input "f _HET1 " of the microwave unit 25, and its output is connected through the discrete attenuator 88 to the input of the amplification and bandpass filter 89, the output of which is connected to the first input of the second balanced mixer 90. The second input of the balanced mixer 90 is connected to the output of the bandpass filter 91, the input of which forms the second heterodyne input "f _HET2 " of the microwave unit 25.

The output of the second balanced mixer 90, which is the output of the microwave unit 25, is connected to the signal input of the intermediate frequency pre-amplifier 26, which is the input of the selective amplifier 92. The second input of the selective amplifier 92 is connected to the output of the frequency divider 93, the input of which forms the control input of the pre-amplifier 26 connected to the output of the electronic key 117 of the control signal switching unit 30. The signal input of the electronic key 117 forms the input of the control signals “IF (KS)” of the unit 30 (and the receiving device 24), the control input of which is connected to a control amplifier 115 through a series-connected DC amplifier 115 and a relay 116 connected to the control the input of the electronic key 117, which is in the idle (normally closed) state is loaded with a resistor R.

The output of the selective amplifier 92, which is the output of the preliminary amplifier 26, is connected to the signal input of the main amplifier 27 of the intermediate frequency, formed by the signal input of a three-stage adjustable amplifier 94, the blanking input of which forms the input of the blanking pulses "BI" of the main amplifier 27.

The gain control input of a three-stage adjustable amplifier 94 is connected to the output of the OR element 98, and its output is connected to the input of a three-stage amplifier-limiter 95, the output of which forms the signal output "IF2" of the intermediate frequency of the main amplifier 27 and the receiving device 24.

In addition, a chain of series-connected selective amplifier 101, amplitude detector 102 and video amplifier 103 is connected to the output of the last stage of amplifier-limiter 95, the output “VIa” of which forms the output of the video scanning pulses in range, and the control input is the input of the signal for switching the band and sensitivity adjustment video amplifier ("Signal 1") of the main amplifier 27 and the receiving device 24.

The control output of the video amplifier 103 is connected to the input of the threshold block 104

voltage control, the output of which forms the output of the signal "Corr.PRM" operability of the receiving device 24.

In addition, the output of the three-stage amplifier-limiter 95 is connected to the input of the BALL 96 block, the output of which is connected to the first input of the electronic key 99, the second input of which forms the input of the signal "RRU" for manual gain control of the main amplifier 27. The output of the electronic key 99 is connected to the first input element OR 98, and its control input forms the input of the main amplifier 27 (and the receiving device 24) on the signal "off SHARU" shutdown noise automatic gain control. The threshold adjustment ballpoint for the BALL (“P-BALL”) and the BALL gate gate (“BALL Gate”) of the 96 BALL block form the inputs of the same name for the main UCH 27 and the receiving device 24.

The inputs of the electronic key 100 form, respectively, the input of the VARU triggering pulses (“VZV”) and the input of the “VARU off” signals for disabling the temporary automatic gain control of the main UCH 27 and the receiving device 24. The output of the electronic key 100 is connected to the control input of the VARU block 97 connected to the second input of the OR element 98, and the input forms the input signal "VARU-G" adjust the depth of the temporary automatic gain control of the main amplifier 27 and the receiver 24.

The first inputs of the OR elements 106 and 107 and the inputs of the blocks 112, 113 114 of the formation of blanking pulses are connected to the input of the “Blank” signal of the block 28 for generating control signals of the receiving device. The output of block 112, on which the “UHF Blank” pulse is generated, is connected to the blanking input of the amplifier-limiter 86, and the outputs of blocks 113 and 114, on which the “Blank 1” and “Blank 2” signals are blanked, are used for centralizing the memory and LNA of the input protection device 23 and amplification, form the same outputs of the block 28 of the formation of control signals of the receiving device.

The signal input, recording strobe input, and synchronization input of the serial to parallel conversion unit 105 form the corresponding inputs of the control signal generation unit 28, to which the attenuator control signal of the LNA of the input device 23, the DO signal (additional attenuation) are received by the four-digit code ) control discrete attenuator 88, and the commands "FC" (enable functional control mode) and "On GSh" (turn on the noise generator).

The output of block 105 converting the serial code into parallel, on

which generates the attenuator control signal “Att.”, is connected to the second input of the OR element 107, the output of which is connected to the input of the second signal conversion unit 110, and the output of the latter forms the output of the “Control Att.” signals of block 28, which are fed to the control input of the LNA The microwave input device 23 protection and amplification.

The output of the serial to parallel conversion unit 105, on which the DO (US) signal is generated, is connected to the second input of the OR element 106, the output of which through the first signal conversion unit 109 is connected to the control input of the discrete attenuator 88 of the microwave unit 25.

The outputs of the serial to parallel conversion unit 105, on which the FC and On GSh signals are generated, are connected to the first and second inputs of the OR element 108, the third input of which is connected to the contact of the manual button of the noise generator, and the output of the OR element 108 connected to the control input of the electronic key 111, the signal input of which is connected to the output of the stabilizer 123 of the power supply current of the noise generator, and the output forms the output of the signal "On GSh" block 28 of the formation of control signals of the receiving device.

The structure of the block 29 of the secondary power sources, in addition to the stabilizer 123 of the power supply current of the noise generator, includes voltage rectifiers 118, 119, 120, 121, 122, the outputs of which generate output voltages of various ratings for powering the receiver units, as shown in Fig. 5, and an integral a voltage stabilizer 124 generating a voltage of + 9V for the limiter amplifier 86. The input power to the integral stabilizer 124 is supplied from the positive terminal of the rectifier 120. Power distribution circuits from the rectifiers 120 and 121 V block 28 and from the rectifier 118 mainly UPCH 27 for simplicity, not shown in figure 5.

The pulse transmitter 33 of the backup transceiver device consists of a controlled modulator and a magnetron, at the output of which microwave pulses with a constant carrier frequency are formed. The duration modes of the generated pulses are set by the control signals "RD1", "RD2". The modulator is turned on by the “IZP” transmitter start-up pulses, and the high-voltage power supply is turned on by the “IZL” radiation pulses.

The standby receiving device 34 is made in accordance with the structural diagram shown in Fig.6, which adopted the following notation:

125 - cyclotron protective device,

126 is an ultra-high and intermediate frequency amplification unit (microwave-frequency converter) made in the form of a low-noise microwave amplifier, a mirror noise suppression filter, a first balanced mixer, a first intermediate frequency amplifier, a band-pass filter, and a second balanced mixer. In addition, the unit contains the circuits VARU, RRU and ARUSH (automatic gain control by noise);

127 - block amplification and conversion to a video frequency, including a logarithmic amplifier, a video detector and a low-pass filter;

128 - block of the first local oscillator, built on the basis of a voltage-controlled generator (VCO);

129 - block of the second local oscillator, built on the basis of a generator based on surface acoustic waves (SAW);

130 - block automatic frequency control (AFC), comprising a mixer that selects the first intermediate frequency, a frequency divider, a frequency discriminator, an amplifier-limiter and a frequency detector that generates pulses whose amplitude changes are proportional to the deviation of the signal frequency from the reference signal generated by a highly stable frequency generator;

131 - block of secondary power sources.

The input of the backup receiving device 34 is the input of the cyclotron protective device 125, the output of which is connected to the input of the microwave and IF amplification unit 126, the first and second heterodyne inputs of which are connected to the outputs of the blocks 128, 129 of the first and second local oscillators. The control inputs of block 126 by the signals of the receiving device blank (“Blank”), starting the VARU (“IZV”), switching from manual gain control to automatic gain control (“RRU / AGC”), as well as the inputs to which voltages that determine the duration and depth of the VARU ("VARU-D", "VARU-G"), and voltage manual gain control ("RRU"), form the same control inputs of the backup receiving device 34.

The signal output of the microwave-frequency converter unit 126 is connected to the input of the amplification and conversion unit to the video frequency, the output of which forms the output of the “Video-R” video pulses of the scanning range of the receiving device 34, and the output of the output signal follower is connected to the input of the automatic noise gain control (ARUSH ) block 126 of the microwave frequency converter. The control input of the block 127 amplification and conversion to the video frequency signal "Lane." Switching the receiver band forms

the input of the same device 34.

The signal output and the input signal of the first heterodyne frequency of the automatic frequency control unit 130 are connected respectively to the control input and output of the block 128 of the first local oscillator. The input of the AFC unit 130, to which the output signal of the pulse transmitter 33 is supplied, forms the AFC input of the backup receiving device 34, the control input of which is connected to the corresponding control input of the automatic tuning block 130 by the signal “RPC / AFC” of switching from manual to automatic frequency control frequency, and the control input, which receives the voltage "RPC" manual frequency adjustment, is connected to the corresponding control input of block 128 of the first local oscillator. The control output of the intermediate frequency capture signal “Capture IF” of the AFC unit 130 forms the same output of the backup receiving device 34.

The input of the IHEP unit 131 forms the power input of the receiving device 34, and its outputs, on which power voltages of various ratings are generated, are connected to the corresponding elements of the blocks that make up the receiving device.

The switch control unit 37 is designed to generate TTL level DC voltages for switching to the corresponding position of the power attenuation switch 36.

Block 37 contains an input multiplexer, the inputs of which form the inputs of signals “0Р” and “1Р”, which specify the attenuation level, and the output is connected to the input of the transistor switch block, the inclusion of one of which corresponds to the attenuation of the output signal by 10 dB, and the inclusion of the second by 20 dB The control signals are generated in the switch control unit 37 by removing the voltages incident on the transistor switches. These voltages pass through the output multiplexer to the emitter followers, the outputs of which form the outputs of the control signals “K0P” and “K1P” of the switch control unit 37.

The control and synchronization unit 38 is designed to receive information and control commands from the controller 47 of the communication and control channels via the RS-422 channel (M1 highway), generate control commands for the pulse transmitter 33 and the backup receiver 34, receive and process control signals and transmit them to controller 47 communication and control channels.

In Fig.7 structural diagram of the block 38 control and synchronization adopted the following notation:

132 - micro-computers with internal programmable memory (ROM) programs, random access memory (RAM) and built-in digital-to-analog converter (DAC),

133 - programmable logic integrated circuit (FPGA) of the FLEX 10K type, which implements signal shaper circuits with a given duration and repetition period, a clock shaper, write and read gate shapers, control signal shapers, and a register of output control commands for the transmitter and receiver , register of input commands for working out health signals, register of input control commands for FPGAs, registers of delay codes and duration of generated signals, etc .;

134 - programmable memory device FPGA programs,

135 - crystal oscillator,

136 - block matching input signals mining and health, made on resistor matrices (hereinafter referred to as block matching input signals),

137 - input shaper of blanking pulses of the transmitter ("BIP"),

138 - shaper codes delay pre-emptive start pulses ("UIZP"), made on digital switches,

139 - shaper codes delay pulses blanking the receiver ("Blank"), made on digital switches,

140 - shaper codes delay pulses start VARU ("IZV"), performed on digital switches,

141 - output amplifier of pre-emptive triggers,

142 - output pulse amplifier of the initial reference of the scanning range ("NOD-R")

143 - output pulse amplifier "Blank",

144 - output amplifier pulses start VARU,

145 - output amplifier power control signals,

146 - register commands installation mode

147 - register of control signals of the status of the transceiver device,

148 - block digital-to-analog conversion (DAC),

149 - buffer,

150 - shaper control bus

151 - voltage driver manual frequency adjustment ("RPC"),

152, 153 - transceivers of serial channels RS-422 (trunk M1, M2),

154 connector

155, 156 - connectors for downloading programs.

157 - control bus (SDI),

158 - bus data-address (AD),

159 is a secondary power source.

According to Fig.7, the microcomputer 132 is connected via the control bus 157 (SDI) and the bus 158 address-data (AD) with FPGA 133, with a register 146 of the commands for setting modes, with a register 147 status signals and block 148 of the DAC.

At the outputs of register 146, signals “RD1”, “RD2” for adjusting the duration of the probing signal, signals “0Р”, “1P” for adjusting the attenuation of the power of the probing signal, signal “РРУ / АРУ” of switching from manual to automatic gain control, signal “РПЧ / AFC "switching from manual to automatic frequency adjustment and the signal" Pol.pol. "Switching band receiving device. Transmission and reception of the above signals is through an external connector 154.

The register 147 is used to record control signals of the state of the control panel: “MI current” (magnetron current) and “IF pickup” (capture of an intermediate frequency), which are read by the read strobe and transmitted to the microcomputer 132 when forming the control information packet.

At the outputs of the DAC block 148, control voltages of manual gain control “RRU”, depth “VARU-G” and duration “VARU-D” of temporary automatic gain control are formed. The reference voltage Uop is supplied to the DAC 148 from a secondary power source 159, which generates output voltages of ± 3 V, ± 5 V, and ± 12 V to power the corresponding elements of the control and synchronization unit 38.

In addition, a buffer 149 is connected to the control bus 157, which is used to transmit pulsed signals to start the transmitter (“IZP”), radiation (“IZL”), and start the VARU (“IZV”), a bus driver 150 intended for receiving and transmitting control signals (SDI, W / R, CLK, CON), a serial channel transceiver 152 (M1 highway), through which a packet of control signals that establish the operation mode of the control unit, and a control signal packet of the state of the control unit, and a serial channel transceiver 153 (M2 line) are transmitted, by

to which codes of the current bearing of the TIN antenna are transmitted.

Transmission and reception of the above signals is through an external connector 154.

To the FPGA 133 the outputs of the block 136 matching the input signals of working out and serviceability of the PPU are connected to which the control signal (“IZP control.”, “Got.”) Of the pulse transmitter and the signals “Isp.PRD”, “Isp. PU ”transmitter and receiver serviceability. The FPGA 133 is also connected to the output of the input pulse shaper 137 "BIP" and the outputs of the shapers 138, 139, 140 of the pulse delay codes "UIZP", "Blank" and "Izv", respectively.

The outputs of the FPGA 133, on which the pre-emptive triggering pulses of the "UIZP" are formed, the pulses of the initial counting of the scanning range "NOD-R" and the blanking pulses of the receiving device "Blank" are connected to amplifiers 141, 142, 143, the outputs of which form the corresponding outputs of the control unit 38 and synchronization.

The output of the FPGA 133, on which the signal "IZV" is generated, is connected through the output amplifier 144 and the control bus 157 to the input of the buffer 149. The output pulses of the transmitter "IZP" and the radiation pulses "IZL" generated by the IZL are transmitted to the other inputs of the buffer 149 through the bus 157 FPGA 133. The outputs of the buffer 149, on which the signals "IZP", "IZL" and "IZV" are connected to the connector 154.

The outputs of the FPGA 133, on which the signals “Pit.Heat.”, “Pit.Off.” Of the transmitter power control are generated, are connected to the inputs of the amplifier 145, the outputs of which form the outputs of the corresponding signals of the control and synchronization unit 38 transmitted through the connector 154.

To the output of the digital-to-analog converter, which is part of the microcomputer 132, a shaper 151 of the “RPC” voltages is transmitted to the output of the control and synchronization unit 38 through a connector 154.

The output of the quartz oscillator 135 is connected to the synchronization inputs of the microcomputer 132 and the FPGA 133, to the input of the program downloads of which the ROM 134 is connected.

Block 40 synchronization and pairing, which is part of the device 39 primary processing, contains a synchronization block, the shapers codes for setting the carrier frequency LF ₁ , ..., LF ₇ for the shaper 9 of the emitted signals, implemented on the basis of random number generators, signal matching blocks "AM2 ",

"F1", "F2", "Blank", "BI", "H", "Izv", "strobe SHARU", coming from the device 46 for the formation and processing of complex signals and transmitted through block 40, as well as block matching video pulses in range coming in functional control mode from the receiving device or in the operating mode of the backup channel coming from the backup receiving device 34. The synchronization and pairing unit 40 is implemented on the basis of FPGA technology and also has analog circuits.

Radar processors 41, 42 are designed to process radar video signals and generate data, respectively, for the channel of the circular viewing indicator and the indicator channels of the exact coordinates and the target extractor. Control and data output of radar processors is carried out via serial channels of the local Ethernet 10BASE-T Ethernet network (twisted pair).

On the structural diagram of Fig.8 of the radar processor 41 (42) the following notation:

160, 161, 162 - the first, second and third digital signal processors (DSP) type SHARC (ADSP-21062),

163 - programmable logic integrated circuit (FPGA) radar interfaces,

164 is a programmable logic integrated circuit interface with a mezzanine module of the LAN controller,

165 - analog-to-digital Converter,

166, 167 - ROM (FLASH-memory) programs DSP,

168, 169 - ROM of FPGA programs.

8, the FPGA 163 of the radar interfaces is connected by direct memory access lines (IDMAs) to the first and second DSPs 160, 161, which are connected to each other and to the third DSP 162 via communication buses (Link).

The second DSP 161 is connected via the IDMA trunk to the FPGA 164, to which the E1 (E2) trunk is connected through the Ethernet LAN controller 43 (44).

The FPGA 163 digital interfaces are connected to the RS-422 serial M2 trunk, through which the current antenna bearing code is transmitted, and the M8 trunk of the specialized digital 14-bit radar data input interface, through which information is transmitted from the device 46 for generating and processing complex signals to the radar processor .

For receiving VIA video signals (in pulsed operation modes of the main

radar transmit-receive channel) and Video-R (in the operating mode of the backup radar transmit-receive channel), the radar processor 41 (42) has an analog interface (ADC 165). In the ADC 165, the incoming video signals are digitized, and the ADC output 165 is connected to the input of the FPGA 163, synchronized by the pulses that come from the synchronization and pairing unit 40 together with the video signals.

The digital receiving device 45 provides analog-to-digital conversion of the intermediate frequency signal, the formation of digital quadrature signal components, demodulation, digital filtering of the signal and the formation of the intermediate frequency control signal “IF (CS)”. The implementation schemes of digital receivers are known from the prior art and are considered, for example, in [6].

The device 46 for the formation and processing of complex signals (FOS) performs the functions of generating and processing signals of a coherent long-range Doppler radar operating with complex amplitude-phase-manipulated signals.

In Fig.9 block diagram of the device 46 for the formation and processing of complex signals, reflecting the architecture, bus organization and basic signals in their functional purpose, the following notation:

170 - control signal processor (USP), implemented on an ADSP 2183 chip,

171 — non-volatile programmable memory (ROM) implemented on the AMF040 chip for storing USP programs, correlation spectral processing clusters, system interface architecture files, control command input architecture files, and compression device architecture files;

172 - random access memory (RAM),

173 - controller bus control and data exchange (hereinafter referred to as the bus controller),

174 - encoder implemented on the basis of the FPGA XCV50,

175 ₁ , ..., 175 ₈ - blocks of digital signal compression devices (hereinafter referred to as signal compression blocks) implemented on the basis of the XCV50 FPGA,

176 ₁ , ..., 176 ₈ - signal processors (ADSP 2185),

177 ₁ , ..., 177 ₈ - RAM of the external data memory,

178 - port interface with a digital receiver,

179 - port of the serial channel RS-422,

180 - clock generator

181 - watchdog timer, implemented on an ADM706 chip and logic,

182, 183 - connectors,

184, 185, 186, 187 - buffers.

The FOS device 46 is a hardware-software device based on Xilinx programmable logic FPGAs and Analog Devices Inc. signal processors. with software and mathematics loaded from the built-in Flash-memory that allows changing the structure of signals and their processing algorithms depending on the operating mode.

According to Fig.9, the device 46 includes an encoding device 174, which forms the structure of the probing signals, a control signal processor 170 and eight interconnected clusters of the correlation-spectral signal processing device, including each block 175 ₁ (175 ₂ , ..., 175 ₈ ) signal compression, connected to RAM 177 ₁ (177 ₂ , ..., 177 ₈ ) of the external data memory, and a signal processor 176 ₁ (176 ₂ , ..., 176 ₈ ) connected to block 175 ₁ (175 ₂ , ..., 175 ₈₎ compression signals through the serial bus (SPORT), programmable interfaces tires (FL, PL), the tire reign (WR, RD, DMS, PMS, IDMS), and the address data bus (AD).

The control signal processor 170 is connected through an address bus system (ADDRES Bus), data (DATA Bus) and control (WR, RD, BMS, PMS, DMS, IDMS) with ROM 171, RAM 172 and encoder 174, connected to a bus controller 173 via the control and address buses and, in addition, is connected to the encoder 174 by serial bus (SPORT), programmable interface (PF), control (BR, BG, BHG), interrupt (IRQ) and synchronization (CLK) buses.

The direct memory access ports (IDMA) of the signal processors 176 ₁ , ..., 176 ₈ are connected to the bus controller 173 via direct memory access buses through which control signals are transmitted (CS, IAL, IWR, IRD). The serial ports of the signal processors through which information data is transmitted are connected via a buffer 184 to the data bus.

In addition, the control signal is connected to the watchdog timer 181 and, through the buffer 185, to the connector 182, which is used as a process port for downloading and debugging programs.

The encoder is connected to signal compression blocks 175 ₁ , ..., 175 ₈ by means of a bus system (IOXC), through which words of the generated structure of the sounding signal are transmitted during the correlation signal processing.

The encoding device 174 is also connected to the interface port 178 with the CPU, through which digital quadrature components of information signals are received from the CPU 45 to blocks 175 ₁ , ..., 175 ₈ , and to the port 179 of the RS-422 serial channel, through which the М4 highway communication with the controller 47 communication channels and control.

The information output of the encoding device 174 (and FOS device 46), on which the radar data is generated, is connected through a buffer 186 and a connector 183 via the M8 trunk of a 14-bit specialized interface (Dout) to the inputs of the digital interfaces of the radar processors 41 and 42.

In addition, the outputs of the signals generated by the encoder 174 of the modulating (AM2, F1, F2) and switching (H, Blank, BI, IZV, Strobe BALL) signals, through a buffer 187 and a connector 183, are connected to the synchronization and pairing unit 40, which broadcasts these signals , as shown above, in the corresponding device of the transmitting and receiving paths of the main radar transmit-receive channel.

Figure 10 of the structural diagram of the controller 47 of the communication and control channels adopted the following notation:

188 - microprocessor control unit (MB-U),

189 - microprocessor unit antenna (MB-A), operating in the mode of coprocessor MB-U 188,

190 - block external relations (AC),

191 - control and coordination unit (BCS),

192 - central processing unit (CPU),

193 - a data memory device made in the form of random access memory (RAM) 8 KB,

194 - program memory device (programmable storage device),

195 - watchdog timer

196, 197 - the first and second parallel input-output devices (PPVV), each of which contains three programmable input-output ports, the lines of which are output to the block connector,

198 - display register (RGI),

199 - driver-receiver of the RS-232 serial channel (hereinafter - driver-receiver),

200 - block matching signals

201 - controller of serial channels (RS-422),

202 - block galvanic optical isolation (GOR),

203 - digital-to-analog Converter (DAC),

204 is a block conversion of RS-232 / RS-422 interfaces.

The controller 47 of the communication and control channels comprises two microprocessor units 188 and 189, an external communication unit 190, and a control and coordination unit 191.

Each of the microprocessor units 188, 189, made in the same way, contains a central processor 192 having an address bus (A), along which eight high order bits of the address are transmitted, a bi-directional address-data (AD) bus, along which eight lower order bits of the address are transmitted, and data bytes, and the bi-directional bus of the high-speed port P1.0-P1.7.

In the address space of buses A and AD, there is a data memory device 193, a program memory device (ROM 194), two parallel I / O devices 196, 197, as well as a watchdog timer 195 and an indication register 198, the output of which is connected to a digital indicator. In addition, the CPU 192 has an integrated serial input / output circuit (RXD-TXD) circuitry that is consistent with external communication lines through the driver / receiver 199.

The inputs and outputs of the first parallel input / output devices 196 of the microprocessor units 188 and 189 are interconnected by a software-controlled data exchange bus, and the input-output of the second PPVV device 197 of the microprocessor unit 188 is connected to a signal matching unit 200, which is made on an ALTERA 10K3O FPGA, that implements the functions of the hardware and software interface of the microprocessor control unit 188 with the control and coordination unit 191 and with the serial channel controller 201, which is implemented on the basis of UART-TL16C microcircuits.

Highways M1, ..., M6 of serial RS-422 channels are connected to the controller 201 of the serial channels, through which the controller 47 of the communication and control channels is connected to the corresponding radar devices, as shown in Fig. 1.

The control and coordination unit 191, which performs the functions of receiving and transmitting control and control signals and matching them with the characteristics of communication lines, contains a galvanic-optical isolation unit 202 connected to a signal matching unit 200, a digital-to-analog converter 203 connected to the output of the high-speed port P1.0-P1 .7 microprocessor control unit 188,

and an RS-322 / RS-422 interface conversion unit 204 connected to the driver-receiver 199 of the microprocessor unit 189 of the antenna.

An RS242 serial line M2 is connected to the output of the interface conversion unit 204, through which a 12-bit code of the current antenna bearing is transmitted to the radar processors 41 and 42 and to the control and synchronization unit 38 of the backup control panel.

The corresponding outputs of the GOR unit 202 form the outputs of the discrete signals of the controller 47 of the communication and control channels, namely:

signals for switching the antenna channels (“Kanant.ant.1r”, “Kanant.ant.2r”), control signals of the power amplifier 21 (“Kan.ant. on.”, “Boost. prepared.”, “Kan.s. on. . ”), Attenuation signals (“ Osl. 1p ”,“ Osl. 2r ”,“ Osl. 3r ”) and a signal to turn on the backup radar transmit-receive channel transmitted to the transmitting device operating mode control unit 22;

recording strobe “Strobe zap.”, clock pulses “SI” and codes of control signals “Att.”, “DO”, “On GSh”, “FK”, transmitted to the block 28 for generating control signals of the receiving device;

a simulation enable signal “On Sim.” transmitted to the control signal switching unit 30 of the receiving device 24;

a signal for switching the passband and adjusting the sensitivity ("Signal 1"), transmitted to the control input of the video amplifier 103 of the main amplifier 27;

disconnecting signals VARU and BALL, arriving in the main UChP 27.

The corresponding inputs of the GOR unit 202 form the input of the “Corr.form.” Signal of the health of the driver coming from the control unit 20 of the shaper, the signal “Corr. PRM” of the health of the receiver coming from the block 104 of the control of the receiving device 24, also the group of control signals “Corr.in . ”,“ Rev. out. ”,“ HV on ”,“ HV off ”,“ Got.2k. ”,“ Off Microwave 1 ”,“ Off Microwave 2 ”,“ Osl. 1r, 2r, 3r ”, "Overheating" and temperature control signals Ut1p, ..., Ut4p coming from the block 22 of the control and monitoring.

At the output of the DAC 203, the voltages “RRU” of the manual gain control, “P-BALL” of the BARU threshold adjustment and “VARU-G” VARU depth adjustment, transmitted to the main UCH 27, are formed.

In Fig.11 structural diagram of the drive 2 of the antenna and the controller 48 of the drive of the antenna and the following notation:

205 - microprocessor control unit,

206 - block external relations,

207 - control and coordination unit,

208 - central processing unit,

209 - parallel input-output device,

210 - block matching and converting signals implemented on the FPGA ALTERA 10K30,

211 - controller of serial channels,

212 ₁ , 212 ₂ - the first and second blocks of digital angle conversion,

213 ₁ , 213 ₂ - the first and second power amplifiers,

214 - brushless torque motor,

215 - power gearbox,

216 - engine sensor,

217 - antenna sensor.

According to Fig. 11, the electromechanical drive 2 of the antenna, providing the required antenna rotation speed, setting it to a predetermined position and scanning in a given angle sector, contains a brushless torque motor 214 of the DBM-120 type, a power reducer 215 with a gear ratio i≈30 and two amplifiers 213 ₁ , 213 ₂ power. In front of the gearbox 215, a VT-60 type engine sensor 216 is installed on the motor shaft, generating data q _dv about the position of the rotor of the torque motor, and an antenna sensor 217 is made on the output shaft of the gearbox, made in the form of a non-contact angle sensor type "5 BWT", generating q data _A about the angular position of the antenna.

Power amplifiers 213 ₁ , 213 _{2 are} made according to a transistor bridge circuit, one diagonal of which is connected to a power source, and the other to a motor winding 214. Power is supplied to the motor windings by pulse-width (PWM) signals, which are generated at the output of matching block 210 and converting the signals of the antenna drive controller 48.

The antenna drive controller 48 includes a microprocessor control unit 205, an external communication unit 206, and a control and coordination unit 207.

The microprocessor unit 205, made similarly to the microprocessor units 188, 189, includes a central processor 208 and a parallel input-output device 209, the first port of which is connected to the outputs of the digital angle conversion units 212 ₁ , 212 ₂ , and the second one - with the matching unit 210 and transformations

signals and with the controller 211 serial channels.

Block 210 is made on the basis of FPGA, which implements control and coordination functions, as well as generating, based on the drive control codes coming from the CPU 208, pulse-width modulated signals that are transmitted to the control inputs of power amplifiers 213 ₁ , 213 ₂ .

The engine sensor 216 and the sensor 217 outputs an antenna coupled to inputs of first and second units 213 _1, 213 ₂ digital angle conversion performing signal conversion _dd q and q _A a digital 13-bit codes for transmission to the CPU 208.

The M6 highway is connected to the controller 211 of the serial channels, along which the data of the angular position of the antenna are transmitted to the controller 47, and the M7 highway, through which the drive control commands (type of movement, position of the sight, scanning) are received from the secondary processing, control, and display device 49, and from the controller 48, the calculated values of the drive error Δq and the values of the control signals on the Cos and Sin channels are transmitted.

On Fig structural diagram of the device 49 of the secondary processing, control and display adopted the following notation:

218 - remote terminal,

219 - control device, processing and coordination (UOS),

220 - a video processor (VP) made in the form of a single-board computer of the CPU 686 E type with a Geode GX1 processor having an ISA system bus according to the IEEE-P966 standard, a built-in reprogrammable memory device such as Flash disk 8 MB, video RAM (allocated from the total memory size) , ports for connecting serial RS-232 interfaces, Ethernet 10/100 Base TX interface (via RJ-45 connector), EIDE port for connecting a long-term storage device (compact Flash disk), SVGA port for connecting a display, standard TFT port for connecting TFT and EL panels, etc. Computer video system serial ports CPU 686E is formed on the basis of the video controller LSI 5530 Cx providing display control possibility with a maximum resolution of 1280 × 1924 pixels at 256 colors. The configuration of the CPU 686E is carried out using a serial EEPROM chip, which allows you to store setup programs (SETUP program), I / O port addresses, and other settings.

221 - control processor, made in the form of a single-board computer type CPU 686E,

222 - a command processor made in the form of a single-board computer type CPU 686E,

223 - information display, for example, of the type VMTS-45ZHKM, providing the display of information transmitted via the RGB interface,

224 - electronic control panel, for example, type EL640.400-C3 Panel,

225 - front panel of controls and displays (hereinafter referred to as the front panel),

226 - hour meter,

227 - group of functional buttons,

228 - coordinate pointing device (trackball),

229 - LED display

230 - technology keyboard

231 is a block for converting signals of pressing buttons into a code (hereinafter referred to as a block for converting signals),

232 - video amplifier,

233 - control unit indicators

234 - module isolated digital input-output (board D132-5),

235 - analog-to-digital input-output module (UNIO96-1 Low-Cost Analog / Digital I / O Card),

236, 237, 238, 239 - blocks of isolated converters of the RS-232 interface to the RS-422 interface from the first to fourth, respectively (hereinafter referred to as interface conversion blocks),

240, 241, 242 - the first, second and third DZU (Compact Flash Disk - 512 MB),

243 - controller of serial channels RS-232 (board 5558 Octal Serial Card),

244 - multiplex channel controller (board TX-MP-DB-121SA-M),

245 - Ethernet local area network switch (BT23-415A module),

246 - RGB signal amplifier.

12, the secondary information processing, control, and display device 49 comprises a control, processing, and coordination device 219 based on a video processor 220 and a control processor 221, and a remote terminal 218 (automated workstation (AWS) of a radar operator) based on a command processor 222, equipped with working bodies for entering control information into the devices of the complex and means for displaying information.

The EIDE port of video processor 220 is connected to the first DZU 240, the SVGA port is through an amplifier 246 of RGB signals, connected to the input of the information display 223 of the remote terminal 218, the Ethernet port is connected to the first input-output of the LAN switch 245, and the first is connected to the serial ports of the RS-232 channels and the second blocks 236, 237 interface converters. An RS-422 serial line M5 is connected to the first block 236 of the interface converters, through which communication with the controller 47 of the communication and control channels is connected, and to the second block is the RS-422 serial channel trunk of the UUOS 219 with the remote terminal 218, which is connected through the fourth block 239 interface converters with a controller 243 serial channels of the remote terminal.

The fifth and second inputs and outputs of the LAN switch 245 are connected via the corresponding LAN lines to the Ethernet ports of the command processor 222 and the control processor 221, and Ethernet lines E1 and E2 are connected to its third and fourth inputs and outputs, through which communication with the radar processors 41 and 42.

The EIDE port of the control processor 221 is connected to the second DZU 241, the RS-232 serial channel port is connected to the third interface converter 238, to which the M7 trunk of the RS-422 serial channel is connected, through which communication with the antenna drive controller 48 is connected, and to the system bus the control processor 221 is connected to the multiplex channel controller 244, through which information is exchanged with external systems.

A controller 243 of serial channels, an analog-to-digital input-output module 235 for inputting information from a temperature monitoring device, and an isolated digital input-output module 234 for inputting serviceability signals of secondary power supplies are connected to the system bus of the command processor 222.

The EIDE port of the command processor 222 is connected to the third DZU 242, the TFT port (a video output compatible with displays based on TFT panels) is connected through an amplifier 232 of video signals to the input of the electronic control panel 224, and the output of the conversion unit 231 is connected to the ports of the serial RS-232 channels signals and input block 233 control indicators.

The first group of inputs of the block 231 signal conversion is connected to the outputs of the signal circuits of the group of functional buttons 227 of the front panel of the terminal,

and the second - with the outputs of the signal circuits of the keyboard 230. The buttons include power buttons, turn on the radar, mode buttons, buttons to turn on and off the antenna drive, etc.

The outputs of the indicator control unit 233 are connected to the inputs of the signal circuits of the indicators of the LED board 229, which indicate the status of various radar devices.

In addition, the front panel 225 has a hour meter 226 indicating the operating time of the station, and a trackball 228 with three keys, through which the operator enters control signals to the electronic control panel 224 into the computer system and controls the information display 223).

Radar works as follows.

After turning on the power and completing the test test of the radar computer system, the operator, using the remote terminal controls (group of function buttons 227, trackball 228, keyboard 230, electronic control panel 224), provides the radar either in the main modes of reception of the radar, or in the operation mode of the backup radar transmit-receive channel, or in the functional control mode.

The modes of operation of the main receive-transmit channel differ in the type of probing signal being generated: pulsed (IMP), pulsed with intrapulse phase shift keying (IFM) and quasi-continuous signal with amplitude modulation and phase shift keying (SPS). In each of the selected operating modes, the operator sets the range scale and the carrier frequency setting mode (without tuning, or with tuning each sounding period). In addition, the operator sets the operating mode of the antenna drive (type of movement, position of the sighting device, scanning, speed, etc.).

When an operator uses a group of function buttons 227 and a keyboard 230, their signals are transmitted through a signal converting unit 231 to a command processor 222, and from its Ethernet port through a LAN switch 245 are transmitted to a video processor 220 and a control processor 221 using the corresponding LAN backbones.

Work with the electronic control panel 224 is provided using the trackball 228, the output signals of which are fed to the controller 243 serial channels connected through a system bus to the command processor 222, and

from the controller 243 through the block 239 of the interface converters via the RS-422 channel are transferred to the UUOS 219, in which through the block 237 of the conversion of the interfaces are received in the RS-232 port of the video processor 220.

Next, the control signals of the devices of the main (or standby) transceiver channel from the output of the second RS-232 port of video processor 220 through the block 236 of the interface converters enter the trunk M5 of the RS-422 serial channel and are transmitted through it to the controller 47 of the communication and control channels.

The control processor 221 in accordance with the incoming signals generates control signals for the antenna drive, which from its RS-232 port through the interface conversion unit 238 enter the RS-422 serial channel M7 and are transmitted through it to the antenna drive controller 48.

In the controller 48 of the antenna drive, the received signals through the controller 211 of the serial channels and the PPVV device 209 are supplied to the central processor 208, which generates the signal codes q _{control sin} and q control _cos of the drive motor control, which enter the block 210 matching and converting signals. In block 210, these signals are converted into pulse-width signals, the width of which is proportional to the module | q _control.sin | or | q _{control cos} |, and are transmitted to the control inputs of the power amplifiers 213 ₁ , 213 ₂ , providing the required operating mode of the brushless torque motor 214.

Control of the drive 2 antennas carried by the antenna sensor 217 generating signals q _and the angular position of the antenna, and by an engine sensor 216, coupled to the motor shaft through a fine gear with play-free transmission with the same transmission ratio and generating a signal q _dd used for forming feedback servo drive.

The signals q _A and q of the _two sensors 217 and 216 from the outputs of the drive 2 of the antenna are fed to the inputs of the blocks 212 ₁ , 212 _{2 of the} digital angle conversion, forming codes measured by the angle sensors, and from them through the device 209 PPVV to the Central processor 208, which performs the calculation of the signal Δq drive errors and the formation of control signals through the channels Sin and Cos, fed to the PWM circuit of block 210, which generates control signals for power amplifiers 213 ₁ , 213 ₂ , thus closing the feedback loop of the servo drive.

In addition, the codes of the angular position of the antenna are transmitted through the PPVV device 209 in real time (one codeword every 600 ms) to the controller 211 of the serial channels, the output of which via the M6 highway

in the block 190 of external communications of the controller 47 channels of communication and control.

In the controller 47, the control signals received from the secondary processing, control, and display device 49 and the antenna angular position signals received from the antenna drive controller 48 are transmitted through the serial channel controller 201 and the signal matching unit 200 to the PPVV device 197, and from there to the microprocessor central processor 192 control unit 188, in which algorithms for receiving and transmitting control information and generating control and control signals are programmatically implemented.

The microprocessor unit 189 of the antenna, operating in the coprocessor mode of the microprocessor control unit 188, calculates the compensation corrections for the Doppler frequency shift resulting from the own movement of the radar carrier and transmits them through the external communication unit 190 via the M4 highway of the RS-422 serial channel to the device 46 the formation and processing of complex signals.

In addition, the central processor of microprocessor unit 189 of the antenna generates data for transmission of the current bearing of the antenna, which is transmitted in serial 12-bit code via the RS-232 port and the driver-receiver to the input of the interface conversion unit 204, and from its output through the M2 highway enter the radar processors 41, 42 and to the control and synchronization unit 38 (in the operation mode of the backup radar transmit-receive channel).

The information exchange of the microprocessor control unit 188 with the synchronization and pairing unit 40, the complex signal generation and processing device 46 and the control and synchronization unit 38 (in the operating mode of the backup radar transmit-receive channel) is carried out through the controller 201 of the serial channels of the external communication unit 190 using highways M3, M4 and M1 serial channels RS-422.

The communication of the microprocessor control unit 188 with the control unit 22 of the operating modes of the transmitting device, the emitter 9 of the emitted signals and the receiving device 24 is carried out through the block 200 signal matching and block 191 control and coordination using the block 202 galvanic isolation for transmitting and receiving discrete control and control signals and using the DAC 203 for transmitting analog signals (control voltages).

To ensure the operation of the transmitting path of the main transceiver

The radar channel at the corresponding outputs of the GOR unit 202 first generates the setup signals “Can.sl.on.” and “Can.ant. 1r”, received by an 8-bit serial code (together with synchronization and recording pulses) through the input signal shaper 71 (see 4), at the input of the serial to parallel converter 72.

From the output of the converter 72, the signal “Can.sl.on.” Through the cascade of GR _{2 of} galvanic isolation is supplied to the control input of the key stage of Cl ₂ , opening it, and the voltage of ± 27 V from the DC power source is supplied to the power input (second input) of the unit 61 switching and control in a controlled power amplifier 21 (see figure 3). When this occurs, the block 70 IWEP, providing power to the low-current elements of the amplifier 21 of the power, and at the sixth output of the block 61 of the switching and control signal is generated to turn on the synchronizer 59, which generates synchronization signals of the preliminary and final stages of amplification.

The signal “Kanant.ant.1r” from the output of the converter 72 enters the decoder 73 of the input signal, at the ninth and eleventh outputs of which a combination of the signals “Kan.sl. Ant.” And “Kan.imp.Ekv.” Arriving at the inputs of the element OR ₆ , the output signal of which through the cascade of GR _{7 of} galvanic isolation and the phase-inverse cascade 82 is supplied to the control inputs of the switching unit 83, the output of which is 27 V via the +27 V / -27 V and -27 V circuits to the waveguide switch 4, setting it to the position of connecting the antenna path to the first circ to the cooler 6, and the agreed load 5 to the second circulator 7.

In the absence of signals “Channel Ant.” And “Channel I. Eq.”, Which is equivalent to the presence of signals “Channel C. Ant.” And “Channel C. Eq.”, The voltage is 27 V from the output of block 83 switching enters the waveguide switch 4 through the +27 V / -27 V and +27 V circuits, setting it in a different position.

Then, depending on the type of probe signal selected, the first channel (for IFM and SPS signals) or the second channel (for IMP signals) of the controlled power amplifier 21 is turned on and the level of attenuation of its output power is set.

In this case, depending on the set attenuation level “Oslab.1r”, “Oslab.2r”, “Oslab.3r” of the signals generated at the output of the GOR unit 202, eight gradations of attenuation “Osl.0” are formed at the outputs of the decoder 73 of the input signals, ..., "Donkey 7". Signals, "Osl.4", ..., "Osl.7" corresponding to the output level

the power of the first (transistor) amplification channel, through the OR ₃ element and the cascade of GR _{5 of} galvanic isolation, form a control signal for turning on the key stage Kl ₅ , at the output of which a signal “On 1” arriving at the input connector (first input) of block 61 switching and control. At the same time, at the first output of the switching and control unit 61, a “Upr.PK” signal is generated, which sets the diode switch 56 to the position of transmitting signals from the output of the preliminary amplifier 55 to the input of the first (transistor) terminal amplifier 57, and the signal " Upr. ”, Setting the waveguide switch 65 to the transmission position of the output signal of the first terminal amplifier 57 through the directional coupler 66 and the ferrite switch 67 to the output of the controlled power amplifier 21.

In the modes of emission of pulsed sounding signals, the microprocessor control unit 188 generates a “Boost.” Signal, which is transmitted through the GOR unit 202 to the mode control unit 22, in which, after passing through the shaper 71 and the serial to serial converter 72, it is supplied to the first inputs block of elements And ₁ , ..., And ₄ , to the second inputs of which the signals "Osl.4", ..., "Osl.7" are supplied from the outputs of the decoder 73. The output signals are Osl. 0, ..., "Osl.3" of the decoder 73, corresponding to the level of the output power of the second channel of the amplifier 21, under are applied to the inputs from the first to the fourth element OR ₄ , the inputs of which from the fifth to the eighth receive signals from the outputs of the elements AND ₁ , ..., AND ₄ . Upon receipt of the corresponding input signals at the output of the OR element ₄ , a control signal is generated, which is transmitted through the decoupling stage 84 to the control input of the key stage C ₆ , which generates the output signal “Pre-on channel 2”, which is supplied to the switching and control unit 61.

At the same time, the “Pre-On” signal is generated at the fifth output of block 61, which is fed to the control input of block 63 of high-voltage sources, which consists of a number of separate power supplies with independent stabilization, which provide cathode power, heater power, bias source power, etc.

At the end of the delay (100 s) necessary for heating the klystron heater, and when the protection circuits are enabled by the temperature of the klystron housing, the bias and excess of the cathode current, the switching and control unit 61 generates a signal “Got.2 channels.”, Which is fed to the first inputs elements And ₅ , ..., And _{8 of the} block 22 mode control. The second inputs of the elements And ₅ , ..., And ₈ are fed the signals "Osl 0", ..., "Osl 3", and their output signals are fed to the inputs OR ₅ , the output signal

which passes through the cascade of GR ₆ galvanic isolation to the control input of the key stage Kl ₇ , forming a signal "On channel 2" to enable the second channel of the power amplifier, which is fed to the input of the switching and control unit 61. In this case, the contactor is activated in block 61, and the “OnVN” command is sent to the high-voltage power supply block 63 to turn on the high voltage minus 2 kV.

At the same time, from the first output of block 61, the control signal “Upr. PC” is removed, and the diode switch 56 is transferred to the second position, in which its second output is connected to the input of the second terminal amplifier 57, and the signal “Upr. VP” is removed from the third output of block 61 , and the waveguide switch 65 is set to the transmission position of the output signal of the second terminal amplifier 58 through the directional coupler 66 and the ferrite switch 67 to the output of the controlled power amplifier 21.

After the cathode power source enters the mode (about 1 s), the “HV on” control signal is generated at the output of block 63, and after another 1 s, the channel for generating modulating pulses is turned on, and the terminal power amplifier 58 switches to the operating mode.

In addition, depending on the combination of the attenuation signals set by the mode control unit 22, the signals “Slack 10 dB” and “Slack 20 dB” are generated, which are transmitted through block 61 to the control input of the ferrite switch 67, providing step-wise adjustment of the output power of the controlled amplifier 21 power both when using the first and second channels of the power amplifier 21.

Simultaneously with the inclusion, as discussed above, of the controlled power amplifier 21, the microprocessor control unit 188 generates control signals defining the probing signal generation mode, which are transmitted along the M4 highway to the input of the serial port 179 of the complex signal generation and processing device 46, starting the encoder 174 ( see Fig. 9).

The encoding device 174, interacting with the control signal processor 170, produces the structure of the probing signals (repetition period, duration, duty cycle, number of range quanta, quantization period, effective signal base) depending on the type of signal and range scale.

In modes with a simple pulse signal, the encoder 174 generates periodic amplitude modulation signals AM2 with different repetition periods, duration and duty cycle, depending on the range scale. The number of range quanta is the same on all scales, so the size of the range quantum is proportional to the scale.

In modes using single FM signals (IFM), the encoder 174 generates periodic pulses of amplitude modulation AM2 and signals F1, F2 of intrapulse phase manipulation according to a pseudorandom law that changes each repetition period of the probe pulses.

In modes using quasi-continuous signals (SPS), the encoder 174 generates pseudorandom sequences of amplitude modulation signals AM2 and signals F1, F2 of phase shift keying of the carrier frequency with different total duration of the probe signal and a different FM sample.

In all modes, simultaneously with the modulation and manipulation signals, the encoding device 174 generates a signal “H” for blanking the shaper of the emitted signals, signals “Blank” and “BI” for blanking the devices of the receiving path, the pulse “IZV” for starting the VARU and the strobe of the BALL. To accurately match the temporal position of the emitted signal (somewhat delayed relative to the modulation signals) and the blanking signals of the receiving device, software correction (adjustment) is provided for the position of all generated signals in 50 ns increments.

The modulation, manipulation and switching signals generated by the encoding device 174 are recorded in a packed format into an external data memory (RAM 177 ₁ , ..., 177 ₈ ). Algorithms for generating signals are determined by software.

Further, the encoding device 174 goes into the signal generation cycle when the operating mode changes or when the range scale is switched.

After completion of the formation of signals, the device 46 for the formation and processing goes into the sensing cycle. In the sensing cycle, the words of the generated signals are read from the external data memory and after adjustment are transmitted at the corresponding time points through the buffer 187 to the synchronization and pairing unit 40, the signals “АМ2”, “Ф1”, “Ф2”, “Ч” are generated at the corresponding outputs , "Blank", "BI", "Izv" "Strobe ORB" for transmission to a transceiver device

tract.

In addition, the microprocessor control unit 188 generates control signals that specify the mode of change of the carrier frequency of the probing signals, arriving along the M3 line to the synchronization and interface unit 40, which generates the carrier frequency codes LF1, ..., LF7 for switching the emitter 9 of the emitted signals.

Formation of the carrier frequency of the signal (at one of 12 operating points) is carried out by direct synthesis, where the output frequency of the signal is formed as a combination of the frequencies of several crystal oscillators with their subsequent selection in the mixer unit.

The master oscillators 10 and 11 of the generator 9 of the emitted signals (see figure 2) contain the first four and the second three identical chains of a crystal oscillator KG, a diode modulator DM and a frequency multiplier by 4 and differ only in the nominal values of the operating frequencies of crystal oscillators KG ₁ , ..., KG ₇ . Switching of the diode switches DM ₁ , ..., DM _{4 of the} first master oscillator 10 is performed by the output signals of the modulators M ₁ , M ₂ upon receipt of the codes LF ₁ , ..., LF _{4 of the} carrier frequency, and switching of the diode switches DM ₅ , DM ₆ and DM _{7 of the} second master oscillator 11 - modulators M ₃ and M ₄ upon receipt of the codes LF ₅ , ..., LF ₇ . The output signals of frequency multipliers by 4 through the diode switches DKm ₁ and DKm ₂ , also controlled by the corresponding modulators M ₁ , ..., M ₄ , are fed to the inputs of the amplification-multiplier chains, the outputs of which are the output signals of the first and second master oscillators 10 and 11 .

Next, a signal with a power of at least 10 mW from the output of the first master oscillator 10 enters the amplification multiplier stage 14, where its frequency is multiplied by 8. From the output of the balanced amplifier BU _{1 of} cascade 14, a signal with a power of at least 30 mW is supplied to the first input of the transistor mixer CM ₁ the first block 15 of the frequency conversion, the second input of which through the pre-amplifier Y ₃ power receives the output signal of the second master oscillator 11 with a capacity of at least 10 mW. In the mixer CM ₁ , an output signal is generated with a frequency equal to the difference of the input frequencies, which is allocated by the output bandpass filter and fed to a two-stage balanced amplifier (BU ₃ , BU ₄ ), the second stage of which has two identical outputs. The signal from the first output is used to complete the formation of the signal of the first local oscillator f _HET1 , and the signal from the second output is used to generate the emitted signal f _s . The power of the signals at the outputs of the first block 15

frequency conversion of at least 30 mW.

The signal f _{Get1 is} completed in the first channel of the two-channel frequency multiplier 18, in which the frequency of the output signal of the first frequency conversion unit 15 is multiplied by 2, and then amplified by a balanced amplifier BU ₇ . At the output of the first channel of the two-channel frequency multiplier 18 there is a directional coupler HO ₁ with a detector and a valve. The power of the output signal f _Get1 at the first output HO ₁ (and the output of the first channel of the multiplier 18) is regulated by a potentiometer and is set from 2 to 8 mW. The control signal f _HET1-K from the second output HO ₁ is transmitted to the block 50 threshold voltage control.

From the second output of the first frequency conversion unit 15, the signal is fed to the first input of the second transistor mixer SM ₂ , in which a frequency shift is made between the emitted signal and the signal of the first local oscillator. The signal from the first output of the third master oscillator 12 is fed to the second input of the CM ₂ mixer through the preamplifier U _{9. A} signal is generated in the CM ₂ mixer with a frequency equal to the sum of the frequencies of the input signals, which is extracted by a band-pass filter and fed to a two-stage balanced amplifier (BU ₅ , Control unit ₆ ) of power, the second stage of which is the output of the second frequency conversion unit 16. The output power of the signal block 16 is not less than 30 mW. Next, the output signal of block 16 is fed to the input of the second channel of the two-channel frequency multiplier 18, in which the generation of the carrier frequency signal is completed by doubling the frequency of the input signal and amplification of the balanced power amplifiers by two stages (BU ₈ , BU ₉ ). The signal power at the output of the second channel of the two-channel frequency multiplier 18 is not less than 30 mW.

The third master oscillator 12 is based on the KG ₈ crystal oscillator, the output signal of which, after multiplying the frequency by 3, is supplied through the DM ₈ diode modulator to the input of the amplification-multiplier chain, which provides frequency multiplication by 4 and amplification in the amplifier U ₄ , after which the signal from the first the output of the third master oscillator 12 is supplied to the second input of the second frequency conversion unit 16.

Switching of the diode modulator DM _{8 is} performed by the output signal of the modulator M ₆ , to which a shaper blanking signal “H” is supplied from the output of the synchronization and pairing unit 40 through the signal presence control unit “H” 52. In the absence of the signal "H" diode modulator DM8 is closed, the output signal of the third master oscillator 12 does not enter the block 16 conversion

frequency and, therefore, the output signal of the latter does not enter the frequency multiplier 18.

Part of the crystal oscillator signal CG ₈ through the power amplifier ₅ V is applied to the third frequency converting unit 17, where the signal shaping f _op reference frequency. In the third frequency conversion unit 17, the output of the KG _{8 is} first multiplied by 3, then by 2, and fed to the CM ₃ mixer, to the other input of which a signal is supplied from the second output of the fourth master oscillator 13. A signal with a frequency difference of the input signals is allocated in the CM ₃ mixer , which is then multiplied by 4 and amplified by the amplifier U ₁₀ . The signal power f _op at the output of block 17 lies in the range from 0.8 to 1.8 mW. In addition, part of the power of the output signal of the amplifier U ₁₀ is supplied to the transistor detector (Det), the output signal f _{op-k of} which is supplied to the corresponding input of the threshold voltage monitoring unit 50.

The fourth master oscillator 13 generates a signal of the second local oscillator f _HET2 , the beginning of the formation of which is carried out in the crystal oscillator KG _{9 of the} block. Then the signal frequency is multiplied by 8, the signal is amplified and fed to the output frequency multiplier by 2, the output of which is fed to a directional coupler HO ₂ with a detector section to control the output power of the signal f _ГЕТ2 and then to the first output of the fourth master oscillator 13. The power of the output signal f _Get2 at the first output of HO ₂ lies in the range from 10 to 25 mW. The control signal f _HET2-k from the second output of HO _{2 is} supplied to the corresponding input of the threshold voltage control unit 50.

A part of the power of the KG ₉ crystal oscillator is supplied to the amplification-multiplication chain with a multiplication factor of 4, and then to the second input of the SM ₃ mixer of the third frequency conversion unit 17.

The carrier frequency signal from the output of the second channel of the multiplier 18 enters through the valve В1 to the phase manipulator (FM), which changes the phase of the signal according to the law 0, π in accordance with the control signals Ф1, Ф2 of the intrapulse phase manipulation coming from the synchronization and coupling unit 40 to the control inputs phase manipulator through series-connected amplifier converter Pr ₂ (Pr ₃ ) and acceleration circuit Usk ₂ (Usk ₃ ), which provides acceleration of the overcharge of the input capacitance of microwave diodes during the decay of the output pulses and, with Responsibly, reducing the switching time of the phase manipulator.

From the output of the phase manipulator, the signal enters the diode modulator DM ₉ ,

the control input of which through the circuit PR ₁ , Usk ₁ receives the pulses of amplitude modulation "AM2-1" generated by the synchronizer 59 of the controlled power amplifier 21 in accordance with the reference signals "AM2" amplitude modulation coming into it from the block 40 synchronization and pairing. The signals "AM2-1" from the output of the synchronizer 59 are fed to the diode modulator DM ₉ through the block 53 for monitoring the presence of the signal AM2-1, which, if absent, generates a fault signal that is received at the corresponding input of the generalized health signal generating unit 54.

The output signal of the diode modulator DM ₉ through the valve B ₂ and the directional coupler HO _{3 is} fed to the output of the block 19 AM-FM, forming a signal output f _{from the} shaper 9 of the emitted signals. The transmission loss of the 19 AM-FM unit is not more than 5 dB. With a branch control signal output _{Ho3-f with a} corresponding block is supplied to the input 50 of threshold control voltages.

In block 50 of the threshold voltage control, which contains amplifier stages on operational amplifiers and voltage comparators whose threshold voltages are set by resistors, the amplitude of the signals f _ГET1-К , f _ГЕТ2-К , f _оп-к, and f _{с-к is monitored} . If the amplitude of the monitored signal exceeds the threshold voltage, a malfunction signal is generated at the corresponding output of block 50 in the form of a pulse or potential with a logic level of “1” TTL.

Block 51 of the logical signal processing controls the presence and analysis of the correctness of the input signals LF ₁ , ..., LF ₇ . In the absence of a signal, the unit 51 generates a signal “Absent.”, And if the input signal code is prohibited, a signal “Failure” is generated.

Block 54, based on the logical processing of the output signals of blocks 50, 51, 52, 53, generates a generalized health signal of the driver, which is transmitted to the controller 47 of the communication and control channels.

The output signal f _c generated at the output of the AM-FM unit 19 of the emitter 9 of the emitted signals is transmitted to a controlled power amplifier 21, in which it is fed to the input of a preliminary amplifier 55, common to both amplification channels, which generates pulse signals amplified by 20 dB.

In the case of using the first channel of the power amplifier 21, the output signal of the pre-amplifier 55 is supplied through the diode switch 56 to the first terminal amplifier 57 (in the presence of the “PC control” signal), in which

further amplification of the microwave signal up to 10 dB in power. Next, the signal from the output of the first terminal amplifier 57 passes through a waveguide switch 65, which is set to the corresponding position by the "Upr. VP" signal, and a directional coupler 66 to the input of the ferrite switch 67, attenuating, if necessary, the power level of the output signal in accordance with a given attenuation level.

From the output of the ferrite switch 67, the probe signal through the first circulator 6, the waveguide switch 4 and the rotating connector 3 enters the antenna 1 and is radiated into space.

When using the second channel of the power amplifier 21, the switching order of which was discussed above, the output of the diode switch 56 is connected to the input of the second terminal amplifier 58 (pulse amplifying klystron), which amplifies the input signal by 30 dB. At the same time, in the signal processing unit 60, the control signals (currents) of the pin attenuator of the diode switch 56 are generated, corresponding to the frequency codes received at the first input of the unit 60 from the output of the synchronization and pairing unit 40 through the switching and control unit 61. The generated control signals provide adjustment of the input microwave power of the klystron (setting the optimal value for a given frequency).

The klystron pulsed mode is provided by a pulsed modulator 62, triggered by the front (IF) and decay (IP) clock pulses generated at the fourth output of the synchronizer 59 in accordance with the AM2 amplitude modulation pulses entering it.

Pulse modulator 62 includes under the modulators, powered by a voltage of +20 V (low potential), which are connected by transformer communication with the modulator itself, made on high-voltage field-effect transistors and under the potential of the klystron cathode. The front of the modulating pulse is formed by a transistor that discharges the capacitance of the junction of the emitter follower - the cathode of the klystron, and the decline - by the transistor charging this capacitance. To protect the transistors of the output stage during breakdowns in the klystron, a protection unit is provided, when triggered, a high-voltage operability signal is removed from the output of the block 63 of high-voltage power sources, and the “VN on” signal is removed from the output of the switching and control unit 61.

The output signal of the second terminal amplifier 58 through the circulator 64 is fed into the waveguide switch 65, and from it through the directional coupler 66 and

ferrite switch 67 enters the waveguide path of the antenna.

In the process of operation of the controlled power amplifier 21, the signal processing unit 60 generates a control signal “Correct input” from the envelope of the output signal of the preliminary amplifier 55, and the input operability is corrected along the envelope of the output signal of the first terminal amplifier 57 (when the first channel is operating) and the output signal of the detector section directional coupler 66 (when the second channel is operating) generates a “Correct Out.” signal of output health. In addition, the corresponding protection and control circuits of the switching and control unit 61 provide protection of the supply current, protection of the klystron current, bias and high voltage control, temperature control of the base, housing of the first terminal amplifier 57 and klystron of the second terminal amplifier 58, as well as output control signals: “Goth. 2 channels”, “Overheat”, and Rt temperature control signals.

These control signals of serviceability and condition of the controlled power amplifier 21, as well as control signals characterizing the state of the waveguide switch 4, are received in the control unit 22 of the operating modes of the transmitting device.

In the mode control block 22, as a result of the logical processing by the block of elements And ₉ , ..., And _{16 of the} input attenuation signals and output signals generated by the key stages Cl ₃ , ..., Cl ₇ , the attenuation control signals are generated that enter the first encoder 79 , output signals “Oslab.1r”, “Oslab.2r”, “Oslab.3r” which, as well as the control signals “Got.2 chan.”, “Repair input”, “Repair output”, “Overheat ”,“ VN on. ”Of the switching and control unit 61 are received in the first word register 77.

As a result of comparing the given signals of the position of the waveguide switch and the input control signals of the state of the waveguide switch 4, the logical signals And ₁₇ , ..., And ₂₀ and the encoder 80 form the control signals “Can. Ant.1p” and “Can. Ant.2p”, and the logic elements OR ₇ and H ₂₁ , AND ₂₂ form the signals “Off Microwave” and “Off Microwave 2”, characterizing which channel of the waveguide switch 4 is used. These signals, as well as temperature control signals, are received in the register 78 of the second word.

The reading of the control signals of the state of the controlled power amplifier 21 and the waveguide switch 4, recorded in the registers 77, 78 of the first and second words, is carried out by the read command and address signals received at the input of block 22 from the microprocessor control unit 188, after which the corresponding

the signals from the outputs of the registers 77 and 78 through the shaper 75 of the output signals are transmitted to the inputs of the galvanooptic isolation unit 202, and from it through the signal matching unit 200 to the microprocessor control unit 188. MB-U 188 forms, based on the received control signals, the status bytes of the nodes of the transmitting channel and transmits them through the external communication unit 190 along the M5 line of the RS-422 serial channel to the secondary processing device 49, in which they are displayed on the information display screen 223.

In the pause between the emitted signals, the microwave path is locked in the power amplifier 21 and in the shaper 9 of the emitted signals through the control signal chain "AM2" and "AM2-1", respectively. For additional locking of the shaper 9, the “H” signal is used, in the presence of which the master oscillator 12 operates in a predetermined mode, and in the absence of the “H” signal, the master oscillator 12 is turned off, as was discussed above. The signal "H" is generated by the device 46 for the formation and processing of complex signals synchronously with the signal "AM2".

The reflected signals received by the antenna 1 pass through a rotating connector 3, a waveguide switch 4, and a first circulator 6 into the input protection and amplification device 23, which is blocked by blanking pulses “Blank 1” and “Blank 2” for the duration of the probe pulses, providing high-quality isolation of the transmitting and receiving paths (attenuation of the signal by at least 90 dB). The pulses "Form 1" and "Form 2" are formed by electronic keys of the blocks 113 and 114 of the formation of blanking pulses of the receiving device 24 (see figure 5) upon receipt of the signal "Form" from the output of the block 40 synchronization and pairing. The “Blank 1” pulse is fed to the control anode of the cyclotron protective device, and the “Blank” pulse is fed to the control input of the LNA power supply, turning it off.

A feature of the electrostatic fast cyclotron wave electron beam amplifier (DLC) used in the input device 23 is a set of characteristics inherent only to this class of amplifiers, namely: the possibility of obtaining low values of the noise figure (not more than 3.5 dB), wide dynamic range, linear amplitude and phase characteristics, ultrafast switching of the “receive-transmit” modes. The output signal of the RAM is amplified by the LNA and then transmitted to the input of the receiving device 24. The transmission coefficient of the input device 23 in the working frequency band is at least 20 dB. The gain of the input device 23 is adjusted using the built-in

LNA controlled attenuator, providing a reduction in the gain (10 ± 1) dB). The attenuator is turned on by the “Upp.” Signal, which is generated at the output of the serial to parallel conversion unit 105 when the “Att” signal is received, from the microprocessor control unit 188. The output signal “Control Attr.” Of the logic level from block 105 is combined by the OR function with the input signal “Blank” in the element OR 107 and enters the block 110 signal conversion, the output of which the signal “Control Att.” Is generated, in the form of voltage from -1.3 V to -1.7 V with an input signal having a logical level of “1”, and voltages from 3.5 V to 4.5 V with an input signal having a logical level of “0”.

In the receiving device 24 (see Fig. 5), the signal of the input protection and amplification device 23 is fed to the input of the attenuator unit 85, with which the desired gain of the receiving device is set.

Next, the received signals are amplified in the amplifier-limiter 86, converted into signals of the first intermediate frequency in the first balanced mixer 87, to which the signal "f _HET1 " is _supplied from the output of the two-channel frequency multiplier 18, the frequency of which is lower than the frequency of the received signals by the value of the first intermediate frequency.

After amplification and bandpass filtering in block 89, the signals of the first intermediate frequency are fed to the second balanced mixer 90, which also receives the signal f _{ГЕТ2 of the} second local oscillator from the output of the fourth master oscillator 13, whose frequency is constant, while the frequency f _{pc of the} converted signals is f _ГЕТ1 - f _HET2 .

In block 25, the microwave frequency to suppress the mirror signal f _pch1 -2f first _IF bandpass filter applied in block 89, tuned to a frequency f _pch1 and to suppress spurious components at frequencies f _{nq GET2} ± f in the spectrum of the second local oscillator - the filter 91 which is tuned to frequency f _HET2 = f _pch -f _pch .

During the radiation of the probe pulses to the microwave unit 25, a blocking amplifier-limiter 86 “UHF blank” pulse is generated by the electronic key of block 112 according to the “Blank” signal, providing attenuation of at least 20 dB, and a blocking pulse supplied to the input of the discrete attenuator providing attenuation of 24 dB. In addition to blanking, a discrete attenuator 88 is used to expand the dynamic range of the receiver. The formation of signals that specify the level of attenuation of the discrete attenuator 88 is carried out

a microprocessor control unit 188, which transmits them through the GOR unit 202 to the input of the serial to parallel conversion unit 105. The output signal "DO (US)" of the logical level generated by block 105 is combined in the element 106 by the function OR with the signal "Blank" and enters the block 109 signal conversion, which generates an output current signal of 15 mA or -15 mA depending on the logical level "1" or "0" of the input signal "DO (Us)" or "Blank".

The output signals of the microwave unit 25 with a frequency f _{pch are} amplified by the selective amplifier 92 of the pre-amplifier 26 and fed to the main amplifier 27, consisting of a three-stage adjustable amplifier 94 and a three-stage amplifier-limiter 95 connected in series.

In addition, the main control unit 27 includes a BALL block 96 and a VARU block 97, the control voltages of which are supplied through the OR element 98 to the control stages of the amplifier 94.

The BALL 96 block provides noise stabilization at the output of the FC2 signals of the three-stage amplifier-limiter 95 and the VIA signal output of the video amplifier 103. The BALL gate gating signal is generated by the encoder 174 and transmitted through the synchronization and coupling block 40 to the first control input of the BALL 96, and the value of the SHARU threshold value is generated by the microprocessor control unit 188 and transmitted through the port P1.0-P1.7 of the central processor 192 to a digital-to-analog converter 203, from the output of which the control voltage “P-SHARU” is blunt unit 96 in the ball.

In general, the UCHF 27 also provides for the possibility of disconnecting the BALL block 96 by the “SHAR OFF” signal coming from the microprocessor control block 188 through the GOR block 202 to the control input of the electronic key 99. When the BALL block 96 is turned off, the necessary gain in the three-stage adjustable amplifier 94 is set the voltage level "RRU", which is formed similar to the threshold of the ball and transmitted through a digital-to-analog Converter 203 to the signal input of the electronic key 99, and from its output through the first input of the OR element 98 - to the input of the gain control of a three-stage adjustable amplifier 94.

VARU block 97 operates only in the pulsed mode of operation of the main radar transceiver channel and is turned on by the signal "Izv" generated by the encoding device 174 and received through the synchronization and pairing unit 40 and electronic

key 100 to the input enable block 97 VARU. In the modes with IFM and KNS signals, the VARU block 97 is turned off by the “VARU off” control signal, which is generated by the microprocessor block 188 and transmitted through the GOR block 202 to the control input of the electronic key 100, opening it. The duration of the VARU signal is regulated by a variable resistor of block 97, and the depth of the VARU is controlled by the voltage "VARU-G" generated by the microprocessor control unit 188 and transmitted through the DAC 203 to the input of the VARU block 97.

In the pulsed mode of operation of the radar of the main UPCH 27 using a selective amplifier 101, an amplitude detector 102 and a video amplifier 103 provides the formation of video pulses "VIa" scan along the range of the received reflected signals used to monitor the health of the receiver. To ensure maximum receiver sensitivity, the UCH 27 provides for switching the low-pass filter band and the video amplifier transmission coefficient by the signal “Signal 1”, which is generated by the microprocessor control unit 188 and transmitted through the GOR unit 202 to the control input of the video amplifier 103.

A blanking pulse “BI”, generated at the output of the synchronization and pairing unit 40 synchronously with the “Blank” signal and fed to the blocking input of a three-stage adjustable amplifier 94, provides a decrease in the gain of the receiving device during radiation of the probe pulse by at least 40 dB.

The “Repair PMR” signal of the operability of the receiving device 24, generated at the output of the threshold voltage control unit 104, is transmitted to the controller 47 of the communication and control channels through the GOR unit 202.

Further processing of the intermediate frequency signals "IF2" generated at the output of the three-stage amplifier-limiter 95 is performed in the primary processing device 39, which operates as follows.

The signal "IF2" is fed to the input of a digital receiving device 45 operating under the control of a device 46 for generating and processing complex signals, which is connected through a port 178 of the communication interface with the CPU.

The CPU 45 performs analog-to-digital signal conversion, the formation of digital quadrature components, digitally transfers the signal from an intermediate frequency to a zero frequency (demodulation), compensates for the Doppler frequency shift due to the carrier’s own speed, and digitally filters the signal with frequency decimation in filters with a comb characteristic. The width of the line

The transparency of the digital filter CPU 45 is aligned with the minimum quantum of phase manipulation.

The signal of the reference frequency F _OP enters the CPU 45 from the output of the third block 17 of the frequency conversion.

The Doppler corrections are calculated by the microprocessor unit 189 of the antenna.

The digital quadrature components of the reflected phase-manipulated signal formed at the output of CPU 45 through port 178 are then sent to a correlation-spectral signal processing device, which is eight processing clusters, each of which contains a compression unit 175 ₁ (175 ₂ , ..., 175 ₈ ), the signal processor 176 ₁ (176 ₂ , ..., 176 ₈ ) and RAM 177 ₁ (177 ₂ , ..., 177 ₈ ). Signal processing is performed in the Doppler channels, the number of which depends on the type of signal and the radar mode.

Range resolution, speed resolution and maximum Doppler frequency are determined by the performance of the computing system of the device, which is distributed depending on priorities. In particular, in modes using SPS signals, 512 range samples are always used, and in all modes with an IFM signal, with the exception of small scales, the number of range samples is 2048.

In the process of correlation processing, digital samples of the generated video signal CPU 45 are supplied to a quadrature multi-channel convolution computing device based _on compression units 175 ₁ , ..., 175 ₈ . The convolution is calculated by signal segments, the duration of which is determined by the analyzed Doppler frequency range. The number of generated segments for the signal duration is equal to: K _segment = T _s / T _segment = Nfft, where T _c is the signal duration, Nfft is the number of spectral coefficients of the fast Fourier transform (FFT).

The correlation processing device for each signal processing cluster has a 16-channel correlator (processes 16 distance elements), tunable over four range zones. The distance shift of the zone is due to the corresponding shift in the correlators of the reference signals recorded in the RAM 177 ₁ , ..., 177 ₈ at the stage of formation of the probe signal structure by the encoder 174. The total number of dynamic correlation channels in the processing cluster is 64. The signals from the multi-channel correlator go to RAM 177 ₁ , ..., 177 ₈ , in which further signal accumulation occurs.

This correlation signal processing in the current sensing cycle ends. The receiving memory bank is switched and then the signal is correlated in a new sensing cycle, and the results of the convolution of the signal of the past cycle are transmitted via the SPORT serial interface to digital signal processors 176 ₁ , ..., 176 ₈ for spectral processing.

The spectral processing of convolutions of signal segments in signal processors 176 ₁ , ..., 176 ₈ is performed in parallel with time with correlation processing using the fast Fourier transform algorithm, the dimension of which is determined by the number of signal convolutions and is equal to Nfft, and is performed sequentially for all distance elements. For each element of the distance, a set of Nfft spectral coefficients is obtained.

The next step is to find for each element the distance of the maximum spectral response in amplitude. This value is compared with the “threshold”, and the excess over the threshold becomes the amplitude of the signal of the analyzed distance element. If the mode of selection of moving targets or selection of stationary targets is set, then the specified processing procedure is carried out in the allowed Doppler frequency band.

The calculation of the threshold stabilizing the probability of false alarms caused by noise and interference is made by averaging the results of spectral correlation processing in the range-azimuth coordinates. This procedure provides an estimate of the intensity of interference in the processing channels. An estimate of the noise intensity multiplied by the “threshold constant” determines the threshold value.

This ends the spectral signal processing in the current sensing cycle. The receiving data bank is switched and the signal is spectrally processed in a new sensing cycle.

The result of the described processing is an increase in the signal-to-noise ratio for the reflected signal by tens or hundreds of times, depending on the base of the signal used. In this case, the range resolution is one quantum of phase manipulation.

Then, by sequentially polling the range channels, the range is restored and transmitted using the digital 14-bit DOUT 0-13 code under control of the USP 170 through the encoding device 174 and the buffer 186 along the M8 highway to the radar processors 41, 42.

In modes with a simple pulse signal, the signal processing is intermediate

frequencies are performed on the same hardware, but without correlation-spectral processing operations.

Continuous monitoring of the health of the device 46 is carried out using the watchdog timer 181 of the WATCH DOG type. At the same time, each FPGA and signal processor generate control pulses, which are combined in logic and fed to a watchdog timer. The absence of at least one pulse within a few milliseconds triggers the watchdog timer, which generates an error signal and gives a reset signal to the device.

Radar processors 41, 42 are designed to process radar video signals and generate data, respectively: RP 41 for the channel of the circular viewing indicator, and RP 42 for the indicator channels of the exact coordinates and the target extractor.

The IKO channel provides data generation for displaying a circular radar panorama on the screen of the information display 223 of the device 49 for secondary processing, control and display with the number of range samples up to 512 and the number of range sweeps per revolution of the antenna up to 4096.

In the radar processor 41, the following signal processing steps are implemented:

- in the IMP, KNS, IFM modes, the input of 14-bit amplitude codes with a cycle from 50 ns to 6.4 ms;

- the formation of the amplitudes of the primary range quanta from two adjacent amplitude samples according to the maximum rule to reduce detection losses during time quantization;

- processing of equidistant signals of two adjacent sweeps in range according to the minimum rule to suppress emissions from non-synchronous interference and side lobes of the compressed signal;

- compression of primary range quanta by 1, 2, 4, 8, or 16 times with the formation of an output value from the maximum of compressible amplitudes to obtain 512 output range quanta without loss of target signals;

- compression of neighboring sweeps in azimuth 1, 2, 4, 8 or 16 times with the calculation of the average value for compressible amplitudes to obtain 4096 output sweeps per revolution of the antenna while increasing the signal-to-noise ratio:

- accumulation in azimuth of a sliding window from 1 to 16 compressed sweeps to increase the signal-to-noise ratio (without shifting the angular position of the mark);

- adaptive noise suppression, which is performed by subtraction

from the amplitude of the video signal of the adaptive threshold and the cutoff of negative results. The adaptive threshold is calculated for each discrete range in a 2-parameter scheme, taking into account estimates of the average value of the interference and the estimation of the mean square deviation of the interference;

- conversion of signal amplitudes into 4-bit brightness codes in accordance with the conversion table;

- formation of output data arrays in accordance with the required format and their transmission via Ethernet (E1 highway):

- receiving over the Ethernet channel from the device 49 secondary processing, control and display commands to control the modes and parameters of the channel IKO.

All channel parameters are set programmatically via the control interface. For each of the radar operating modes, its own coefficients and parameters are set, which ensure the best processing characteristics.

The channel of the indicator of the exact coordinates of the radar processor 42 provides data for enlarged display of a portion of the radar panorama on the display screen 223. The dimensions of the portion that is displayed on the field with a format of 256 × 256 pixels are (1/8 scale × 22.5 °) or (1 / 16 scales × 11.25 °). By construction, algorithms and format of the output data, the data processing in RP 42 is identical to that performed in RP 41, but differs from it in the values of the processing parameters.

The channel of the target extractor of the radar processor 42 provides the detection of targets and the transfer of forms with their parameters to the device 49 secondary processing for automatic tracking.

RP 42 implements the following stages of radar signal processing for the EC channel:

- operations for the normalization of analog video signals, similar to operations performed on the IKO channel, but with specific settings for compression and interference suppression coefficients, providing maximum measurement accuracy;

- automatic capture of targets in the detection zone according to the criterion that the amplitude exceeds the normalized signal of the threshold level. The detection zone can have either one section of an arbitrary shape, or for cases of complex interference conditions, be set by detection gates with the number 50 per antenna revolution coming from the auto tracking system;

- automatic measurement of target coordinates according to the rules of the middle or center of gravity, as well as their "mass" and length in range and azimuth;

- target detection using the criterion of the angular size of the pack and rejecting targets at the upper and lower boundaries of the size in range and azimuth;

- formation of output arrays of target forms in accordance with the required format and their transmission via Ethernet (E2 trunk);

- receiving via Ethernet channel commands for controlling the modes and parameters of the EC channel operation.

The maximum number of detected targets reaches 40 at one azimuth and 200 per revolution of the antenna. For the navigation mode, it is possible to set automatic prohibition zones. For the target designation mode, it is possible to set zones for automatic capture of targets and the ability to set the strobe for specific targets. All parameters of the ITK / EC channel are set programmatically through the control interface. For each of the radar operating modes, its own coefficients and parameters are set, which ensure the best processing characteristics.

The output data of the raster channels (IKO and ITK) are formed in polar coordinates: bearing-range and represent a set of sweeps in range, each of which is represented by a set of consecutive in range 4-bit amplitudes, packed in 32-bit words with the attached value of the current antenna bearing , which enters the RP 41, 42 from the microprocessor unit 189 of the antenna through the block 204 conversion of interfaces on the serial channel RS-422 (highway M2).

For the best use of network resources, the output data of the ITK and ET channels are combined into blocks formed within the fixed “slicing” sectors attached to the bearing. The size of the “slicing” sectors depends on the antenna rotation speed and is set by the operator using the front panel 225 controls of the remote terminal 218. When transmitting, the output data of the ITK and EC channels are combined into common data blocks.

In the process of operation of the radar processors 41, 42, the distribution of tasks between their functional units is as follows.

FPGA 163 of radar interfaces receives radar data from complex signal generation device 46 (or, in standby channel mode, from ADC 165), signals from the current bearing of the antenna from microprocessor unit 189 of the antenna, performs preliminary signal processing (range and azimuth compression, suppression non-synchronous interference) and provides data to the DSP 160.

DSP 160 performs threshold signal processing for the channel IKO (ITC) and partial signal processing for the channel EC. The processed sweeps of the IKO channel (TKI) are transmitted to the DSP 161. Partially processed sweeps of the EC channel are transmitted to the DSP 162.

DSP 161 provides communication with device 49 for secondary processing, control and display of information via the Ethernet interface, receives and parses commands from device 49, generates commands for DSP 160 and 162 and FPGA 163, 164, receives data from them, and converts output data in accordance with a given conversion table into 4-bit values, it packs 8-sample data into a 32-bit code word and sends it to device 49 via FPGA 164 and Ethernet LAN controller 43 (44) to display an information display 223 on the screen.

The DSP 162 receives partially processed scans from the DSP 160 and completes the threshold processing of these scans in accordance with the interference suppression parameters set for the EC channel. Next, the formation of the primary marks of the goals is carried out in accordance with the set targeting parameters and their issuance to the DSP 161.

FPGA 164 provides an interface to the mezzanine module 43 (44) of external communication, which provides hardware support for the Ethernet 10 BASE-T (twisted pair) interface. The ROM of the mezzanine module 43 (44) stores the unique address of the module on the Ethernet network.

Computing means of the device 49 secondary processing, control and display provides the following tasks of the secondary processing of radar information:

- the formation of zones of prohibition of auto tracking;

- the formation of the strobe escort in automatic and semi-automatic modes;

- implementation of algorithms for semi-automatic tracking of goals and setting goals for automatic tracking;

- determination of the current distance to the target and the current bearing to the target;

- measurement and display of coordinates of targets indicated by the operator on their radar image;

- measurement of landmark parameters in the polar coordinate system;

- implementation of the goal classification algorithm.

In navigation mode (ARPA), the implementation of the algorithms for detecting trajectories, updating the parameters of the trajectory in the process of linking its new marks is provided, the trajectory parameters are extrapolated at the time of the next measurement, the updated parameters of the target’s movement, the true course and speed of the target, etc. are determined. Data on course and speed tracking targets are displayed on the screen of the information display 223.

The backup radar transceiver channel is designed to solve the problems of navigation and the detection of surface targets in case of failure of the main transceiver channel.

The backup transceiver is turned on by the signals “Can.imp.on.” And “Can.ant. 2p”, which are generated by the microprocessor control unit 188 upon receipt of the corresponding command from the device 49 of the secondary processing, control and display and are transmitted to the mode control unit the operation of the transmitting device through the block 200 matching signals and block 202 galvanic-optical isolation. In the block 22 control modes these signals through the shaper 71 of the input signals are supplied to the Converter 72 of the serial code in parallel.

When the signal “Kanimp.onkl.” Is received, the control signal is generated at the output of the converter 72 and supplied through the cascade ГР _{1 of} galvanic isolation to the control input of the key stage Kl ₁ , which is activated by supplying a voltage of ± 27 V to the input of the source 32 of the secondary power supply and the power inputs of the pulse transmitter 33 and the standby receiver 34.

According to the signal “Kanant.ant.2r”, the signals “Kanimant.ant.ant.” And “Kan.sl.eq.” Are generated at the outputs of the converter 72, providing, as discussed above, the installation of the waveguide switch 4 in a position in which the second (antenna) input-output is connected via the fourth input-output to the second circulator 7, and the third output (the channel of the antenna equivalent connected to the matched load 5) is connected through the first input-output to the first circulator 6.

Next, the microprocessor control unit 188 generates a packet of control signals specifying the operating mode of the backup transceiver device, which are transmitted along the M1 highway of the RS-422 serial channel to the control and synchronization unit 38 (see Fig. 7), in which they pass through the transceiver 152 to the serial micro computer 132.

Codes of the current bearing of the antenna ("TIN") transmitted by microprocessor

block 189 antennas on the M2 highway of the RS-422 serial channel, enter the microcomputer 132 through the transceiver 153.

Micro computer 132 based on the information received performs the following operations:

- generates synchronization modes and commands for controlling the operation of the backup transceiver;

- sends and writes generated strobes to the FPGA registers 133 and to the register 146 of the mode setting commands;

- writes to FPGA 133 the value of the pulse repetition period "IZP", and the pulse duration "Blank", "Izv";

- writes to the FPGA 133 the value of the pulse delay "IZP";

- generates voltage values "RRU", "VARU-G", "VARU-D" with the recording of voltage codes and addresses in block 148 of the DAC;

- generates the voltage value "RPC" with the recording of the voltage code and address in the built-in computer 132 DAC;

- reads the strobe reads from FPGA 133 and register 147 information about the health of the PPU blocks, analyzes it and transmits through the transceiver 152 serial channel to the controller 47 of the communication and control channels.

To ensure the operation of the pulse transmitter 33, the following TTL level control signals are generated:

- "IZP" is the transmitter start pulse generated by FPGA 133 and transmitted through buffer 149;

- “IZL” - the signal that the transmitter is switched on to the microwave power radiation mode generated by the FPGA 133 and transmitted through the buffer 149;

- “RD1”, “RD2” - signals that control the selection of the duration of the generated pulses generated at the output of the register of 146 mode setting commands;

- “0Р”, “1Р” - signals that specify the level of attenuation of the output power, generated at the output of the register 146 commands installation modes.

The transmitter unit 33 is a pulsed magnetron transmitter operating without tuning the carrier frequency in three modes for the duration and duty cycle of the emitted microwave pulses, with a pulse power of at least 8 kW.

The “IZP” pulse is supplied to the transmitter modulator, which is based on the principle of amplification of a modulation pulse formed at a logical level by a power amplifier, the load of which is a magnetron. Formation

signals of the required duration and the conditions for their arrival on the modulator are carried out by the modulator control unit, which, depending on the signals “RD1”, “RD2”, which is a binary combination of DC voltage of high TTL level (logical “1”) and low TTL level (logical “ 0 ”) generates short, medium or long modulation pulses.

According to the signal “IZL”, which comes from the control and synchronization unit 38, a high-voltage modulator power source is turned on, the voltage of which is supplied to the modulator key circuit, which generates a modulating pulse with an amplitude of up to 8 kV and arrives at the magnetron cathode. Under the influence of a modulating pulse, the magnetron generates a microwave signal, which through a directional coupler 35 enters the power attenuation switch 36, and from its output through the circulator 7 and the waveguide switch 4 into the antenna path and is emitted by the antenna 1 into space.

The switch 36 is a ferrite device with one input and two outputs, between which the input signal power is divided in a proportion depending on the magnitude of the control current supplied to the switch from the output of the switch control unit 37. Block 37 is controlled by two commands “0P” and “1P”, which are generated at the output of register 146 of the command settings for the control and synchronization unit 38 in the form of a combination of binary signals “1” and “0”, depending on the value of which at the output of block 37 control signals are generated corresponding to the attenuation of the signal by 0 dB, 10 dB or 20 dB. In 0 dB mode, the microwave signal passes through switch 36 without attenuation, with the exception of losses in the ferrite elements that make up the switch.

The control signals "K0R" and "K1P", which determine the attenuation of the emitted signal, from the outputs of the control unit 37 to the switches are received through the block 136 matching the signals working out and health in the FPGA 133.

In addition, during the operation of the transmitter, the modulator control unit generates a control signal “IZP control.”, Confirming the arrival of the pulse “IZP” to the modulator, a signal “Got.” (Readiness), allowing to send a signal “IZL”, a signal “Isp. .PRD ”(transmitter serviceability),“ MI current ”signal (magnetron current) and“ BIP ”blanking pulse, equal in duration to the emitted pulse, but with opposite polarity. The control signals "IZP control.", "Got." And "Isr.PRD" are transmitted to the FPGA 133 through block 136 coordination

input signals working out and serviceability, and the signal "BIP" - through the input driver 137.

Upon receipt of the appropriate control signals, the FPGA 133 generates control signals "KIZP", "KIZL", "KBIP" and transmits them to the microcomputer 132. The signal "Current MI" is recorded in the register 147, from which it is read by the reading strobe and transmitted to the microcomputer 132 The microcomputer 132 processes the control information and generates a packet of status control signals, which transmits to the controller 47 communication and control channels along the M1 highway.

Upon receipt of the “BIP” signal, the FPGA 133 generates a “Blank” signal, which is transmitted through the output amplifier 143 to the control input of the amplification unit 126 for microwave and inverter (see Fig. 6), providing locking of the receiving device 34 for the duration of the radiation of the probe pulse, as well as the signal "NOD-R" transmitted through the output amplifier 142 to the block 40 synchronization and pairing.

In addition, to ensure the operation of the FPGA receiving device 133, in accordance with the set delay, it generates an “Izv” impulse for starting the VARU “Izv” pulse transmitted to the block output through the buffer 149, and the microcomputer 132 provides reading from the register 146 and issuing 38 commands to the output of the block “RRU / AGC”, “RPC / AFC” for setting the gain and frequency control modes and the “Full Pol.” Command for switching the receiver band.

The values of the gain control voltages (“RRU” or “VARU-G”, “VARU-D”) are formed by the microcomputer 132, and their transmission to the output of the block is performed through the DAC block 148 upon receipt of the corresponding reading gates.

The value of the voltage "RPC" is formed at the output of the DAC, which is part of the microcomputer 132, and its transmission to the output of block 38 is made through the shaper 151 voltage RPC.

The standby receiving device 34 operates as follows.

The reflected signal received by the antenna is fed to the input of the cyclotron protective device 125, similar to a DZU, which is used in the protection and amplification device 23. Next, the signal is supplied to the amplification unit 126 for microwave and inverter, in which it is amplified by the first low-noise amplifier, passes through the filter of the suppression of the mirror channel and enters the first balanced mixer, which _{selects the} first intermediate frequency f _pc1 = f _c -f _G1 .

The signal f _{G1 is} generated by the block 128 of the first local oscillator, made in the form of a voltage-controlled oscillator (VCO). The voltage controlling the VCO 128,

fed from the automatic frequency control unit 130. After filtering and amplification, the VCO signal is supplied to the output power divider of block 128, from which the signal f _G1 is supplied to both the signal mixer of the amplification block 126 for microwave and inverter, and to the mixer of the AFC block 130.

Maintaining the output frequency of the mixer of the AFC unit 130 is carried out by the AFC system, which monitors the drift of the frequency of the signal f _{from the} transmitter 33, which is fed to the AFC input from the second output of the directional coupler 35, and the temperature drift of the frequency of the signal f _Г1 generated by the block 128 of the first local oscillator. In block 130, the signal of the transmitter 33 is preliminarily attenuated to the level of operation of the mixer and then fed to the mixer of the AFC unit 130, which, in the holding mode, allocates an intermediate frequency f _Г1 . After amplification, the signal from the output of the AFC mixer enters the frequency divider, where it is divided up to the frequency at which the frequency discriminator of the AFC operates. Then the signal is limited in the amplifier-limiter and is fed to a frequency detector that generates pulses whose amplitude change is proportional to the deviation of the signal frequency from the reference frequency f _et . The amplitude of the output signal of the frequency detector is periodically calibrated (Δt = 1 min) using a highly stable frequency generator. In the holding mode f _AFC = f _ET ± Δf _AFC , where Δf _AFC is the error of the AFC.

The operation of the AFC circuit is controlled programmatically with the output of a signal to the VCO, control signals to a reference generator, and search and capture status signals “Capture AFC” to the output of the receiver, from which these signals are transmitted to register 147 of the control and synchronization unit 38, and are read from it reading strobe and enter the microcomputer 132.

In the manual frequency adjustment mode, the unit 130 is turned off by the control signal “RPC / AFC” from the output of the register 146, and the voltage “RPC” generated at the output of the driver 151 is supplied to the control input of the block 128 of the first local oscillator.

After converting in block 126 to the first intermediate frequency, the processed signal is amplified by the second LNA and, after filtering, is fed to the smooth attenuators of the VARU. Adjusting the duration (from 10 to 70 μs) and depth (from 20 to 40 dB) VARU is made by the signals "VARU-D" and "VARU-G", coming from the output of block 148 DAC.

Then, after filtering and amplification by the amplifier of the first intermediate frequency, the signal enters the smooth attenuators of the switchgear with a depth of at least 50 dB. Manual

gain adjustment is carried out by applying an external control voltage "RRU" to the DC amplifier of the RRU. Instead of the switchgear, a circuit for automatically adjusting the gain in noise (ARUSH) can be applied, switched by the signal "switchgear / AGC" from the output of register 146.

Then, at the second mixer of block 126, the signal is converted to the second intermediate frequency: f _pc2 = f _pc1 -f _G2 , where f _G2 is the frequency of the second local oscillator generated by the second local oscillator unit 129, which is made in the form of a generator on surface acoustic waves.

At the second intermediate frequency in the block 127 amplification and conversion to the video frequency, the signal is switched in strips depending on the duration of the generated pulse of the “Pol. Pol.” Band.

In block 127, at a frequency f _pc2 , a linear-logarithmic amplitude characteristic of the receiver is formed using the logarithmic section of the video amplifier at about 50 dB for the amplifier output signals of 0.632-200 mV. For level signals <0.632 mV, the amplifier operates in linear mode.

After detection and filtering in the low-pass filter at the output of block 127, a video signal "Video-P" is generated, which is transmitted to the output of the receiving device 34.

From the other output of block 127 (via the repeater), the Video-P signal is removed for the ARUSH circuit and receiver operability control circuits. The output signal of the serviceability of the receiver “Isp. PU” is transmitted through the block 136 matching the input signals of mining and serviceability in the FPGA 133.

FPGA 133 generates a control signal "KIZV" and control signals of the status of the receiving device and transmits them to the microcomputer 132, which processes them, reads from the register 147 the status signal of the AFC unit and generates a packet of control information, which is transmitted to the controller 47 of the communication and control channels .

In the controller 47, the received control information about the state of the pulse transmitter 33 and the standby receiving device 34 is processed by the microprocessor control unit 188, which generates the status bytes of the nodes and transmits them along the M5 line to the secondary processing, control, and indication device 49, where the control data is in generalized or expanded form (depending on the commands entered by the operator) are displayed in the control window of the information display 223.

Video pulses “Video-R” of the scanning range of the received reflected signals generated at the output of the receiving device 34, as well as pulses of the initial reference of the scanning range “NOD-R”, and pre-emptive triggering pulses “UIZP”, formed by the control and synchronization unit 38, are received in the block 40 sync and pairing. Upon receipt of the UIZP pulses, unit 40 prepares for receiving the Video-R information signals and the NOD-R clock signals, which are transmitted to the radar processors 41, 42.

In the radar processors 41, 42, the information video signal is converted into a digital analog-to-digital converter 165 and received through the FPGA 163 of the radar interface, synchronized by the NOD-R pulses, to the DSP 160, and from it, as discussed above, to the DSP 161 and 162 The data arrays formed in the radar processors 41, 42 are transmitted along the Ethernet LANs E1, E2 to the video processor 220, which provides reception and processing of information for display on the display 223.

In the functional control mode, the correct operation of both the radar transceiver path as a whole and its individual devices is checked.

To ensure control of the transceiver path to the second output of the directional coupler 8, a delay line of the reflective type is connected, the output of which is connected to the signal input of the microwave unit 25. The delay line simulates the reflection of sounding signals from surrounding objects.

To introduce a noise control signal into the receiving path, a noise generator 31 is connected to the input protection and amplification device 23. The block of the noise generator consists of a noise generator, a block of attenuators with attenuations of 0.3 and 6 dB, with the help of which the level of noise power, a ferrite valve and a directional coupler are set. The ferrite valve protects the noise generator from leaking power of the transmitting device. The directional coupler provides a branch from the noise generator path of such a part of the noise signal power that provides a noise level at the receiver output that is twice as much as its own noise level.

The noise generator 31 is turned on by the “FC” (functional control) or “GSh” signals, which are generated by the microprocessor control unit 188 and transmitted to the receiver control signal generation block 28, or by pressing the “GSh On” button. These signals are fed to the inputs.

element OR 108, which upon receipt of any of them generates a control signal that opens the electronic key 111, through which the noise generator 31 is powered from the stabilizer 123.

Checking the operation of the radar is carried out by first turning on each of the radiation modes of the pulse signals (with parameters that vary depending on the range scale), and then each of the radiation modes of the IFM and SPS signals.

At the same time, in each mode, the serviceability of the transmitting and receiving tracts devices is checked by the presence of the corresponding control signals generated, as was discussed above, during the standard operation of the radar and displayed on the information display.

In pulsed operating modes, the VIA signal is used to control the signal processing path, which is generated at the output of video amplifier 103 and supplied to radar processors 41, 42 through synchronization and interface unit 40.

In the modes of emission of complex signals, the processing path is checked by generating at the output of the digital receiving device 45 control signals “IF (CS)” at the second intermediate frequency in the form of IFM and SPS signals with a time-varying delay.

The control signal "IF (KS)" through the block 30 switching control signals (opened by the control signal "On.Imit." Coming from the controller 47) and the divider 93 frequency 1: 1000 is fed to the control input of the selective amplifier 92, and from it to the main amplifier 27 intermediate frequency. After a full processing cycle, the control signal is displayed on the screen of the information display 223 in the form of a spiral.

The control of the video signal path is carried out by generating in the block 40 synchronization and pairing of the control video signal with a constant delay, and the control of the video signal processing path by generating control signal signals in the input circuits of the radar processors 41, 42.

Thus, due to the possibility of generating various types of probing signals with tunable parameters, the proposed radar provides high information content and reliability of target detection in a wide dynamic range of signals at various distance ranges, regardless of the conditions of the jamming environment.

Hardware and software implementation of signal conditioning devices and

control modes provides ample opportunity to vary the parameters of adjustment and tuning with continuous monitoring of all stages of the passage of signals.

The implementation of the primary processing device in the form of a program-controlled multi-channel device for correlation and spectral signal processing with the number of Doppler channels depending on the type of signal and radar mode allows digital processing of signals at an intermediate frequency and thereby eliminates information loss that occurs in the case of pre-conversion to video frequency.

The use of radar processors based on digital signal processors and interacting via standard interfaces with a radar computing system that provides secondary processing of information to generate displayed data allows the implementation of various algorithms for solving lighting problems, target designation and navigation with adaptive suppression of various interference.

The industrial applicability of the proposed radar is ensured by the possibility of its manufacture according to the above description and drawings on the basis of well-known components and technological equipment and use on floating equipment for various purposes to illuminate the situation, navigation and other tasks.

Information sources

1. Guide to radar, ed. M. Skolnik // Translation from English. Volume 4. M :, Sov. Radio, 1978.

2. US Patent No. 4.338.604, IPC G 01 S 13/24, 7/28, publ. 07/06/82

3. RF patent No. 2037842, IPC G 01 S 13/02, publ. 06/19/95

4. RF patent No. 21242221, IPC G 01 S 13/42, publ. 12/27/98, prototype.

5. Yu.A. Budzinsky, S.P. Kantyuk. Electrostatic amplifiers. - Electronic equipment / ser. Microwave technology //. - 1993 - No. 1.

6. "Devices and methods of digital and analog signal processing" / Interuniversity collection. // Voronezh: Polytechnic Institute. - 1988

Claims (1)

A radar station containing an antenna kinematically connected through a rotary connector with an antenna drive, a shaper of emitted signals, a controlled power amplifier, a receiving device, a primary processing device and a secondary processing, control and display device, characterized in that an input protection device is additionally introduced into it and amplification, the control unit of the operating modes of the transmitting device, the controller of the communication and control channels and the controller of the drive antenna, while the receiving device yours contains a series-connected amplification block at an ultra-high frequency (microwave) and double conversion to an intermediate frequency (microwave block), the input of which is connected to the output of the input protection and amplification device, a preliminary amplifier of an intermediate frequency (UPCH) and a main amplifier, made with the possibility of manual adjustment gain (RRU) or temporary automatic gain control (VARU) and with the possibility of noise automatic gain control (BAR), as well as a unit for generating control signals of the receiving device In addition, the primary processing device contains a synchronization and interface unit, a radar processor of the channel of the circular viewing indicator (IR) and a radar processor of the channels of the indicator of exact coordinates (ITC) and the target extractor (EC), the information outputs and control inputs of which are connected through the controllers of the local computer network ( LAN) Ethernet with a device for secondary processing, control and display through the corresponding LAN backbones, as well as interacting through the interface channel of information exchange a digital receiving device, the input of which is connected to the output of the intermediate frequency signals of the main amplifier, and a device for generating and processing complex signals, the information output of which is connected via the radar data input line to the inputs of the digital interfaces of the radar processors of the IKO channel and the channels ITK and EC, the outputs of the formation device and processing complex signals on which the start-up signal of the VARU, the gate signal of the BALL and the blanking signal of the main amplifier are generated, through the synchronization unit and with the voltages are connected to the corresponding control inputs of the main amplifier, and the output on which the signal of the blanking of the input stages of the receiving path amplification is generated is connected through the synchronization and pairing unit to the corresponding control input of the receiver control signal generation unit, at the corresponding outputs of which are blanking pulses blocking the input the protection and amplification device and the microwave unit for the duration of the sounding signal, the control input of the microwave unit by the enable signal additional attenuation through the block for generating control signals of the receiving device is connected to the corresponding output of discrete signals of the controller of communication channels and control, and the outputs of the controller of communication channels and control, which generate voltage manual gain control, adjust the depth of the gain and adjust the threshold of the ball, the outputs of the discrete disconnect signals of the gain and the BALL and the input of the health signal of the receiving device are connected to the corresponding control inputs and the output of the main amplifier, except , the generator of emitted signals contains four master oscillators, three frequency conversion units (BFC), an amplifier-multiplier cascade, a two-channel frequency multiplier, an amplitude modulation and phase manipulation unit (AM-FM unit), and a driver control unit, the output of the first master oscillator being amplified the multiplying cascade is connected to the first input of the first BPC, the second input of which is connected to the output of the second master oscillator, the first output of the first BPC is connected to the input of the first channel of the two-channel mind frequency spreader, at the output of which a signal of the first heterodyne frequency is generated, which arrives at the first heterodyne input of the microwave unit, the second heterodyne input of which supplies a signal of the second heterodyne frequency from the first output of the fourth master oscillator, the second output of the first LPC connected to the first input of the second LPC, the second input which is connected to the first output of the third master oscillator, and the output is connected to the input of the second channel of the two-channel frequency multiplier, the output of which is connected to the signal input of the AM-F unit , the inputs of the third BPC are connected to the second outputs of the third and fourth master oscillators, and the output at which the reference frequency signal is generated is connected to the reference input of the digital receiving device, the control inputs of the AM-FM block, to which the signals of intrapulse phase shift keying are received, are connected through the block synchronization and pairing with the corresponding outputs of the device for the formation and processing of complex signals, the output of the pulses blanking the shaper of which through the block synchronization and pairing and block The driver circuit is connected to the control input of the third master oscillator, the outputs of the synchronization and interface unit, on which the carrier frequency codes are generated, are connected to the corresponding switching inputs of the carrier frequency setting of the first and second master generators and to the corresponding inputs of the driver control unit, to which the control outputs are also connected signals generated in the AM-FM unit, a two-channel frequency multiplier, a fourth master oscillator and a third BPC, and the output of the control unit is formed The driver, on which the conditioner of the driver is generated, is connected to the corresponding input of discrete signals of the controller of communication channels and control, in addition, the controlled power amplifier contains a preliminary amplifier, the input of which is connected to the signal output of the AM-FM unit, and the output through the diode switch is connected to the input the first transistor terminal amplifier and with the input of the second terminal amplifier, made on a pulse amplification klystron, as well as a pulse modulator, the output of which is under The key to the modulating input of the second terminal amplifier is a synchronizer, a signal processing unit, a switching and control unit, a power amplifier circulator, a waveguide switch of a power amplifier, a directional coupler with a detector section, and a ferrite switch, the first control input of a diode switch to which a control signal is input by switching channels, it is connected to the corresponding output of the switching and control unit, and the second control input to the output of the signal processing unit, on which the control current of the attenuator of the diode switch is formed depending on the carrier frequency code, which is supplied to the first input of the signal processing unit from the synchronization and interface unit through the switching and control unit, the control outputs of the envelope signals of the pre-amplifier, the first, are connected to the inputs of the signal processing unit from the second to the fourth the terminal amplifier and the detector section of the directional coupler, and the second output of the signal processing unit, on which the health signals of the input and output are generated an ode of the controlled power amplifier, through the control unit of the transmitting device’s modes, connected to the corresponding inputs of discrete signals of the communication and control channel controller, the output of the first terminal amplifier is connected to the first input of the waveguide switch of the power amplifier, the second input of which is connected through the circulator of the power amplifier to the output of the second terminal amplifier, the control input is connected to the corresponding output of the switching and control unit, and the output is connected through a directional coupler with a detector section with an input of a ferrite switch, the output of which forms the signal output of the controlled power amplifier, and the control input is connected to the output of the switching and control unit, on which signals of stepwise adjustment of attenuation of the output power are generated, the first input of the synchronizer is connected to the output of the synchronization signal of the switching and control unit , its second input through the synchronization and pairing unit is connected to the output of the device for the formation and processing of complex signals, on which the specifying amplitude modulation signal, and the first synchronizer output, on which the amplitude modulation pulses are generated, is connected through the driver control unit to the amplitude modulation control input of the AM-FM unit of the emitter of the emitted signals, the synchronization inputs of the preliminary amplifier are connected to the outputs from the second to the fourth terminal amplifier and pulse modulator, inputs of the switching and control unit, to which control signals of power on, channel on in the first or second terminal amplifiers and signals that specify the level of attenuation of the output power, as well as the outputs of the control readiness and status signals through the control unit of the operating modes of the transmitting device are connected to the corresponding outputs and inputs of the discrete signals of the controller of communication channels and control, the interface inputs and outputs of which are connected by means of corresponding highways of serial channels RS-422 with a device for secondary processing, control and display, with a device for forming processing complex signals, with radar processors of the IKO channel and the channels of ITK and ETs, with a synchronization and pairing unit and with an antenna drive controller, inputs of the antenna drive controller, to which information signals from the antenna drive arrive and the outputs of the drive control signals are connected to the corresponding outputs and inputs antenna drive, and the interface input-output of control and monitoring signals is connected via the RS-422 serial line trunk to a secondary processing, control and display device, except e of this, the first and second circulators are additionally introduced, a waveguide switch, the antenna input-output of which is connected to the antenna through a rotating connector, and the antenna equivalent channel output is connected to the matched load through the first directional coupler, a pulse transmitter, a backup receiving device, a control and synchronization unit , a power attenuation switch, a switch control unit and a second directional coupler, wherein the input-output signals of the main receive-transmit channel of the waveguide of the first switch through the first circulator is connected to the signal output of the controlled power amplifier and to the signal input of the input protection and amplification device, the input-output of the signals of the backup receive-transmit channel through the second circulator is connected to the output of the power attenuation switch and to the signal input of the backup receiving device, and the control the input to which the signals of setting the waveguide switch to the appropriate position, and the control output of the state signals of the waveguide switch Without the control unit, the modes of the transmitting device are connected to the corresponding outputs and inputs of the discrete signals of the controller of the communication and control channels, the signal output of the pulse transmitter is connected to the input of the second directional coupler, one output of which is connected to the signal input of the power attenuation switch, and the other to the input of automatic frequency adjustment the backup receiving device, the control input of the power attenuation switch is connected to the output of the switch control unit, the inputs to otogo by signals that specify the level of attenuation, and the outputs of the control signals are connected to the corresponding outputs and inputs of the control and synchronization unit, which is connected to the controller of the communication and control channels through two lines of serial channels RS-422, on one of which control and control signals are transmitted, and on the other - the codes of the current bearing of the antenna, the outputs of the control and synchronization unit, on which the transmitter trigger pulses, radiation pulses and duration adjustment signals are generated the radiation pulse, as well as the inputs to which the blanking pulses of the transmitter and the signals of its readiness and serviceability are connected, are connected to the corresponding inputs and outputs of the pulse transmitter, the outputs of the control and synchronization unit, on which the blanking pulses of the backup receiving device are generated for the duration of the radiation of the probe pulses, pulse start of VARU, voltage for adjusting the depth and duration of VARU, voltage for manual frequency adjustment, signal for switching from manual to automatic adjustment for hours frequencies, switchgear voltages, a switching signal from manual to automatic adjustment of the noise level, as well as the input to which the intermediate frequency capture signal is supplied, are connected to the corresponding control inputs and the control output of the backup receiving device, and the signal output of the backup receiving device, on which scan video pulses are generated by the range of the received reflected signals, and the output of the control and synchronization unit, on which the pulses of the initial reference of the sweep range are formed, through bl ok synchronization and pairing are connected to the inputs of the analog interfaces of the radar processors channel IKO and channels ITK and EC.