RU523U1 - Adaptable device for debugging microcontrollers - Google Patents

Abstract

1. Adaptable device for debugging microcontrollers, containing the address-data interface (NAD) and control signals (IMS) for communication with instrumental personal computers, RAM of user programs (RAM), RAM of control points (RAM), control signal generator (FSU), an address bus switch (CAB) and a data bus switch (CAB), and the first group of IAD outputs is connected to the address inputs of OZUPP and OZUKT, as well as to the CAB output, the inputs of which are connected to the external address bus (BAS) of the debugged microcontroller device (MK ), and the second group of inputs and outputs of the IAD is connected to the input-output of the RAM data, the input of the RAM and the first group of the outputs of the CDM, the second group of inputs and outputs of which is connected to the external data bus (BDM) of the MCU, the output of the ICS is connected to the first group of inputs FSU, the second group of inputs of which is connected to the input control bus (ШУВх), and the output of the FSU is connected to the control inputs of RAM, RAM, KShA and KShD, characterized in that a programmable unit (PB) is inserted into it, the first group of inputs of which is connected to the input IMS, the second group of inputs - with OZUKT output, the third group of inputs is from ШУВх, the first group of ПБ outputs is connected to the output control bus (ШУВых), the second group of outputs to a backup output control bus (ДУУВых), and the third group of outputs to the third group of FSU inputs. 2. The device according to claim 1, characterized in that the programmable unit comprises a sync generator (SG), a register and a programmable combinational circuit (PCB), the first, second and third groups of inputs of which are the corresponding input groups of the PB, the fourth group of PCB inputs is connected to the output of the register, is�

Description

Adaptable device for debugging microcontrollers

The technical field to which the utility model relates.

The inventive utility model relates to the field of computer technology, namely, debugging devices for the software and hardware of microcontroller devices (MCU), made on the basis of microprocessors (MP) or single-chip micro-computers (OMEMS).

State of the art

Known devices in the form of processors that implement the function of debugging microprograms by using a circuit comparing the breakpoint address with the current address of the control memory, as well as circuits that turn off the clock when a match is detected (Japanese Application No. 61-198339, G06F 11/28).

The disadvantages of the known device are the excessive complexity of the solution associated with the creation of a specialized processor; narrow scope - only debugging microprograms of partitioned microprocessors using only a clock input to stop the microprocessor.

The closest in technical essence to the claimed device is a debugging device for a microprocessor system (European application N 0251481, filing date May 22, 1987, class G06F 11/00, 1988), containing an instrumental computer having a user interface, a ROM emulator and a unit monitor, which uses the interrupt channel of the target microprocessor to organize the step-by-step mode. The following disadvantages are characteristic of the indicated device: - the target processor is controlled via the interrupt channel, which reduces the capabilities of the target processor by one uro-MI4-G06 F 14g / hr interrupt;

- debugging of the developed MCU is possible only for target processors having an interrupt channel;

-the presence of the reserved area in the RAM of the user under the monitor reduces the amount of user program;

- there is no possibility of a tactless check of a microprocessor (MP).

Utility Model Essence

The basis for creating the claimed base model is the task of creating such an adaptable device for debugging microcontrollers, which would ensure the achievement of the following technical results:

- high-quality expansion of the scope by providing debugging of any microprocessors with an open data address bus and at least one of the inputs: Ready (readiness), C (clock) or Int (interrupt);

-constancy of hardware implementation for debugging various microprocessors and microcomputers with a minimum amount of adjustment software instrumental PC;

-the ability to cycle and command debug MCU, which allows you to diagnose the target processor;

- ease of implementation.

The task is achieved by the fact that in an adaptable device for debugging microcontrollers (AUOM), containing address-data interfaces (NAD) and control signals (IMS) for communication with the instrumental computer, random access memory of user programs (RAM), random access memory of control points (OZUKT), a control signal generator (FSU), an address bus switch (KSA) and a data bus switch (KSHD), the first group of NAD outputs connected to the address inputs of OZUPP and OZUKT, as well as to the KSA output, input which are connected to the external address bus (BAS) of the debugged microcontroller device (MCU), and the second group of I / O NAD is connected to the input-output of OZUPP data, the input of the OZUKT and the first group of I / O of the KShD, the second group of I / O of which is connected to the external bus

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MCU data (ШДВ), the ICS output is connected to the first group of FSU inputs, the second group of inputs of which is connected to the control input bus (ШУВх), and the FSU output is connected to the control inputs of the RAM, RAM, KShA and KShD, a programmable block (PB) is introduced, the first group of inputs is connected to the output of the IMS, the second group of inputs is with the output of the OZUKT, the third group of inputs is with the input control bus (ШУВх), the first group of outputs of the power supply is connected to the output control bus (ШУВых). the second group of outputs is connected to the redundant output bus management (ДШУВых), and the third group outputs - to the third group of inputs of the FSU.

In a preferred embodiment of the utility model, the programmable unit may comprise a clock generator (SG), a register and a programmable combinational circuit (PCB), the first, second and third group of inputs of which are the corresponding input groups of the PB, the fourth group of PCB inputs is connected to the register output, which is the first group PB output, and the fifth group of PKS inputs is connected to the first group of outputs of the clock generator, the second group of outputs of which is connected to the clock inputs of the register, and the information inputs of the register are connected inens with the first group of PCB outputs, which is the second group of PCB outputs, the second group of PCB outputs is connected to the SG input, the third group of PCB outputs is the third group of PCB outputs;

Programmable combinational circuit can be implemented on a single chip type programmable logic matrix (PLM) or programmable read-only memory (ROM), or random access memory (RAM).

The programmable block can be performed on a single chip of the type of matrix of logical cells (ML).

In a preferred embodiment, the sync generator consists of a clock, the output of which is the second group of outputs of the SG and connected to the clock input of the counter, the output of which is the first group of outputs of the SG, and the input of the SG is the installation input of the counter.

The above implementation of the inventive device allows you to expand the range of debugged MCU, to ensure adaptation to new types of microprocessors and OMEVM. Moreover, undergoing adaptation

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an insignificant part of the software, hardware support remains unchanged. The presence of a programmable unit allows the developer to use for debugging the inputs of synchronization, availability or interruption of the target microprocessor. To do this, the developer only needs to rewrite the contents of the ICS. The presence of a duplicate control output bus allows in some cases to do without a register and increase the speed of AUOM. When using the clock input of the target MP for debugging the MCU, the programmable unit allows for both command-wise and cycle-by-block execution of the user program, which makes it possible to diagnose not only the MCU, but also the target MP.

The programmable block can be implemented on a single chip programmable logic matrix (PLM) type KS1556HP8 or KS1556HP6, or on the LSI matrix of logical cells (ML) type Xilinx. However, PB can be performed on three microcircuits as well: one 8-bit register, one PKS microcircuit, which can be used as KP556RT2 PLCs, KP556RT7 or KP556RT16 PRZUs, as well as K573RF4 RPZUs or any type of RAM with a capacity of at least 2k X 8, are enough for this. ; As a sync generator, you can use a conventional counter chip.

List of drawings

The invention is illustrated by drawings, where in FIG. 1 is a structural diagram of an AUOM; FIG. 2 is a structural diagram of a safety device; FIG. 3 is a graph diagram of the algorithm (GAW) of the operation of the PB, in FIG. 4 GAW formation of a shortened clock pulse Tct.

Information confirming the usefulness of

In the structural diagrams of FIG. 1 and 2 1, the following notation is used for the blocks and buses included in them: address-data interface 1, control signal interface 2, user program RAM 3, control signal generator 4, control point RAM 5, programmable combinational circuit 6, sync models

regenerator 7, address bus switch 8, data bus switch 9, register 10, programmable block 11, address bus (ША) 12, data bus (ШД) 13, control bus (ШУ) 14, external address bus (ШАВ) 15, external data bus (SHDV) 16, the input control bus (ШУВх) 17, which is simultaneously the 3rd group of PKS inputs, the output control bus (ШУВых) 18, which is simultaneously the output bus of the shortened clock pulse, the duplicate control bus (ДУУВых) 19, which is simultaneously clock bus output, microcontroller device (MCU) 20, 5th load PPA inputs PKS 21-23, 4th group of inputs PKS 24-28, 1st group of inputs PKS 29, 2nd group of inputs PKS 30, clock 31, counter 32.

The purpose of the blocks and tires AUOM is described as follows. Block NAD 1 is designed to receive and transmit addresses and data from the instrumental PC. VLOC ILC 2 transmits control signals from the instrumental PC to FSU 4 and PKS 6. VLOC OZUPP 3 stores the user program, as well as the program for outputting the contents of the internal memory of the target processor, which is loaded into OZUPP 3 only for the duration of its execution. FSU 4 is used to generate control signals for the operation of OZUPP 3, OZUKT 5, KShA 8, MShD 9. OZUKT 5 stores information about the presence of control points, which allows you to stop the execution of the user program when it reaches a predetermined address. PKS 6 generates the excitation functions for register 10 and the output functions of the SShVs 19 for PV 11. SG 7 generates the clock signals for register 10 and the synchronized frequency for the low-voltage switchgear 20. KSA 8 switches the ASW 15 from the target processor to the SHA 12. KSHD 9 switches the SHDV 16 to the SH 13 in the forward and reverse directions. The register 10 together with the PKS 6 and SG 7 form the PV 11, which is a sequential machine.

The operation of AUOM can be described by the example of a specific implementation for the target processor KR1806BE1.

AUOM implements the following options: monitor, automatic (real-time), automatic with stop at control points, step-by-step and tact-free.

In monitor mode, OZUPP 3, OZUKT 5 are loaded and read, software 11 is checked, read and write source and boot files from magnetic media, source files are translated, etc.

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In automatic mode, the user program is executed by the target processor in real time, in the control point mode, the program runs in real time to the first control point (CT).

In step-by-step mode, AUOM stops the target MP after each command is executed, and in beat-by-bit mode, for each clock cycle of the clock. The volume of RAM is 4 KB, RAM is 4096 bits. NAD 1 and ICS 2 are built on the KR580Ik55 microcircuit, OZUPP 3 - on two KR537RU10 ICs, FSU 4 - on the PLM KR556RT2, OZUKT 5 - on the KR537RUZ, PKS 6 - on the PLM KR556RT2, SG 7 - on the KR55561N1. KShA 8 and KShD 9 are made on three K555AP6 microcircuits, the K555TM9 IC is used as register 10. The entire AUM circuit has only 14 digital ICs. Software support is supplied to the IBM PC and consists of a monitor, cross-assembler, tracer, disassembler, and peripheral service packages. To ensure the above operating modes, instrumental PC software generates the following control signals:

Reset - setting register 10 to its initial state; ZPPR - record in OZUPP 3 in monitor mode; ZPKT - record in RAM 5 in monitor mode; RVPP - resolution selection OZUPP 3 in monitor mode; RVKT - resolution sampling OZUKT 5 in monitor mode; RSA - permission to access the ShA 12 from MKU 20; MKU - permission to work with MKU, exit from the monitor mode; TIKP - clock pulse for MKU 20, formed in the PC; ATGO ... ATGN - (n + 1) -bit address for selecting the value of the clock frequency for MKU 20; Auto - set automatic mode AUOM; Manual - setting a step-by-step mode; The step is to exit the target MP from the shutdown state.

In addition, the FSU to ensure the coordinated operation of OZUPP 3, OZUKT 5, KShA 8 and MShD 9 synthesizes the following output signals: UO sample crystal (VK) for the younger half of OZUPP 3; U1 - VK for the older half of OZUPP 3; U2 - VK for RAM 5; UZ - record in OZUPP 3; U4 - output resolution for WMS 9; U5 - permission output for OZUPP 3.

The synthesis of the output signals in FSU 4 is carried out in accordance with the following Boolean functions:

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UO All (MKU RVPP h- MKU CROM + MKU W CRAM); U1 AI MKU RVPP + MKU CROM +

U2 MKU F RVKT + MKU U6;

UZ MKU F ZPRR + MKU W WR;

U4 MKU (CROM + CRAM); j

U5 MKU RVPP ZPPR + MKU (CROM + CRAM WR RVPP).

The following signals from ШУВх 17 and from PKS 6 are used in these functions:

AI - the most significant bit of the 12-bit address bus; CROM - signal of the target MP about reading data from ROM; CRAM - target MP signal about access to RAM; WR - signal of the target MP about writing to RAM; U6 is the resolution signal of the OZUKT 5 crystal sample when the AUOM operates in non-monitor mode.

In FIG. 2 is a structural diagram of the programmable unit 11. The first group of inputs 29 to PV 11 receives the signals Aut, Manual, Step, TIPK, ATGO and ATG1, the second group of inputs 30 - the CT signal from the output of RAM 5, the third group of inputs - CA signals and CROM from MKU on ШУВх 17.

When operating in the RKT and SR modes, as well as on the STOP PB 11 command, the MKU 20 processor must stop at strictly fixed time points: after the arrival of the strobe of the CA address, but before the third clock pulse Tkt, at which the KR1806BE1 processor finishes reading the command set to SHDV 16. After the processor is stopped, the instrumental PC loads into RAM3 an output program for the contents of the internal memory of the processor KR1806BE1 and runs it until it stops at the previous CT. Then the PC restores the contents of RAM 3 and allows rotsessoru ISU 20 continued work

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kMKU F CRAM RVPP);

selected mode. The operation of the BP 11 is described by a graph diagram of the algorithm (GAW) shown in FIG. 3.

At GAW and further in the formulas, the following notation is used:

D1 - D3 - the corresponding inputs of register 10;

T1 - TK - the corresponding outputs of the register 10;

XI - Auth;

X2 - Ruchi;

ХЗ - Step;

X4 - CT;

X5 - CA;

X6 - CROM;

U6 - VK OZUKT in non-monitor mode;

U7 - reset counter.

The inverse values of CA and CROM are taken as X5 and X6, because it is in this form that they enter SHUVh 17.

It follows from the graph-diagram of the operation algorithm of the PB that from the initial state aO, the sequential automaton goes into state al in the case of control point (RCT) mode in the absence of control points (CT). In state al, the automaton remains until the signal arrives, and then it goes into state a2 and generates a sample signal of the OZUKT U6 crystal. The automaton goes into the AZ state automatically, continuing to issue Y6, after one period of the clock frequency supplied to the input of register 10. From the AZ state, if there is a CT, that is, when, the automaton goes into state A4 status with Y7 output, counter reset signal 32. In this state, the machine remains / - ig5oolMj:

u - is before arrival, after which, without removing U7, it goes into state a5.

In states a4 and a5, due to the output of U7, the counter 32 stops, forming the clock frequency for the MCU 20, which leads to a stop of the latter. In this pause, the instrumental PC starts its program for outputting the contents of the internal memory of the MKU 20.

The signal U7 is removed only by releasing the HZ, after which the automaton switches to state a6, where it remains until the active-low signal X5 arrives, with the arrival of which the transition to the initial state of aO occurs.

From the initial state of aO, the automaton in a step-by-step mode (SR), that is, at, immediately switches to state a4 with the issuance of Y7 and repeating the entire chain of the above transitions from a4 to aO.

If in the initial state of aO it turns out that, that is, automatic mode (ABT) is set, then the automaton will only go through the chain of states aO, a6.

The CT mode in the absence of a control point is characterized by the passage of the automaton through the states aO - a3 and a6 without stops and differs from the automatic mode by analysis of the state of the OZUKT, that is, by issuing U6 and polling the X4 signal.

In state a4, a change of operating modes is possible in accordance with the table. Simultaneously with setting the mode, a single pulse X3 is formed, since otherwise it is impossible to get out of states a4 and a5.

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- & The synthesis of the output functions and the excitation functions, carried out in accordance with the GAW of PB 11, gives the following Boolean expressions:

D3 TK T2 T1 X5 + TK T2 T1 X4 + TK T2 T1 X1 X2 + TK T2 T1 + TK T2 HZ; D2 TK T2 T1 X5 + TK T2 KT1 X6 + TK T2 T1; D1 U6 U7

Due to the fact that OMEVM K1806BE1 imposes restrictions on the duration of a clock pulse, for a low-frequency clock it is necessary to form a shortened pulse Tkt from a regular pulse. This procedure is performed in accordance with the GAW,

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I table

(1) TK T2 T1 + TK T2 HZ + TK T2 T1 KX1 X2 + TK T2 T1 X6; TZZhT2.

shown in FIG. 4. The implementation of this GAW in the form of a sequential automaton is described by the following Boolean functions:

D4 -

(2)

D5

U: T4.

The following notation is used here:

D4, D5 and T4, T5 - the corresponding inputs and outputs of the register 10; X Beat; U - Tkt.

The clock 7 is designed not only to generate clock pulses of different frequencies for the MKU 20, but also to ensure synchronization of the appearance and shutdown of these pulses when the MKU is stopped in the Stop, CT and SR modes. Therefore, the Beat 19 signal generated in the PCS 6 is described by the following Boolean function:

Tact TIPK ATGO ATGI-R1 ATG1 ATGO + P2 ATG1 ATGO + RZ KATG1 ATGO, (3)

where ATGO, ATG1 is the address of the clock generator, in accordance with which the clock frequency is selected;

F1 -F3 - corresponding frequencies at the output of the counter 32; TIPK - a clock pulse generated by instrumental PC.

Boolean functions (1) - (3) are recorded in the PCS 6, after which PB 11 is ready for operation.

GAW (Fig. 3 and 4) describe the operation of the adaptive hardware, a device for debugging microcontroller programs. To display the contents of the internal memory of MKU 20, a certain program is required.

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1 frame support. As an example, one of the software support algorithms for MKU based on KR1806BE1 can be given. An algorithm for outputting the contents of the internal memory of the MCU. 1. Check the breakpoint for the start of the command. The sign of the beginning of the command is formed by the cross-assembler and is issued in the form of a list of addresses of the beginning of the user program commands. 2. Remember the return address AW, that is, the address at which the stop occurred, and the contents of the three RAM cells, starting with AW. 3. At the AW address, write the unconditional jump command to the address of the POTR program to output the contents of the internal memory of the MCU. 4. Write the POTR program to the second page of RAM, if the stop occurred on the first page, otherwise, on the first. 5. Record at the end of the POTR program the unconditional transition command to 6. Issue the resolution of the program memory selection (RVPP). 7. Run the POTR program in two stages: a) output the battery in RAM to the zero page and enter the contents of the RAM cell using the IdO command with indirect addressing by the register pair P4, P6 to determine the current page number of the RAM; the page number is read in the high byte on ША); b) output of the contents of the remaining internal memory to the zero page of the RAM, control of the end of the POTR program by the number of TIPK pulses and the achievement of the return address AW. 8. Transfer the results of the POTR program from the zero page of the RAM to the memory of the instrumental PC. Remove RVPP. 9.Restore the zero and first (or second) pages of the RAM. 10.Restore the three previously changed RAM cells at the return address AW. Using the AUOM as an example for the OMEVM KR1806BE1, a hardware-software system for telemetry and signaling was developed and debugged with the transmission of information over dial-up telephone lines over 30 km. The user program volume is i.

pitch 4 kbytes.

Since even the 8-bit register 10 allows the construction of a spacecraft with 256 states, this means that for almost any microcontroller its own system of Boolean functions can be implemented on PCS 6. However, to write Boolean functions in ICS 6, a programmer or a set of replaceable PCS 6 modules is required This is not always convenient, therefore, PCS 6 can be executed on the basis of RAM and change the set of Boolean functions by transferring them from the instrumental PC directly to RAM. This architecture, when controlling the operation of the MCU on the clock input, also allows the possibility of an invariable system of Boolean functions in PCS 6 for some types of processors.

Managing the MKU's clock input is relatively complex. Significantly easier input control Ready or Interrupt.

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Claims (7)

1. Adaptable device for debugging microcontrollers, containing the address-data interface (NAD) and control signals (IMS) for communication with instrumental personal computers, RAM of user programs (RAM), RAM of control points (RAM), control signal generator (FSU), address bus switch (CAB) and data bus switch (CAB), the first group of IAD outputs connected to the address inputs of OZUPP and OZUKT, as well as to the CAB output, the inputs of which are connected to the external address bus (BAS) of the debugged microcontroller device (MK ), and the second group of inputs and outputs of the IAD is connected to the input-output of the RAM data, the input of the RAM and the first group of the outputs of the CDM, the second group of inputs and outputs of which is connected to the external data bus (BDM) of the MCU, the output of the ICS is connected to the first group of inputs FSU, the second group of inputs of which is connected to the input control bus (ШУВх), and the output of the FSU is connected to the control inputs of RAM, RAM, KShA and KShD, characterized in that a programmable unit (PB) is inserted into it, the first group of inputs of which is connected to the input IMS, the second group of inputs - with OZUKT output, the third group of inputs is from ШУВх, the first group of ПБ outputs is connected to the output control bus (ШУВых), the second group of outputs to a redundant output control bus (ДУУВых), and the third group of outputs to the third group of FSU inputs. 2. The device according to claim 1, characterized in that the programmable unit contains a clock generator (SG), a register and a programmable combinational circuit (PCB), the first, second and third groups of inputs of which are the corresponding groups of inputs of the PB, the fourth group of inputs of the PCB is connected to the output register, which is the first group of output of the PB, and the fifth group of inputs of the PCB is connected to the first group of outputs of the clock, the second group of outputs of which is connected to the clock inputs of the register, and the information inputs of the register are connected to the first ppoy output PKC, which outputs a second group IB, group PKC second outputs connected to the input of SH, the third group of outputs PKC third group IB is output. 3. The device according to claim 2, characterized in that the programmable combinational circuit is made in the form of a programmable logic matrix. 4. The device according to claim 2, characterized in that the programmable combinational circuit is made in the form of read-only memory. 5. The device according to claim 2, characterized in that the programmable combinational circuit is made in the form of random access memory. 6. The device according to paragraphs. 1 and 2, characterized in that the programmable unit is made in the form of a matrix of logical cells. 7. The device according to claim 2, characterized in that the clock generator consists of a clock generator, the output of which is the second group of outputs of the SG and connected to the clock stroke of the counter, the output of which is the first group of outputs of the SG, and the input of the SG is the installation input of the counter.