RU4395U1 - MULTI-PROCESS SHIP CONTROL COMPUTER SYSTEM - Google Patents

Abstract

A multiprocessor ship control computer system containing microprocessors and an external random access memory connected by input / output ports to the first interface highway, information input blocks connected via the second interface highway to the second input / output port of the third microprocessor, a clock generator connected by an output to the inputs synchronization of all microprocessors and a switch connected by inputs to the outputs of the information output unit associated with the input-output port and through a fourth interface highway with a second input / output port of the fourth microprocessor, characterized in that an adapter is connected to it by an input / output port through a third interface highway with an input / output port of a control panel and a second input / output port of a second microprocessor, external storage device connected by the exchange bus with the corresponding input / output of the second microprocessor, as well as the first and second control signal generators-distributors connected to only to the first and second groups of outputs of the switch, while the control inputs and control outputs of all microprocessors are connected respectively to the output and to the first input of the adapter, the second controlled input of which is connected to the fourth output of the control panel, the first, second and third control outputs of which are connected to controlled inputs respectively, the switch and both shapers-distributors of control signals, and the first control output of the control panel is also connected to the control input

Description

Multiprocessor Ship Management Computer System

The utility model relates to computer technology and is designed to collect information and its subsequent processing to generate control signals for various processes, equipment, in particular, ship weapons.

Currently, intensive work is underway to create high-speed multiprocessor systems for collecting and processing information, in particular, distributed microprocessor systems that perform parallel data processing using a large number of micromachines organized in a certain way.

Known microprocessor system 1, containing several microcomputers with individual memory devices and several common memory devices, each of which is associated with two microcomputers. When working with individual memory, microcomputers can execute programs independently of each other. For the exchange of information between microcomputers, common storage devices are used.

The disadvantages of this system include the lack of the ability to exchange data directly between the individual storage devices of the microcomputer, as well as the limited number of connected microcomputers

MRKGOIF 15/16

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to one common storage device, which reduces the performance of information exchange in the system.

Also known microprocessor system 2, consisting of several autonomous microprocessors connected via a system bus with a common external memory. The exchange of information between microprocessors is via shared memory. Access autonomous microprocessors to the shared memory is provided by the distributor of the system bus. Such an organization of the system is preferable to the previous one, since all microprocessors have the same capabilities when using shared memory.

The main disadvantage of this system is the inability to directly exchange information between microprocessors, which reduces system performance.

Also known is a multiprocessor system 3, which contains microprocessors connected by two-way communications through a device for interfacing with a memory device, and a resource allocation device that performs the functions of a system dispatcher.

The disadvantage of this system is that the resource allocation device provides scheduling only of tightly connected subtasks without taking into account interruptions of calculations, for example, for input / output.

Closest to the technical nature of the proposed device is a multimiprocessor system 4, containing n Executive microprocessor units, microprocessor input / output units, a storage device, a communication device with memory, a switching unit and a clock generator, while the information input-output, address and control the inputs of the storage device are connected respectively with the information input-output, address and first control inputs of each microprocessor unit, as well as nformatsionnym input address and control outputs first communication device with a memory. The synchronization of the system elements is carried out by signals from the clock generator.

The disadvantage of this system is the lack of test control and control of the correct functioning of the devices included in its composition, as well as the complexity of controlling the computing process of the system.

These shortcomings are largely eliminated in the proposed utility model, the essence of which lies in the fact that in a multiprocessor ship control computer system containing microprocessors and external random access memory connected via input / output ports to the first interface highway, information input blocks are connected via the second an interface line with a second input / output port of a third microprocessor, a clock generator connected by an output to the synchronization inputs of all microprocessors and a switch connected by inputs to the outputs of the information output unit connected to the input / output port via the fourth interface highway with the second input / output port of the fourth microprocessor, an adapter connected to the input / output port via the third interface line to the input / output port of the control panel is introduced and with a second input / output port of the second microprocessor, a second external storage device connected to the exchange bus with the corresponding input / output of the second microprocessor ora, as well as the first and second shapers-distributors of control signals connected respectively to the first and second groups of outputs of the switch, while the control inputs and control outputs of all microprocessors are connected respectively to the output and to the first input of the adapter, the second controlled input of which is connected to the fourth output control panel, the first, second and third control outputs of which are connected to the controlled inputs of the switch and of both shapers-distributors of control s signals, and the first control output of the control panel is also connected to the control input of the first microprocessor.

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- 3 control signals and commands between consumers depending on their type.

The essence of the utility model is illustrated by the drawing, which shows the structural diagram of the proposed utility model, where are indicated:

1-4 - microprocessors;

5 - random access memory;

6 - the first interface highway; 7-9 - information input blocks;

10- second interface highway;

11- adapter;

12 - external storage device;

13 - clock generator;

14- control panel;

15- alphanumeric indicator;

16-video indicator;

17- keyboard;

18 - pairing unit;

19- third interface highway;

20- fourth interface highway;

21 - information output unit;

22-switch;

23, 24 - the first and second shapers-distributors of control signals.

In accordance with the drawing, the microprocessors 1, 2, 3, 4, as well as random access memory 5 are connected by input / output ports to the interface highway 6, information output input blocks 7, 8, 9 through the second interface highway 10 are connected to the second input / output port microprocessor 3, adapter 11 control output and input respectively connected to the control inputs and outputs of microprocessors 1, 2, 3, 4, synchronization inputs to. 4 of them are connected to the output of the generator 13 clock pulses. The second input of the adapter 11 is connected to the fourth output of the control panel 14, including a alphanumeric indicator 15, a video indicator 16 and a keyboard 17, respectively connected by inputs and outputs to the interface unit 18, the input / output port of which is connected via the highway 19 to the input / output port of the adapter 11 and a microprocessor 2 connected by an exchange bus with an external storage device 12. Microprocessor 4 by a second input / output port via an interface line 20 with an input / output port of an information output unit 21 connected to an output to the inputs of the switch 22, the first group of outputs of which is connected to the inputs of the shaper-distributor 23, and the second group of its outputs is connected to the inputs of the shaper-distributor 24. The controlled inputs of the shapers-distributors 23, 24 are connected respectively to the second and third outputs of the keyboard 17 of the control panel 14, and the first output of the keyboard 17 is connected to the controlled inputs of the switch 22 and microprocessor 1.

The structural construction of the blocks and devices included in the system is widely known in the technical literature.

As microprocessors 1-4 can be used in the structure given in the book. Computers Reference Guide Ed. G. Helms, trans. from English., Moscow, World, 1986. from. 121, fig. 24.2, p. 125 images 24.5, as well as in the book. Designing digital devices on single-chip microcontrollers ed. Stashin V.V., Urusov A.V. and others M. Energoatomizdat, 1990. p.52, fig. 3.2.

As block 18, a programmable keyboard and display controller (LSI KR 580 BB 79) can be used, see book. S. T. Hvoshch et al. Microprocessors and microcomputers in automatic control systems 1987, p. 105, fig. 2.23.

As an external storage device 12 can be used programmable non-volatile memory, consisting of mini-assemblies on cylindrical magnetic domains and a controller that provides information exchange (see, for example, the book. Computers. Reference manual, t. 1. edited by G. Helms, trans. from English Moscow, Mir, 1986, pp. 283-284.

The system operates as follows.

As can be seen from the drawing, the utility model is made in the form of a multiprocessor control computing system with the distribution of functions between its microprocessors.

The microprocessor 3 through the interface highway 10 provides information from blocks 7, 8, 9 input information from external sources and enter it into the interface highway 6, while block 7 serves to receive and output information from the ship's radar station. This information is the distance (DK) to the observed surface object, its current bearing (Pk) or heading angle (Yak), as well as its speed (UK). This information is used to generate torpedo tube control signals.

Block 8 serves to receive and enter information from the ship’s sonar system. This information includes the range (Dpl) to the underwater object, its bearing (LPS) or heading angle (Yap), as well as its speed (Upl). This information is used to generate control signals for bombing devices.

Block 9 is designed to receive and enter information from the ship's navigation complex. This information is the current own course (Ks) and speed (Vc), as well as the angles of the board (0) and pitch (40 pitch). Depending on the observed situation, the system processes information from either block 7 or block 8. Information The output from block 9 is continuously received. The information received at the inputs of blocks 7, 8, 9 can be either digital, analog, or in combination. Therefore, before entering it into highway 10, it is converted to digital form. output set analog-c digital converters.

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- 6 Information entered by microprocessor 3 into highway 6 is received by microprocessor 1, which processes the information in accordance with predetermined algorithms corresponding to information from a radar station from block 7, or from a hydroacoustic station from block 8. The processing algorithm is set by a signal from the remote control 14 control input to the controlled input of microprocessor 1.

The microprocessor 4 is designed to receive information processing results from line 6 and input them via the interface line 20 to the information output unit 21, which is converted into analog form in it and then issued to the switch 22, which is controlled by a control signal from the first output of the control panel 14 . At this signal, the switch 22 generates control signals either to the shaper-distributor 23, or to the shaper-distributor 24.

Shaper-distributor 23 is a block of amplifiers controlled by signals from the second output of the console 14, depending on the designated bombing apparatus.

When controlling torpedo tubes, the switch 22 provides signals to an analog driver-distributor 24, which is controlled by a signal from the third output of the control panel 14.

The microprocessor 2 in cooperation with RAM 5 and an external storage device 12 provides mathematical software for the system in the main mode of operation and in the test operational control mode.

During the test control, the microprocessor 2 interacts with the adapter 11, the external storage device 12 and the remote control 14.

The exchange of information between these devices is carried out through the interface line 19.

Monitoring the correct functioning of the system after passing the tests is carried out by analyzing the error signals of the adapter 11.

The absence of a signal during the interrogation of the corresponding microprocessor 1-4 indicates its normal functioning.

If there is an error signal, the microprocessor 2 by means of the adapter 11 determines the address of the faulty microprocessor, turns it off and provides the corresponding information to the control panel 14.

The ability to programmatically disable a faulty device allows the program to carry out an appropriate reconstruction of the computing system without affecting its overall performance. After passing the tests normally, the system is considered ready to work in the main mode discussed above.

Thus, the proposed multiprocessor control computing system in comparison with the known provides:

- software reconstruction of the system in case of improper functioning of one of its devices.

Another advantage of the system is its simplicity.

The presented drawings and description of the system make it possible, using the existing element base, to manufacture it in an industrial way, which characterizes the proposed utility model as industrially applicable.

Sources of information.

1.Pat. US No. 4065809, CL G06F 15/16, 1977

2.Pat. US No. 3959775, CL G06F 15/16, 1976

3.A.S. USSR No. 742943, cl. G06F 15/16, 1980

4.A. S USSR No. 907551, class G06F 15/16, 1982 (prototype).

Claims (1)

A multiprocessor ship control computer system containing microprocessors and an external random access memory connected by input / output ports to the first interface highway, information input blocks connected via the second interface highway to the second input / output port of the third microprocessor, a clock generator connected by an output to the inputs synchronization of all microprocessors and a switch connected by inputs to the outputs of the information output unit associated with the input-output port and through a fourth interface highway with a second input / output port of the fourth microprocessor, characterized in that an adapter is connected to it by an input / output port through a third interface highway with an input / output port of a control panel and a second input / output port of a second microprocessor, external storage device connected by the exchange bus with the corresponding input / output of the second microprocessor, as well as the first and second control signal generators-distributors connected to only to the first and second groups of outputs of the switch, while the control inputs and control outputs of all microprocessors are connected respectively to the output and to the first input of the adapter, the second controlled input of which is connected to the fourth output of the control panel, the first, second and third control outputs of which are connected to controlled inputs respectively, the switch and both shapers-distributors of control signals, and the first control output of the control panel is also connected to the control input th microprocessor.