RU43114U1 - SINGLE-RING DATA PACKAGE NETWORK - Google Patents

Abstract

The utility model relates to data packet transmission networks with packet routing and can be used in integrated security systems, industrial automation of buildings, vehicles, aircraft. The data packet transmission network contains addressable devices and a power supply of addressable devices with a router. The control circuit of the power supply of the addressable devices with the router includes a means of comparing the identifier and address of the sender of the packets recorded in the buffer with the same data coming from the addressable packets. The network is configured to delete a packet, the identifier and address of the sender of which coincides with the identifier and address of the sender of the packet stored in the buffer, and then delete the record corresponding to the packet from the buffer. The buffer is periodically cleaned after a time interval corresponding to the maximum possible packet lifetime in the ring. The network is divided into segments, between which at least one power supply of addressable devices with a router is connected, at least one addressable device is connected to the buses of each segment. The latter is equipped with a means of disconnecting it in the event of a short circuit in the bus. The technical result to which this utility model is aimed is to increase the reliability of the network by preserving the power of the devices and the possibility of exchanging data between network devices when the bus is open or shorted and the possibility of building a reliable industrial network of long length, both linear and ring

Description

The utility model relates to data packet transmission networks with packet routing and can be used in integrated security systems, industrial automation of buildings, vehicles, aircraft.

A known data packet network containing addressable devices via a two-wire bus (half-duplex mode) or four-wire bus (duplex mode) and a power supply of addressable devices with a router, designed to power these buses, relay data packets generated by means of generating addressable device packets, including a control circuit with buffer memory (Japanese application No. 2003-309623, published October 31, 2003).

The technical result, which this utility model aims to achieve, is to increase the reliability of the network by preserving the power of the devices and the possibility of exchanging data between network devices when the bus is open or shorted and the possibility of building a reliable industrial network of long length, both linear and ring topology, with the combination of power and data transfer functions on agreed and non-agreed communication lines.

The technical result, the achievement of which the creation of this utility model is aimed at, is achieved by the fact that in a peer-to-peer ring transmission network of data packets containing addressable devices and a power supply of addressable devices with a router, connected by means of two-wire buses (half-duplex mode) or four-wire buses (duplex mode) to power these buses, relay data packets generated by means of generating packets of addressable devices, including a control circuit with a buffer memory - buffer, control circuit of the power supply of addressable devices with a router

includes a means of comparing the identifier and address of the sender of the packets recorded in the buffer with the same data arriving from the addressable devices of the packets, and is configured to delete the packet, the identifier and addresses of the sender of which coincides with the identifier and address of the sender of the packet stored in the buffer, and subsequent deletion from the recording buffer corresponding to the mentioned packet, as well as periodically flushing the buffer after a time interval corresponding to the maximum possible lifetime of the packet one in the ring, while the network is divided into segments, between which at least one power supply of addressable devices with a router is connected, at least one addressable device is connected to the buses of each segment, which is equipped with a means of disconnecting it in case of a short closures and is configured to generate data packets over a time interval T equal to N / S, where N is the number of addressable devices in the ring, S is the number of packets transmitted per unit time, and the buffer is configured to store records in excess of the number of addressable devices in the ring.

Figure 1 presents a diagram of a peer-to-peer ring network.

Figure 2 presents the structural diagram of the address device.

Figure 3 presents a structural diagram of a network power source with a router.

Figure 4 shows the byte of the transmitted signal at the physical level in accordance with the data transmission protocol in the network.

Figure 5 presents the transmission of packets at the data link layer.

6 shows a packet format.

The peer-to-peer ring network 1 for transmitting data packets (Fig. 1) contains connected via address buses 2 (two-wire in half-duplex mode or four-wire in duplex mode), address devices 3 and power supplies 4 of address devices with a router, designed to power these buses, relay packets data generated by means of generating packets of addressable devices. Network

divided into segments, between which the indicated power sources 4 of the address devices 3 are included. The address device 3 (FIG. 2) includes a control circuit 5 with a buffer memory — a buffer, two transceivers 6 and 7, the first inputs / outputs of which are connected to two inputs / outputs of the control circuit 5, and the second inputs / outputs to the address buses. The output of the control circuit 5 is connected to the input of the means 8 for switching off the address device in the event of a short circuit in the bus (short circuit isolator. The means 8 for switching off the address device in the event of a short circuit in the bus includes a key 9, the control input of which is connected to the output of the key protection circuit 10 The power supply 4 of the addressable devices with the router includes a control circuit 11, which also contains a buffer, two transceivers 12 and 13, the first inputs / outputs of which are connected through the galvanic isolation blocks 14 and 15 s to the first two inputs / outputs of the control circuit 5, and the second inputs / outputs to the address buses 2. The third input / output of the control circuit 11 is connected to the input / output of the indication circuit 16. The power supply 4 with the router also includes a voltage converter 17, designed to connect either to the battery 18 or to the industrial power network 19 (respectively, at the first input / output and the first input). For example, a pulse voltage converter can be used. The second input / output of the voltage converter 17 is connected to a fourth input / output of the control circuit 11. The first and second outputs of the converter 17 are connected to the power inputs of the transceivers 12 and 13. The third input / output of the voltage converter is connected to the first input / output of the overload protection circuit 20, the second input / output of which is connected to the fifth input of the output of the control circuit 11. And from the output of the overload protection circuit 20, power is supplied to the sensors and actuators. The control circuit contains a means of comparing the identifier and address of the sender of the packets recorded in the buffer with the same data coming from the address devices of the packets. The network works as follows.

Any device on the network (address device 4 or power supply 5 with a router) can start transmitting a message (datagram) on its own initiative. Each datagram contains the address of the sender and the serial number of the packet from this sender, so the combination of these fields is unique and can be repeated only when the packet number counter overflows. If several devices try to transmit a message at the same time, the conflict resolution mechanism is activated, so that as a result, a message with a higher priority is transmitted first. Moreover, if we take into account that the dominant bit - the logical “1” bit corresponds to the presence of a pulse on the line, and the recessive bit - the logical “0” bit corresponds to the absence of a pulse in the bit interval, then when transmitting a packet, each device simultaneously analyzes the received data, and when discrepancy of the received bit to the transmitted one, the device stops further transmission and continues to receive a packet from another device. Since the bit of logical “1” is dominant, when a conflict occurs, it gives way to a device that transmits a logical “0” in a conflict bit.

The sent message is heard (received) by all devices 3 in the corresponding bus segment 2, that is, between two power sources 4, as well as two indicated sources 4 connected to this segment. At the same time, each source 4 checks in its buffer whether the given packet passed through it, if it didn’t, it writes the packet identifier to the buffer and forwards the packet to the next segment of bus 2. Thus, the message begins to spread along the ring in both directions. In the end, one of the sources 4 message will come from two sides. This source 4, having discovered that he already received such a message (by recording in the buffer), does not pass it further, thereby preventing the multiplication of packets in the ring. A package is deleted, the identifier and address of the sender of which coincides with the identifier and address of the sender of the package stored in the buffer, and then removed from the buffer of the record corresponding to the mentioned package. The buffer is periodically cleared after the interval has expired

time corresponding to the maximum possible lifetime of the packet in the ring

With any single break of bus 2, a message from any device 3 will reach each address device in all segments of bus 2. At the same time, with a break, the power of all devices 3 will also be saved, since each segment receives power from two sides.

With a single short circuit in any place of the ring bus, the keys 9 are activated in the shutdown means 8 in all addressable devices 3. The key protection circuit 10 switches the key off when the voltage on the bus is reduced during a short circuit, preventing the key from switching to linear mode.

Then, the control circuit 5 will act on them, restoring their original position. At the same time, circuit 10 will not allow the keys of those addressable devices to turn on after which a short circuit has occurred. Thus, the network will work in the same way as during a break, while maintaining the ability to transfer data and power all devices. After closing the circuit, the initial position of the keys 9 is automatically restored.

Thus, the control circuit 9 of the addressable device provides:

- reception, transmission and processing of packets related to the device;

- performance of applied tasks;

- key management 9.

The voltage Converter 17 provides galvanically isolated voltage outputs of the transceivers 12 and 13, the power of the control circuit 11, the battery 18, the transition to the "Standby" mode when there is no (or lower than normal) voltage in the network 19. At the same time, the control circuit 11 provides control of the battery 18 (measurement of battery voltage, charge control), control of the presence of voltage in the network 19, measurement of currents and voltages of loads, control of the reception and transmission of packets (data gram), control of relay packets between the segment Bus Ami 2.

The power supply 5 of the addressable devices with the router performs the following functions: power supply of bus segments 2 with protection against short circuit and

congestion, relaying packets between bus segments 2, buffering packets passing through source 5 with storing a unique packet identifier (sender ID + packet number). The size of the buffer should ensure that all packet identifiers are retained for the maximum delay time of the packet passing through the ring, approximately 4 s × 20 p / s = 80 p (packets).

Blocking the packet (not passing the packet to the next segment of the ring) to prevent the multiplication of packets in the ring by removing packets re-entering the source 5. The fact that the packet is re-entered is determined by the match of the record (sender address and ID) in the IPM buffer with the sender address and ID in the incoming package. After removing the package, the record from the control circuit buffer 11 is also deleted.

Clearing a packet record in the buffer after the packet has expired in the ring is approximately 2-10 seconds.

When transmitting a byte of information (figure 4), data is transmitted in the most significant bit forward. As mentioned above, a logical “0” is the absence of a pulse, and a logical “1” is the presence of a pulse, StartBit is the start bit, always equal to one. StopBit - the final bit, always equal to one. Parity - parity bit, used to control the correctness, only data bits are taken into account, ERR - error bit; if the parity bit does not match on the receiving side, then the error bit is set to 1.

To ensure bit and packet synchronization along the edge of each pulse (voltage drop across the line), all devices adjust the phase of their master bit-interval generator.

When transmitting packets (FIGS. 5 and 6), the checksum is calculated in accordance with the following ratio;

Byte0 Xor Byte1 Xor Byte2 Xor ... Xor ByteN = Byte CRC

An addressable device generates data packets over a time interval T equal to N / S, where N is the number of addressable devices in the ring, and S is the number of packets transmitted per unit time (i.e., the data rate in

network, packets / sec), while the buffer is configured to store the number of records M, exceeding the number N of addressable devices in the ring: M _buffer. > N.

Under these conditions, double passage of the packet through the same segment of the ring is impossible.

False blocking of a package is possible only if the following conditions are met:

during time t, the same device will form packets with the same identifiers (IDs) and at the same time, a record with the address of this device and with the same ID will be saved in the buffer of one of the IPMs.

Deleting entries from the source buffer 5 after the maximum possible lifetime of the packet in the ring is necessary to avoid false delay in the packet.

This ensures that the ID cannot be repeated for a time longer than the maximum possible packet lifetime in the ring.

Claims (1)

A peer-to-peer ring data packet network containing addressable address devices and a four-wire bus (duplex mode) or a four-wire bus (duplex mode) for supplying these buses, relaying data packets generated by means of packet generation of addressable devices, including a control circuit with a buffer memory - a buffer, characterized in that the control circuit of the power supply of addressable devices with a router The torus includes a means of comparing the identifier and the sender address of packets recorded in the buffer with the same data arriving from the addressable devices of the packets, and is configured to delete the packet whose identifier and sender addresses match the identifier and address of the sender of the packet stored in the buffer, and the subsequent deletion from the buffer of the record corresponding to the mentioned package, as well as periodic cleaning of the buffer after a time interval corresponding to the maximum possible lifetime and a packet in the ring, while the network is divided into segments, between which at least one power supply of addressable devices with a router is connected, at least one addressable device is connected to the buses of each segment, which is equipped with a means of disconnecting it in case short circuit and is configured to generate data packets over a time interval T equal to N / S, where N is the number of addressable devices in the ring, and S is the number of packets transmitted per unit time, while the buffer is configured to store the number of entries in excess of the number of addressable devices in the ring.