JP2875400B2 - Communication control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control system in which a terminal sends a forward signal including a destination address and receives a response signal from the destination terminal to perform communication in a communication network system having a full-duplex transmission path. .

[0002]

2. Description of the Related Art Conventionally, there are various types of communication networks of this kind. One of them is a multi-channel grid communication network based on analogy of living nerve cells.
-74349, JP-A-2-29046 and the like. This is achieved by connecting a communication control element of a multi-input one-output signal as a node to a multi-coupled structure to form an irregular communication network (LADERNET = Lattice Dynamic Architecture).
e Network), and each node has a communication network form in which digital signals are transferred on a first-come, first-served basis.

The grid communication network has many advantages, but is particularly excellent in the following points. One is that the degree of freedom of the network topology is high due to the multi-coupling structure. Therefore, the fault tolerance (fault tolerance) is high. That is, even if there is a failure in a part of the network, communication is appropriately secured on another route. Second, an optimal communication path (shortest path) is selected for each communication by first-come-first-served logic. Further, this system adopts a multi-channel system in which a plurality of connection channels are simultaneously established in a node, and efficiently establishes full-duplex communication.
Thus, the present system is effectively applied, for example, to the physical layer of OSI (Open System Interconnection).

[0004] Here, in consideration of network integration, a relay device such as a data link bridge or a gateway compatible with a communication protocol of the CSMA / CD system represented by Ethernet (Ethernet) or Starlan (Star Run) is used. Network integration is becoming mainstream. Here, when an attempt is made to apply the data link bridge to a LAN such as the above-mentioned irregular communication network formed by a full-duplex transmission line, since this does not have a unique address, a countermeasure is necessary. .

[0005] For example, when a certain terminal transmits to another terminal in the same network, a response signal from the data link bridge may arrive earlier than that from the target terminal. The path is fixed to the data link bridge, and communication with the target terminal becomes impossible. That is, a problem occurs in the operation with the normal terminal. In consideration of this point, as a communication control device corresponding to a data link bridge, a maximum one-way transmission delay time of the network is set to T _PMAX, and a time period from when the communication control device for the terminal starts reception to when transmission of the response signal starts is transmitted. It has been proposed by the present applicant that, when the time is T _A , the predetermined period until the response signal is transmitted is set to be larger than (T _A + 2 · T _PMAX ). This is when the signal from the network is received, in which it has to be sent the response signal after a predetermined time T _R to be a broadcast signal.

[0006] Such a data link bridge compatible communication control device establishes a physical dedicated communication path (fixed path) between the originating terminal and the destination terminal, as in the case of the above-mentioned irregular communication network. Use something that can be set,
A disadvantage arises when there are two or more data link bridges in the same network.

This will be described with reference to FIG. In the illustrated example, three networks 1, 2, and 3 utilize two data link bridges 4 and 5 and four communication control devices 6 and 6.
An example of integration by 7, 8, and 9 is shown. In the illustrated example, for example, if one of the terminals belonging to the network 1 (this is referred to as terminal A) starts transmitting to a terminal belonging to the network 2 (this is referred to as terminal B), this signal is The data is received by both the data link bridges 4 and 5. Then, both the data link bridges 4 and 5 send a response signal. At this time, the terminal A is located closer to the data link bridge 5 than the data link bridge 4 and the response from the data link bridge 5 is returned. Arrives at the terminal A earlier, a communication path is formed between the terminal A and the data link bridge 5. Therefore,
A signal cannot be sent to the intended destination terminal B.

In view of the above, even if a plurality of data link bridges exist in the same communication network, only one response signal is returned, so that communication with a desired destination terminal can be performed. Was also filed by the present applicant in Japanese Patent Application
No. 256563.

FIGS. 3 to 5 show the contents. First,
The basic idea of the proposed example will be described with reference to FIG. The communication control device for the data link bridge stores the addresses of all the terminals belonging to the network of the other party as seen from the self. For example, in the illustrated example, the communication control device 6 corresponds to the network 2, the communication control device 7 corresponds to the network 3, the communication control device 8 corresponds to the networks 1, 3, and the communication control device 9 corresponds to the networks 1, 2. The addresses of all the terminals (not shown) to which the terminal belongs are stored. When receiving a signal from the Ne <br/> Ttowaku, the destination address contained therein relative to the total addresses its own communication control apparatus has stored, it returns a response signal if is a match It is like that.

A configuration of a communication control device (any of 6 to 9) for realizing such a basic idea will be described. Here, each of the networks 1 to 3 shown in FIG. 3 is the above-mentioned irregular communication network, and the communication means is Ethernet. FIG. 4 schematically shows the response signal transmitting means 10 and its related parts in the configuration of the communication control device. The illustrated example relates to, for example, the communication control device 6. First, there is provided a receiver 11 for receiving the differential transmission signal TTRMT from the data link bridge 4 and converting it into a TTL-level signal TD. A driver 12 is provided. On the other hand, on the other hand, the differential reception signal NRCV from the network 1 is received and the TTL
A receiver 13 for converting the signal into a level signal RD;
A driver 14 that converts the converted signal RD into a differential signal TRCV and outputs the converted signal RD to the data link bridge 4 is provided. Further, the encoded signal TTRMT is converted into NR
Z data signal T × D and clock T × synchronized therewith
A Manchester encoder / decoder (MED) 15 for converting into C and outputting is provided. The MED 15 affirms the signal TCSN while receiving the signal TTRMT, and when the signal TCSN is negated, the output of the driver 12 is turned off. Similarly, there is provided a Manchester encoder decoder (MED) 16 which converts the encoded signal NRCV into an NRZ data signal R × D and a clock R × C in synchronization with the NRZ data signal R × D and outputs the converted signal. The MED 16 receives the signal RRCV while receiving the signal NRCV.
When the signal RCSN is negated, the output of the driver 14 is turned off.

Further, a selector 1 for selecting transmission / reception
7 are provided. This selector 17 receives the signal TCSN.
Is affirmed earlier than signal RCSN, signal Tx
D and T × C are output as data DATA and clock CLK. Conversely, when signal RCSN is asserted earlier than signal TCSN, it outputs signals R × D and R × C as data DATA and clock CLK. In addition, the signal TCSN or RCSN, whichever is affirmed earlier,
Output as signal PEN. On the output side of the selector 17, a preamble detection circuit 1 functioning as an operation control unit
8 are connected. The preamble detection circuit 18 starts operating when the signal PEN is affirmed, and the data DA
It detects the end of the TA preamble. That is, when the end of the preamble is detected, the signal PEND is affirmed.

The preamble detection circuit 18 is connected to an address comparison circuit 19 which is a feature of the proposed example.
As shown in FIG. 5, the address comparison circuit 19 is configured by sequentially connecting a counter 20, an OR gate 21, an AND gate 22, a memory unit 23 serving as a storage unit, and a comparison unit 24 serving as an address comparison unit. First, the counter 20 receives the signal PEN.
When D is affirmed, the clock CLK for 48 bits corresponding to the destination address following the preamble of the data DATA is counted, and when the counting is completed, the output Q is affirmed. The supply of the clock CLK to the memory unit 23 and the comparison unit 24 is controlled by the OR gate 21 and the AND gate 22. That is, when the data DATA is the signal R × D, it is output immediately after the end of the preamble, but when the data DATA is the signal T × D, it is output after the output Q of the counter 20 is affirmed. Simultaneously writing data DATA in the internal register in synchronism with the memory unit 23 the clock CLK, to already sequentially read out from the output Q ₁ Qn address information stored. Data DATA is signal Tx
In the case of D, the content of the register is stored when the output MMTCH from the comparing unit 24 is affirmed. This comparison unit 24
Simultaneously and sequentially compares the contents of data DATA with Q _{1 to} Qn output from the memory unit 23 in synchronization with the clock CLK. If the data DATA is T × D and they do not match at all, the signal MMTCH is affirmed,
In the case where the ATA is R × D, the signal MTCH is affirmed if at least one matches.

That is, the address comparison circuit 19 outputs the signal PEN
When D is affirmed, the operation is started, and data D
Different operations are performed when the ATA is T × D and when the ATA is R × D. If the data DATA is T × D, the source address in the signal is compared with all the addresses already stored, and if they match, the operation is terminated. It is assumed that the source address has not been set, and the source address is newly stored. That is, the storage of the terminal addresses belonging to the network 2 on the side of the data link bridge 4 as seen from the self is automatically learned and registered from the signal transmitted from the data link bridge 4. Therefore, it is possible to automatically follow a change such as movement or exchange of a terminal in the network 2 without requiring any manual labor. On the other hand, when the data DATA is R × D, the destination address included in the received signal is compared with all the addresses already stored, and if there is a match, the signal MTCH is affirmed. Then, the operation of the response signal transmission circuit 25 serving as a response signal transmission unit is started. As a result, the response signal sending circuit 25 outputs the response signal RF and the signal RFEN affirming it. If the signal RFEN is affirmed, the MED 16 encodes the response signal RF, converts it into a differential signal, and outputs it. Therefore, if the destination address in the received signal matches at least one of the stored addresses, the response signal RF is sent out, so that even if there are a plurality of data link bridges, the one including the terminal of the desired address is included. Only one data link bridge returns a response signal, and communication with a desired terminal is secured.

[0014]

However, even with such a proposal, problems still remain. For example, assuming that a terminal A is initially on the other side of the data link bridge, and the address of the terminal A is stored in the device, then the terminal A moves to this network. In this case, if another terminal B transmits to terminal A, both terminal A and the data link bridge (specifically, a communication control device connected to these terminals) transmit a response signal. Become. Therefore, if the data link bridge is closer, the terminal B can fix the path only with the data link bridge, and the terminal A cannot communicate.

[0015]

A full-duplex transmission path in which a transmitting terminal transmits a forward signal including an address of a destination terminal and receives a response signal confirming the address from the destination terminal to perform communication. In a communication control apparatus for a data link bridge of a communication network,
A storage unit that stores addresses of all terminals belonging to the communication network on the data link bridge side connected from the viewpoint of the self,
An address comparing unit for comparing a destination address in a signal received from a communication network with addresses of all terminals stored in the storage unit, and a response signal for transmitting a response signal when the comparison result has at least one matching address A response signal transmitting means having a transmitting unit and a delay circuit for delaying the response signal transmission timing by a predetermined time with respect to the response signal transmission timing in the terminal is provided.

[0016]

[0017]

According to the present invention, even if the terminal moves with respect to the data link bridge by delaying the response signal transmission timing by the delay circuit by a predetermined time from the response signal transmission timing in the terminal, the terminal side transmits the response signal. Response signal transmission is given priority, and communication with this terminal can be performed reliably.

[0018]

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIG. The same parts as those shown in FIGS. 3 to 5 are denoted by the same reference numerals. In this embodiment, a timer 2 as a delay circuit is provided between the address comparison circuit 19 and the response signal sending circuit 25.
6 is inserted. The timer 26 is intended to delay a predetermined time to the timing T _A of the response signal transmission timing T _R of the response signal transmitted by the terminal.
Here, when the maximum transmission delay time of the network of one way was T _PMAX As described above, the timing T _R is T
_R > (T _A + 2 · T _PMAX ).

In such a configuration, the timer 26 is activated when the signal MTCH is affirmed, and the predetermined timing T _R
When elapses, the output RFST is affirmed. As a result, the response signal sending circuit 25 becomes operable. That is,
Since the response signal transmission circuit 25 cannot operate immediately by the signal MTCH from the address comparison circuit 19 but operates with a delay, even if the terminal moves to the data link bridge, the response signal transmission on the terminal side has priority. And communication with the terminal can be reliably performed. Therefore, the freedom of movement of the terminal in the network is greatly improved.

Next, a modification of the present invention will be described with reference to FIG. This modification is different from the address comparison circuit 1 shown in FIG.
In the basic structure of 9, also an additional function of comparing the contents of the source address following the destination address, if there is one comparator unit 24 coincides, the data were consistent within the Q ₁ Qn Qx
(Indicating the address of the memory unit 23) is output to the memory unit 23, and the output MTCH of the comparison unit 24 is output.
2 is output to the memory unit 23. In the memory unit 23, the information of the address Qx is erased by the output MTCH2.
Here, "erasing" means, for example, that all information at the address Qx is set to "1". This is because in the case of Ethernet, the first bit of the source address information is always "0". Therefore, even if the terminal moves with respect to the data link bridge, the source side is invalidated, and communication with this terminal can be reliably performed. Therefore, the freedom of movement of the terminal in the network is greatly improved. In particular, according to the present embodiment, there is no need to delay the timing of sending a response signal, and network expansion becomes easy. Further, in the irregular communication network, the path is fixed quickly, and the use efficiency of the network is not impaired.

In FIG. 2, when DATA is R × D, the contents of the destination address following the preamble are compared with all data stored in the memory unit 23, and if there is a match, the output MTCH1 is affirmed. I do. This corresponds to the output MTCH shown in FIG.

[0023]

As described above, according to the present invention, the addresses of all the terminals belonging to the communication network on the side of the data link bridge connected as viewed from the self are stored, and the destination address in the received signal from the communication network is stored. The base station is configured to compare with the addresses of all the terminals stored in the storage unit and to transmit a response signal when the destination address in the received signal matches at least one of the stored addresses. A delay circuit delays the response signal transmission timing by a predetermined time from the response signal transmission timing in the terminal, or sets the destination address in the reception signal from the communication network to the transmission source in the transmission signal from the own communication network. The address is compared with the address, and when the comparison result with the source address matches, the address is deleted from the storage unit. Also it is possible to reliably perform communication with the terminal as has moved relative to tank bridge
This has the effect of

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a modification of the present invention.

FIG. 3 is a schematic diagram showing an example of the overall system configuration.

FIG. 4 is a block diagram showing a response signal transmitting means of the already proposed example and its periphery.

FIG. 5 is a block diagram illustrating an address comparison circuit.

[Explanation of symbols]

 1 to 3 communication network 4, 5 data link bridge 10 response signal transmitting means 23 storage unit 24 address comparing unit 25 response signal transmitting unit 26 delay circuit

Continuation of the front page (56) References JP-A-4-236535 (JP, A) JP-A-4-207649 (JP, A) JP-A-4-154335 (JP, A) JP-A-4-134945 (JP) JP-A-2-127845 (JP, A) JP-A-2-171339 (JP, A) JP-A-2-65546 (JP, A) JP-A-1-192249 (JP, A) Ricoh Technical R report NO. 16, JANUARY Y, 1987, Takashi Yano, et al., "LAN with Multi-Coupled Distributed Architecture", pages. 80-83 IEICE Technical Report Vol. 86 No. 154, SE86-69, Takashi Yano, et al., "Proposal of Local Area Network COMLAT with Multiple Connection Topology", pages. 31-36 (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 12/46 H04L 12/28 JICST file (JOIS) WPI (DIALOG)

Claims (1)

(57) [Claims] 1. A communication network having a full-duplex transmission path, in which a transmitting terminal transmits an outgoing signal including an address of a destination terminal and receives a response signal confirming the address from the destination terminal to perform communication. In a communication control device for a data link bridge, a storage unit for storing addresses of all terminals belonging to a communication network on the side of the data link bridge connected as viewed from the self, and a storage unit for storing a destination address in a signal received from the communication network. An address comparing unit that compares the addresses of all the terminals stored in the terminal with each other; a response signal transmitting unit that transmits a response signal when the comparison result has at least one matching address; A communication control device provided with a response signal transmission means having a delay circuit for delaying a signal transmission timing by a predetermined time; .