JPH0442635A - Packet communication system - Google Patents

Abstract

PURPOSE:To reduce a data storage time to process a low speed data into a packet by accommodating data of plural destinations to each block of a packet data circulated on the transmission line of a loop type local area network. CONSTITUTION:One packet consists of a control area CTL, destination address areas DA1, DA2 for two lines, packet data areas DATA1, DATA2 and a packet data management area CHK. Addresses for two lines accommodated to nodes being transmission destinations are stored in the destination address areas DA1, DA2. The packet data areas DATA1, DATA2 share 64 bytes in total and the area per line shares 32 bytes being half of the 64 bytes. Since the buffering time processing the data from one line into a packet is reduced to half of the conventional system, the data storage time for processing the low speed data into a packet is decreased.

Description

[Detailed Description of the Invention] [Summary] Regarding the packet communication method, the purpose of this invention is to shorten the data storage time for packetizing low-speed data, and to reduce the amount of time each packet data circulates on the transmission path of a loop local area network. Configure a block so that it can accommodate data for multiple destinations.

[Industrial application field]

The present invention relates to a packet communication method in which line data is packetized and transmitted, and the opposing device converts the line data back into communication.

FIG. 8 is a block diagram showing the basic configuration of a loop type local area network as an industrial application field of the present invention. In the figure, a master node 81 and slave nodes 82 to 84 are interconnected in a loop. A plurality of line terminals are connected to each slave node. In the figure, only one line terminal is shown connected to each slave node for simplicity, but in reality multiple line terminals may be connected to each slave node. The master node 81 is also called a loop monitoring node, and the slave nodes are also called terminal interface nodes.

The present invention relates to improvements in packet transmission processing and packet reception processing in each slave node.

In such loop-type local area networks, the buffering time required to packetize data from low-speed line terminals such as 9.6 Kbps or 64 Kbps is too long, so it is necessary to efficiently packetize data. be.

[Conventional technology] FIG. 9 is a diagram showing a conventional packet format.

In the figure, one packet has a control area CTL,
It consists of a destination address area DA, a source address area SA provided as needed, a packet data area DATA for transferring data for one line, and a packet data management area CHK. The control area CTL is
The data in the packet data area DATA includes a flag bit USD indicating whether it is valid or invalid.

As shown above, conventionally it was necessary to buffer and packetize one packet of data per line.

[Problem to be solved by the invention]

As mentioned above, in the past, it was necessary to buffer one packet of data per line, which caused the problem that it took a long time to accumulate data for packetization.

An object of the present invention is to shorten the data storage time for packetizing low-speed data.

[Means for Solving the Problems] FIG. 1 is a diagram explaining the principle of the present invention. In the figure, according to the present invention, each block of packet data circulating on a transmission path of a loop local area network can accommodate data for a plurality of destinations.

In one aspect of the present invention, each block of packet data includes a flag bit indicating that the transmission destination is multiple lines, the address of the transmission destination of the multiple lines, and the data to be transmitted to the transmission destination of the multiple lines. It is included.

In another aspect of the present invention, each block of packet data circulating on a transmission path of a loop local area network includes a flag bit indicating that the transmission destination is two lines, and an address of the transmission destination of the two lines; This includes data to be sent to two transmission lines.

In still another aspect of the present invention, in a loop local area network interconnecting a plurality of nodes, each node accommodates a plurality of lines, and each block of packet data circulating on a transmission path has a The flag bit indicating that the transmission destination is multiple lines, the address of the transmission destination of multiple lines, and the data to be sent to the transmission destination of multiple lines, and the flag bit indicating that the transmission destination is multiple lines. A flag bit detection section that detects the presence or absence of a flag bit, a self-node address comparison section that compares the destination address included in a received packet with the self-node address, and a receive data select when a flag bit is detected and the self-node address is detected. It is equipped with a reception data selection signal generation section that generates a signal, and receives data of a corresponding transmission destination in response to the reception data selection signal.

In still another aspect of the present invention, in a loop local area network interconnecting a plurality of nodes, each node accommodates a plurality of lines, and each block of packet data circulating on a transmission path has a The flag bit indicating that the transmission destination is 2 lines, the address of the transmission destination of 2 lines, and the data to be sent to the transmission destination of 2 lines, and the flag bit indicating that the transmission destination is 2 lines. a flag bit detection unit that detects the presence or absence of a flag bit; a self-node address comparison unit that compares the destination address included in a received packet with its own node address; It is equipped with a reception data selection signal generation section that generates a data selection signal, and receives data at a corresponding transmission destination in response to the reception data selection signal.

[Effect]

Since data for multiple destinations can be accommodated in one packet, the data accumulation time required to create one packet is significantly reduced compared to the conventional method.

[Embodiment] FIG. 2 is a diagram showing a packet data format according to an embodiment of the present invention. In the figure, one packet consists of a control area CTL, destination address areas DAI and DA2 for two lines, packet data areas DATAI and DATA2 for transferring data for two lines, and a packet data management area CHK. . The control area CTL contains a flag bit FLG indicating that this packet is data for two lines, and a packet data area D.
The data in ATA1 and DATA2 include beeps USD1 and USD2 indicating whether they are valid or invalid, respectively. The control fiW area CT L consists of 8 bits, of which only 3 bits, FLG, USDI, and USD2, are used, and the remaining 5 bits are left for other uses. The destination address areas DAI and DA2 contain the addresses of two lines accommodated in the transmission destination node. The packet data areas DATA1 and DATA2 have a total of 64 bytes, but each line occupies 32 bytes, which is half of that. Therefore, the bumping time for packetizing data from one line can be cut in half compared to the conventional technology. It is not necessarily necessary to carry data for two lines in the packet data areas DATA1 and DATA2, and only 32 bytes of data for one line may be carried in, for example, DATA1. In this case, the flag bit FLG indicates 2-line data, for example, '°1''.
The bit USD1 indicating data validity/invalidity is "1" indicating validity, and the bit USD2 is "0" indicating invalidity.

Furthermore, by increasing the destination address area and reducing the amount of data for one line, it is also possible to pack data for three or more lines into one packet.

FIG. 3 is a block diagram showing the configuration of a slave node according to an embodiment of the present invention. In the same figure, master node 3
0 and slave nodes 31 to 33 are connected in a loop. The slave node is a receiving circuit 311 and a transmitting circuit 31
2. Handling circuit 313 and high-speed processing circuit 314
The slave node 33 includes a receiving circuit 331,
It includes a transmission circuit 332, a handling circuit 333, and a high-speed processing circuit 334. It is assumed that the line A and line B of the slave node 31 are connected to the line C and line R of the slave node 33, respectively.

When data from lines A and B is buffered and packetized by the transmission circuit 312 in the slave node 31, the data from at least one of each line is halved.
Once the packet has been buffered, it is converted into the packet data format of the embodiment of the present invention shown in FIG. In the slave node 33, the packet data that has passed through the high-speed processing circuit 334 is analyzed by the handling circuit 333, and then sent to the receiving circuit 331.
receives the data on line C1.

FIG. 4 shows the handling circuit 313 or 3 shown in FIG.
33 is a block diagram showing the configuration of the computer. The configuration shown in the figure makes it possible to send and receive data from two lines in one packet. The handling circuit shown in FIG. 4 includes a flag bit detection unit 41 that detects a flag bit indicating that a received packet is a two-line packet, and a self-node that compares the destination address in the received packet with the self-node address. It includes an address comparison section 42, a received data selection section 43, a packet processing section 4, and a packet data multiplexing section 45.

When a flag bit indicating that the received packet is a 2-line packet is detected, and the destination address matches the own node address, the received data select signal generation unit 43 selects the packet data for each of the 2-line data. A select signal SEL for reception is generated and sent to the receiving circuit, and a control signal for turning off the USD focus is supplied to the packet data multiplexing section 45.

The packet processing section 44 generates bucket + data as necessary, and the packet data multiplexing section 45 multiplexes it with the received packet, and turns off the USDl or USD2 bit according to the control signal from the received data select signal generation section 43. generate a transmission packet and send it to the loop.

When the destination address of only one line matches the own node address, only the corresponding select signal is generated and the USD
Turn off only one of the corresponding bits.

FIG. 5 is a detailed block diagram of the packet handling circuit shown in FIG. 4, and the same parts as in FIG. 4 are given the same reference numerals. In FIG. 5, the flag bit detection unit 41 is a flip-flop FF that latches the flag FLG in the received packet using the flag timing FLG as a clock.

The own node address comparison unit 42 is a comparator COMP that compares the own node address with the destination address DAI or DA2 in the received packet.

The received data selection signal generation section 43 includes a flip-flop 431 that latches tJsDl in the received data using the timing of USDl as a clock, a flip-flop 432 that latches USD2 in the received data using the timing of USD2 as a clock, and a flip-flop 432 that latches tJsDl in the received data using the timing of USD2 as a clock. An AND gate 433 outputs the AND of the outputs of the flip-flops 431 and 432; AND gate 435 using the address signal timing DAI as a clock, and AND gate 43 using the address signal timing DAI as a clock.
AND with the flip-flop 436 that latches the output of 4 and the timing signal DA2 of the address signal as a clock.
Flip-flop 43 latches the output of gate 435
7, USDI reset signal and flip-flop 43
a NAND gate 438 that performs a NAND with the output of 6;
A NAND gate 439 that NANDs the reset signal of USD 2 and the output of the flip-flop 437;
AN which ANDs the outputs of ND gates 438 and 439
D gate 440.

The packet data multiplexer 45 includes a delay circuit (DLY) 451 that delays the received packet by the time necessary for multiplexing it with the USD bit that is turned on or off by the received data select signal generator 43, and a received data select signal. US output from the AND gate 440 of the generation unit 43
AND for multiplexing the D bit and the output of the delay circuit 451
A selector (SEL) selects and outputs either the output of the packet processing unit 44 or the output of the AND gate.
)453.

Next, the operation of the circuit shown in FIG. 5 will be explained.

When the flag bit detection unit 41 detects a flag bit indicating that the received packet data has data for two lines, and the own node address comparison unit 42 detects that the packet data is addressed to the own node, it is determined whether the data is valid or not. I indicating invalidity
Based on the JSD bit, the reception data selection signal generation unit 4
3, select signals SEL 1 and 5EL2 for receiving packet data for each of the two lines of data.
generate.

When the select signal SEL 1 or 5EL2 is generated,
In the packet data multiplexing section 45, the USD bit is turned off, the packet data multiplexing section 45 multiplexes the data into a frame, and transmits the packet data.

More specifically, flip-flops 41, 431, and 4
32, flag bit, USD1 bit, and /
Or detect USD2 bit. If the packet data received by the comparator 42 is addressed to the own node, the AND gate 434 and/or 435 becomes valid, and the flip-flop 436 and/or 437 latches the received data select signal that becomes valid at the timing of the destination address.
Generate data select signals R3EL1 and/or R3EL2 for addresses DAI and/or DA2. This reception data selection signal allows 1/2 packets of each of the two line data to be received separately.

Furthermore, if the flip-flop 41 does not detect the flag bit, the flip-flop 431 detects the USD
Detects the I bit, generates a receive data select signal 5ELL valid for one packet, and converts one line data into one
The number of packets will be received.

The USD bit of the received data is connected to the NAND gate 438.
and/or turn off 439 and AND gate 440;
The data delayed by the delay circuit 451 and the turned-off USD bit are multiplexed by an AND gate 452.

FIG. 6 is a block diagram showing the configuration of a transmitting circuit according to an embodiment of the present invention. In the same figure, a first-in-first-out (FIFO) memory 61, a write control section 62, a transmission packet recognition section 63, a readout control section 64, and a first-in-first-out (FIFO) memory 61, a transmission packet recognition section 63, a readout control section 64, and a first transmission circuit 312 or 332 (FIG. 3) are shown in FIG. It includes a header creation circuit 65 and a multiplexer 66.

When the FIFO memory 61 receives a write timing signal from the write controller 62 at a terminal W, it takes in data from the line from a data input terminal DI in response to the write timing signal. The transmission packet recognition unit 63 determines the F based on the write timing signal from the write control unit 62.
The read timing of data from the IFO memory 61 is determined, thereby controlling the read control unit 64 to provide a read timing signal to the terminal R of the FIFO memory 61, and prompting the packet header creation circuit to create a packet header. When the FIFO memory 61 receives the read timing signal at the terminal R, it outputs data including one line's worth of data DATA or two lines' worth of data DATAI and DATA2 from the data output terminal Do in response. The packet data creation circuit 65
A packet header including flags such as LG, USD, DA, and SA is created and output. The data from the FIFO memory 61 and the packet header from the packet generation circuit 65 are multiplexed by a multiplexer 66 and sent out to the loop as a transmission packet.

FIG. 7 is a block diagram showing an embodiment of the packet header creation circuit of FIG. 6. In the figure, the packet header creation circuit 65 is a RAM that stores a packet header table.
71, and a flip-flop 72 that outputs data from the RAM 71 using a packet header read timing signal as a clock. FLG is stored in RAM71 in advance.

Flags such as USD, USD, 1, USD2, DA, and SA are set. These flags are set by receiving the line number of the transmission packet at terminal AD in response to the MPU write timing signal applied to terminal W. The RAM 71 is a read control unit 64
When the packet header read timing signal from (FIG. 6) is received at the terminal R, the above flag is output from the terminal DT.

The flip-flop 72 is connected to the readout control unit 64
In response to the packet header read timing signal from (FIG. 6), the packet header consisting of these flags is latched and output from the output terminal Q with a delay of one clock.

On the other hand, data (DATA, DATAI,
, DATA2) are outputted from the terminal DO in accordance with the timing signal applied to the terminal R, and the timing signal applied to the terminal R is outputted by the selector 70 at an appropriate timing. That is, the selector 70 selects the DATA read timing signal, the DATAI read timing signal, and the DA
Outputs one of the read timing signals of TA2.

The data output from the F I FO 61 and the packet header output from the flip-flop 72 are sent to the selector 73.
The packets are multiplexed and sent out on the loop as transmission packets.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, data for multiple lines is included in one packet.
The data accumulation time for packetizing low-speed data is
This is shorter than the conventional method, and in particular, when transmitting data on two lines with one packet, the data storage time for packetization becomes half the time compared to the conventional method.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a diagram showing a packet/seven data format according to an embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of a slave node according to an embodiment of the present invention. Figure 4 shows the handling circuit 313 or 3 shown in Figure 3.
5 is a detailed block diagram of the packet handling circuit shown in FIG. 4, FIG. 6 is a block diagram showing the configuration of the transmitting circuit according to the embodiment of the present invention, and FIG. FIG. 6 is a block diagram showing an embodiment of the packet header creation circuit; FIG. 8 is a block diagram showing the basic configuration of a loop local area network as an industrial application field of the present invention; FIG. FIG. 3 is a diagram showing a format. In the figure, 30 is a master node, 31 to 33 are slave nodes, 311 and 331 are receiving circuits, 312 and 332 are transmitting circuits, 313 and 333 are handling circuits, 41 is a flag bit detection unit, and 42 is a self-node address comparison unit , 43 is a received data selection signal generation section, 44 is a packet processing section, and 45 is a packet data multiplexing section.

Claims (1)

[Scope of Claims] 1. A packet communication system characterized in that data for multiple destinations can be accommodated in each block of packet data circulating on a transmission path of a loop local area network. 2. Each block of packet data circulating on the transmission path of the loop local area network includes a flag bit indicating that the transmission destination is multiple lines, the address of the transmission destination of the multiple lines, and the transmission destination of the multiple lines. A packet communication method characterized by including data to be transmitted. 3. Each block of packet data circulating on the transmission path of a loop local area network has two transmission destinations.
A packet communication method characterized by including a flag bit indicating that it is a line, addresses of transmission destinations of the two lines, and data to be transmitted to the transmission destinations of the two lines. 4. In a loop-type local area network that interconnects multiple nodes, each node accommodates multiple lines, and each block of packet data circulating on the transmission path is sent to multiple lines. A flag that includes a flag bit indicating that the transmission destination is a plurality of lines, the address of the transmission destination of the plurality of lines, and data to be transmitted to the transmission destination of the plurality of lines, and detects the presence or absence of the flag bit indicating that the transmission destination is a plurality of lines. a bit detection section, a self-node address comparison section that compares the destination address included in the received packet and the self-node address, and generates a received data select signal when the flag bit is detected and the self-node address is detected. 1. A packet communication system, comprising: a reception data selection signal generating section for receiving data at a corresponding transmission destination in response to the reception data selection signal. 5. In a loop-type local area network that interconnects multiple nodes, each node accommodates multiple lines, and each block of packet data circulating on a transmission path has two transmission destinations. a flag bit indicating that
A flag bit detection unit that detects the presence or absence of a flag bit indicating that the transmission destination is the second line by including the data to be transmitted in the transmission destination of the two lines, and the transmission destination address and own node address included in the received packet. a self-node address comparator that compares the flag bit and a receive data select signal generator that generates a receive data select signal when the flag bit is detected and the own node address is detected; A packet communication method characterized in that data of a corresponding transmission destination is received according to the transmission destination.