RU2810546C1 - Capacitive energy storage charger - Google Patents

Abstract

FIELD: chargers for capacitive energy storage devices.

SUBSTANCE: invention can be used in high-voltage, high-power electrophysical units with a high level of stored energy. A capacitive energy storage charger comprising a constant voltage source, two series-connected metering capacitors, two series-connected diodes, two series-connected transistors shunted by freewheeling diodes, a high-voltage transformer, a high-voltage rectifier, a control device comprising a clock pulse generator, and a two-channel driver, a choke, two groups of additional capacitors, a delay generator, and two 2I logic elements are introduced.

EFFECT: increased reliability of the charger and expanded functionality.

1 cl, 8 dwg

Description

The invention relates to chargers (chargers) of capacitive energy storage devices (CES) and can be used in high-voltage, high-power electrical installations with a high level of accumulated energy.

Currently, in such installations, transistor-capacitor chargers are widely used, built on the basis of high-frequency converters with a resonant nature of processes in power circuits. The dosed method of transferring energy in such devices from the supply network to the CES makes it possible to quite simply regulate the charging speed and provide a parametric limitation of the current (output power) in the event of emergency conditions in the output circuits.

Transistor-capacitor chargers of high frequency are known, based on series resonant inverters, in which the capacitors of the resonant circuit can operate in bipolar and unipolar voltage modes [1...5].

The disadvantage of a charger with a series resonant inverter, in which the capacitors of the resonant circuit operate in a bipolar voltage mode, is the significant unevenness of current and power consumption from the network and the low utilization factor [2] of the constant voltage source , Where - respectively, the maximum and average value of the active power consumed by the charger during the charging cycle of the CES. This leads to an increase in installed capacity and cost of the primary DC voltage source. In addition, when the power of the charger and the constant voltage source are commensurate, this nature of energy consumption in the mode of periodic repetition of charging cycles leads to voltage ripples of the primary source (mains), which reduces the reliability of other consumers [4].

A charger with a series resonant inverter does not have this drawback, in which the capacitors of the resonant circuit operate in a unipolar voltage mode and perform the function of dosing the energy transferred to the CES (dosing capacitors) [2, 3, 5].

This device, selected as a prototype, contains a constant voltage source, two series-connected metering capacitors connected to the positive and negative terminals of the constant voltage source, two series-connected diodes, the cathode of the first of which is connected to the positive terminal of the constant voltage source, and the anode of the second to the negative terminal of this source, and the common points of the metering capacitors and the common points of the diodes are interconnected, two series-connected transistors, shunted by freewheeling diodes, the collector of the first of which is connected to the positive terminal of the constant voltage source, and the emitter of the second to the negative terminal of this source, a high-voltage transformer , one terminal of the primary winding of which is connected to the common point of the transistors, and the second to the common point of the diodes, a high-voltage rectifier, the input of which is connected to the terminals of the secondary winding of the transformer, and the output is connected to a capacitive energy storage device, a control device that generates control pulses supplied to the control circuit transistors.

When the transistors are periodically locked/unlocked, the metering capacitors are charged and discharged and energy is metered from the DC voltage source to the CES.

At constant frequency following the transistor control pulses, the power transferred to the CES is constant and is determined by the formula [2]

,

Where - capacity of the dosing capacitor; - DC voltage source voltage; - power consumed by the charger from a constant voltage source; - Efficiency of the charger.

As a result, during almost the entire charging cycle of the CES, with the exception of a relatively short initial stage [2] of the cycle duration, the charger operates in a constant power consumption mode, while the constant voltage source utilization factor is .

A common disadvantage of the known devices is the presence of dynamic losses in transistors.

So, in a charger with a two-polar voltage mode of operation of the resonant circuit capacitors, each time the power transistors are unlocked, their output capacitances are discharged with dissipation of the energy accumulated in these containers in the internal structure of the transistor. The power loss released in this case , determined by the formula

reduces the efficiency of the charger, especially at higher frequencies in tens of kHz.

The disadvantage of a charger with a unipolar voltage mode of operation of the resonant circuit capacitors (charger with metering capacitors) is that at the initial stage of charging, until the CES voltage reaches the limit value , determined from formula (3) given in [2],

Where And - respectively, the relative and absolute duration of the repetition period of control pulses of the memory transistors (clock period); - period of natural oscillations resonant circuit; - relative value of the boundary voltage of the CES, reduced to the primary winding of the high-voltage transformer;Q - quality factor of the resonant circuit of the charger, switching of the charger transistors occurs at a non-zero value of the current flowing through them [2], and is accompanied by significant switching losses. This leads to a sharp and significant increase in the temperature of the transistor crystal during the initial charging stage [2]. At the final stage of charging in the known device, there are also dynamic losses in the transistors each time they are turned on, due to the discharge of their output parasitic capacitances with dissipation of the energy accumulated in these containers in the internal structure of the transistor.

Due to this, the efficiency and reliability of the known device are reduced. In addition, switching processes lead to interference in control and information networks, both storage devices and electrical installations, which causes failures in their operation and distortion of information obtained during a physical experiment. This reduces the reliability of operation and can lead to emergency modes of the charger and electrical installations in general, as well as to the need to repeat physical experiments, which increases the cost of their implementation, which, in turn, narrows the functionality of the known device and the scope of its application.

The proposed invention solves the problem of increasing the reliability of the UES charger and expanding its functionality.

The technical result from the use of the invention is to increase the efficiency and reduce the temperature of the transistor crystal during the charging cycle of the CES and increase the level of electromagnetic compatibility of the charger.

The specified technical result is achieved by the fact that in the CES memory, containing a constant voltage source, two series-connected metering capacitors, shunted by diodes, two series-connected transistors, shunted by reverse diodes, the collector of the first of which is connected to the positive terminal of the constant voltage source, and the emitter of the second to the negative terminal of this source, a high-voltage transformer, the primary winding of which is connected to the common points of metering capacitors and series-connected transistors, a high-voltage rectifier, to the output of which a capacitive energy storage device is connected, a control device containing a two-channel clock pulse generator having one input, which receives an external signal start of the charger, and two outputs that are connected to two inputs of a two-channel driver that generates transistor control pulses with a duration equal to half the clock period minus the pause interval, a choke is introduced, two groups of additional capacitors, each of which contains two series-connected capacitors connected to the source terminals constant voltage, and the common point of the first group is connected to the common point of series-connected transistors, and the common point of the second group is connected to the first output of the inductor, the second output of which is connected to the common point of the transistors, as well as a delay generator, the input of which is connected to the input of the clock pulse generator, generating a rectangular pulse, the front of which is delayed relative to the front of the external charger start signal by an interval equal to a quarter of the clock period minus the pause interval generated by the driver, and the output of the delay generator is connected to the first inputs of two logical elements “2I”, the second inputs of which are connected, respectively, to the first and second outputs of the two-channel clock generator, and the outputs of the first and second logical element “2I” are connected, respectively, to the first and second input of the two-channel driver.

The introduction of these elements ensures switching of transistors at zero voltage applied to them and the absence of switching losses throughout the CES charging cycle. This allows you to reduce the temperature of the transistor crystals during the charging process, increase the efficiency, reliability of the charger and its level of electromagnetic compatibility.

Figure 1 shows the electrical circuit of the UES charger, where: 1 - constant voltage source, 2.3 - metering capacitors, 4.5 - shunt diodes, 6.7 - transistors, 8.9 - reverse shunt diodes, 10 - high-voltage transformer , 11 - high-voltage rectifier, 12 - capacitive energy storage, 13 - clock generator, 14 - driver, 15, 16 - additional capacitors of the first group, 17, 18 - additional capacitors of the second group, 19 - inductor; 20 - delay generator; 21, 22 - logical elements “AND”.

Figure 2 shows the time diagrams of the CES charger at the initial stage of the CES charging cycle.

Figure 3 shows the time diagrams of the CES charger in the main and final stages of the CES charging cycle.

In the diagrams of Fig. 2 and Fig. 3 the letters indicate: a, b - control pulses of transistors 6 and 7, respectively, at the outputs of the driver 14; c, d - voltages on metering capacitors 2 and 3, respectively; d - current of the primary winding of transformer 10; e - current flowing through the winding of the inductor 19; g - current of transistor 6; h - current of reverse shunt diode 8; and - drain-source voltage of transistor 6 and capacitor 15; k - current of transistor 7; l - current of reverse shunt diode 9; m is the drain-source voltage of transistor 7 and capacitor 16; n, p - currents flowing through additional capacitors of the first group 15, 16, respectively.

Figure 4 shows the timing diagrams of the CES charger at the first clock periods of the CES charging process.

In the diagrams of Fig. 4 the letters indicate: a1 - external signal to start the charger; b1, c1 - voltages at the outputs of clock pulse generator 13; g1 - output voltage of delay generator 20; d1, e1 - output voltages of logic elements 21, 22; z1, z1 - output voltages of driver 14; u1 - current flowing through the winding of inductor 19.

In fig. 5 - 8 show the timing diagrams of the UES charger, obtained on a simulation model of the proposed device with parameters taken as an example: power supply voltage 1 - 500V; capacity of dosing capacitors 2, 3 - µF; the leakage inductance of the windings of the high-voltage transformer 10, which performs the function of an element of the resonant circuit, is 10 μH; transformer ratio 10 ; capacity of additional capacitors 15, 16 - 30 nF; capacity of additional capacitors 17, 18 - 100 μF; energy storage capacity 12 - mF; repetition period of transistor control pulses (clock period) - mks; inductance of the additional choke is 19 - 80 μH.

In fig. Figure 5 shows timing diagrams of the operation of the proposed device with a delay generator as part of the memory control system.

In fig. Figure 6 shows time diagrams of the switching processes of the transistor (6 or 7) of the charger in the proposed device with a delay generator as part of the charger control system in the interval highlighted in Fig. 5 dashed oval curve.

In fig. Figure 7 shows timing diagrams of the memory operating without a delay generator as part of the memory control system.

In fig. Figure 8 shows time diagrams of switching processes of a transistor (6 or 7) of a charger without a delay generator as part of the charger control system in the interval highlighted in Fig. 7 dashed oval curve.

In the diagrams of fig. 5 - 8 letters indicate: a2 - drain-source voltage of transistor 6 (7); b2 - drain current of transistor 6 (7); b2 - current flowing through the winding of inductor 19.

The device contains a constant voltage source 1, to the output of which are connected two series-connected metering capacitors 2, 3, shunted by diodes 4, 5, as well as two series-connected transistors 6, 7 shunted by reverse diodes 8, 9, and the collector of the first transistor 6 is connected to the positive terminal of the constant voltage source, and the emitter of the second 7 to the negative terminal of this source 1, high-voltage transformer 10, the primary winding of which is connected to the common points of metering capacitors 2, 3 and series-connected transistors 6, 7, high-voltage rectifier 11, to the output of which a capacitive storage is connected energy 12, inductor 19, two groups of additional capacitors 15, 16 and 17, 18, each of which contains two series-connected capacitors connected to the terminals of the constant voltage source 1, and the common point of the first group 15, 16 is connected to the common point of series-connected transistors 6, 7, and the common point of the second group 17, 18 is connected to the first terminal of the inductor 19, the second terminal of which is connected to the common point of the transistors 6, 7, a control device containing a two-channel clock generator 13, having one input, which receives an external signal start of the charger, and two outputs that are connected to the two inputs of the two-channel driver 14, which generates control pulses for transistors 6, 7, a delay generator 20, the input of which is connected to the input of the clock pulse generator 13, and the output of the delay generator 20 is connected to the first inputs of two logic elements 21, 22, the second inputs of which are connected, respectively, to the first and second outputs of the two-channel clock generator 13, and the outputs of the first and second logical elements 21, 22 are connected, respectively, to the first and second inputs of the two-channel driver 14.

The operating principle of the proposed device is illustrated by the diagrams shown in Fig. 2, 3, 4 and is as follows.

The memory control system generates control pulses for transistors 6, 7, time-shifted relative to each other by their half-cycle and having a duration , equal to their half-period (clock half-period ) minus the duration of the fixed pause

.

Fixed pause duration determined from the condition of ensuring during it the charging of capacitors 15, 16, shunting transistors 6, 7 from zero to supply voltage The charger is at close to zero CES currents at the end of its charging cycle, and is installed by selecting or setting driver 14 with the required value .

In the interval of the conducting state of transistor 6, an oscillatory discharge of the metering capacitor 2 occurs along the circuit: capacitor 2, transistor 6, primary winding of the transformer 10, capacitor 2. In this case, the energy of the metering capacitor 2 through the transformer 10, rectifier 11 is transferred to the CES, and part of it is accumulated in magnetic field of the leakage inductances of the windings of the transformer 10, which perform the function of a choke of the resonant circuit formed by these inductances and metering capacitors 2, 3. At the same time, the metering capacitor 3 is charged, since the equality is always satisfied

,

Where - voltage on metering capacitors 2 and 3, respectively.

When discharging the metering capacitor 2 to zero and charging the metering capacitor 3 to the supply voltage and at the moment (curves “c” and “d” in Fig. 2 and 3) diode 4 is unlocked, shunt metering capacitor 2 is unlocked and the resonant circuit current is closed along the circuit: shunt diode 4, transistor 6, primary winding of transformer 10, shunt diode 4. Energy, The leakage inductance accumulated in the magnetic field of the transformer windings is transmitted through the transformer 10 and the output rectifier 11 to the CES 12. In this case, the current of the primary winding of the transformer 10 is reduced. At the same time, an increasing current of inductor 19 flows through the open transistor 6 along the circuit: transistor 6, inductor 19, additional capacitor 17, transistor 6.

The control pulse of transistor 6 ends at the moment (curve “a” in Figs. 2 and 3) and then after a fixed pause clock generator 13 at time supplies a control pulse to transistor 7 (curve “b” in Figs. 2 and 3).

Since the moment , transistor 6 is turned off and its current (curve “g” in Figs. 2 and 3) quickly (tens of nanoseconds [6]) decreases to zero with a relatively slow (hundreds of nanoseconds) almost linear increase in the drain-source voltage on it (curve “ and" in Figs. 2 and 3). This nature of the processes on the turn-off transistor 6 is due to the charging of the capacitor 15, which is connected in parallel to the transistor 6, with a practically constant current over this interval equal to half the total current of the resonant circuit and the current of the inductor 19 (curve “n” in Fig. 2, 3) and is classified as “ soft" switching at zero voltage (PVN) [7 p. 318].

Simultaneously with the increase in voltage on capacitor 15, capacitor 16 is discharged, shunting transistor 7, with the same current, the voltage on which decreases linearly (curve “m” in Figs. 2 and 3) in accordance with the equality

,

Where - voltages on additional capacitors 15 and 16, respectively.

At the initial stage of the CES charging cycle, the charge/discharge processes of each of the additional capacitors 15, 16 are caused by half of the total current (curves “n” and “p”, respectively, in Fig. 2, 3) of the primary winding of the transformer 10 (curve “d” in Figs. 2 and 3) and inductor 19 (curve “e” in Figs. 2 and 3) due to the energy accumulated in the magnetic field of inductor 19 and in the magnetic field of the leakage inductances of transformer 10.

When capacitor 16 discharges, to zero at the moment of time (curve “m” in Figs. 2 and 3) the reverse diode 9 is unlocked (diode current - curve “l” in Figs. 2 and 3), the shunt transistor 7, and the resonant circuit current begins to flow through the circuit: reverse diode 9 of transistor 7 , primary winding of transformer 10, shunt diode 4, constant voltage source 1, reverse diode 9. The energy remaining from the previous interval in the magnetic field of the windings of transformer 10 is transmitted through the transformer and output rectifier 11 to the CES 12, as well as to the constant voltage source 1 At the same time, the current of inductor 19 flowing through the circuit begins to decrease: reverse diode 9 of transistor 7, inductor 19, additional capacitor 18, reverse diode 9 due to the transfer of its energy to a constant voltage source, and the discharge of metering capacitor 3 begins along the circuit: capacitor 3 , the primary winding of the transformer 10, the reverse diode 9, the capacitor 3. In this case, a small reverse voltage is applied to the transistor 7 (curve “m” in Fig. 2 and 3), equal to the voltage drop across the open diode 9 (on the curve “m” in Fig. 2 and 3, this drop is assumed to be zero).

After the total current of the primary winding of the transformer 10 and the inductor 19 flowing through the reverse diode 9 is reduced to zero, it changes its direction and begins to flow through the transistor 7 (curve “k” in Fig. 2, 3), to which already starting from the moment of time (Fig.2, 3) a control pulse is supplied. This switching also corresponds to “soft” switching at zero voltage [7].

At the main and final stage of the CES charging cycle, the resonant circuit current flows in the conductivity range of the diode 4 shunting the metering capacitor 2, at the usually selected clock frequency ratio converter and natural frequency resonant circuit < [2] decreases to zero before the moment turning off transistor 6 (see Fig. 3). Therefore, the charge/discharge of each of the additional capacitors 15, 16 is due to only half the current of the inductor 19 and, consequently, the rise/fall time of the voltage at the power electrodes of the transistors increases. Otherwise, the sequence and essence of the processes occurring in the memory during the considered time intervals remains unchanged.

The described nature of the switching processes when switching on/off the storage transistors is confirmed by the diagrams in Figs. 5, 6, obtained on a simulation model of the proposed device in the MATLAB Simulink environment.

To ensure the process of “soft” switching of transistors and increase the reliability of the charger, it is necessary to ensure constant amplitude values throughout the entire charging cycle of the CES, starting from the first clock period inductor current 19 (curve “e” Fig. 2, 3), at which switching occurs.

This is achieved by introducing into the circuit of the proposed device a delay generator 20, the input of which is connected to the input of the clock pulse generator 13, and the output of the delay generator 20 is connected to the first inputs of two logic elements 21, 22, the second inputs of which are connected, respectively, to the first and second outputs clock generator 13. In turn, the outputs of logic elements 21, 22 are connected, respectively, to the first and second input of the two-channel driver 14.

Delay in unlocking at the beginning of the CES charging cycle of the first of the switched-on transistors for an interval duration equal

,

provides a constant amplitude value of the inductor current 19 equal to by the end of the first clock half-cycle and all subsequent periods (Fig. 2, 3, 4).

When an external signal to start the charger is received (curve a1) in Fig. 4) clock pulse generator 13 begins to generate antiphase rectangular pulses with a clock period at its outputs and a duration equal to half the clock period (curves b1 and b1 in Fig. 4). At the same time, the delay generator 20 generates a rectangular pulse (curve r1 in Fig. 4), the front of which is delayed relative to the front of the external start signal (curve a1 in Fig. 4) of the charger for an interval duration equal

.

This pulse arrives at the first inputs of two logical elements 21, 22 “2I”,

the second inputs of which receive the output signals of the clock pulse generator 13. As a result, at the outputs of logic elements 21, 22 “2I” two sequences of rectangular pulses are formed (curves d1 and e1 in Fig. 4), the first pulse of one of which (curve d1 in Fig. 4) has a duration , equal to

.

The output signals of logic elements 21, 22 are then supplied to the inputs of driver 14, which generates control pulses (curves w1 and z1 in Fig. 4) by transistors 6 and 7 with a reduced value duration , determined from the equality

Calculated current expression inductor 19 in the interval of the conducting state of transistors 6 and 7 of the memory is determined from the expression

Where - inductance of the inductor 19, - voltage of additional capacitors 17, 18.

When choosing a container additional capacitors 17, 18 from the condition

voltage on them does not depend on the inductor current 19 and is equal to .

The current of the inductor 19 in accordance with formula (2) at the conductivity intervals of transistors 6, 7 changes according to a linear law

Where - initial value of the inductor current at the corresponding interval 19.

According to expression (4), taking into account (1) and (2), the current increment throttle 19 at interval , on which , will

During the first clock periods of the charger operation, the total charging/discharging current of capacitors 15, 16 has relatively large values and the actual value of the interval The charge/discharge of these capacitors (see Fig. 2) is relatively small. Under these conditions, the duration of the increase in the current of the inductor 19 from zero to the highest value during these periods according to the diagrams in Fig. 4 is also a quarter of a clock period , therefore the increments and amplitude values The inductor currents are also the same during the first clock periods of the memory. This ensures stable switching conditions for transistors 6 and 7 when charging the CES.

In the absence of a delay of the first pulse of one of the sequences of rectangular pulses supplied to the inputs of the driver 14, when transistors 6, 7 are turned on, a transient oscillatory process is observed in the current curve of the inductor 19.

This leads to fluctuations in the amplitude of the inductor current and disruption of the switching process, incomplete discharge of one of the capacitors 15, 16 (for example, capacitor 15, curve a2 in Fig. 8)) during the pause interval and its subsequent discharge with a pulsed current of large amplitude (curve b2 in Fig. 8) when transistor 6 is unlocked with the release of energy accumulated in capacitor 15 in the internal structure of this transistor. The discharge causes overheating of the semiconductor structure of the transistor, which reduces the reliability of the device.

In addition, the transient process is accompanied by a significant (up to double value, curve b2 in Fig. 8) excess current of the inductor 19 of its amplitude value in steady state, which increases its calculated energy intensity, weight and dimensions.

Delay of the first pulse supplied to the input of driver 14 by interval eliminates fluctuations in the amplitude of the inductor current and abnormal switching modes of the memory transistors (see Fig. 5, 6), increases the reliability of its operation, and also makes it possible to reduce the energy consumption, weight and dimensions of the inductor 19.

Information sources:

1. Semiconductor chargers for capacitive energy storage devices / O.G. Bulatov, V.S. Ivanov, D.I. Panfilov. - M.: Radio and communication, 1986. - 160 p. (p.43).

2. Kopelovich E.A., Khvatov S.V., Vanyaev V.V., Troitsky M.M., Flat F.A. Transistor-capacitor chargers for megajoule capacitive energy storage devices. Electrical engineering, No. 7, 2010. - p. 11-16.

3. Pokryvailo A., Carp C., Scapellati C. A High Power High Voltage Power Supply for Long Pulse Applications // URL: www.spellmanhv.com

4. Knysh V.A. Semiconductor converters in storage capacitor charging systems. - Leningrad: Energoatomizdat, 1981. - 160 p.

5. Utility model patent No. 94089 of the Russian Federation, IPC N 03 K 3/53. Storage capacitor charger. Kopelovich E.A. Publ. in the Bulletin “Inventions, utility models”, 2010, No. 13.

6. https://www.infineon.com/dgdl/Infineon-FF2MR12KM1P-DataSheet-v02_00-EN.pdf?

7. Meleshin V.I. Transistor converter technology. - M.: Tekhnosphere, 2006. -632 p.

Claims (1)

A capacitive energy storage charger containing a constant voltage source, two series-connected metering capacitors, shunted by diodes, two series-connected transistors, shunted by reverse diodes, the collector of the first of which is connected to the positive terminal of the constant voltage source, and the emitter of the second to the negative terminal of this source, a high-voltage transformer, the primary winding of which is connected to the common points of metering capacitors and series-connected transistors, a high-voltage rectifier, to the output of which a capacitive energy storage device is connected, a control device containing a clock pulse generator having one input, which receives an external signal to start the charger, and two outputs that are connected to two inputs of a two-channel driver that generates transistor control pulses with a duration equal to half the clock period minus the pause interval, characterized in that a choke is introduced into the device, two groups of additional capacitors, each of which contains two series-connected capacitors connected to terminals of a constant voltage source, and the common point of the first group is connected to the common point of series-connected transistors, and the common point of the second group is connected to the first terminal of the inductor, the second terminal of which is connected to the common point of the transistors, as well as a delay generator, the input of which is connected to the input of the clock generator pulses, forming a rectangular pulse, the front of which is delayed relative to the front of the external charger start signal for an interval equal to a quarter of the clock period minus the pause interval generated by the driver, and the output of the delay generator is connected to the first inputs of two logical elements “2I”, the second inputs of which are connected, respectively, to the first and second outputs of the two-channel clock generator, and the outputs of the first and second logical elements “2I” are connected, respectively, to the first and second inputs of the two-channel driver.