RU2808721C1 - Device of the third decisive circuit for accelerated search and efficient reception of broadband signals - Google Patents

Abstract

FIELD: broadband radio communications; radio navigation

SUBSTANCE: invention relates to data processing and decision-making devices in broadband radio communications and radio navigation. The technical result consists in reducing the search time based on the delay of spread spectrum signals (SSS) and increasing the reliability of SSS reception and processing of decisions by implementing elements of the theory of the “third decision circuit” for receiving and processing derivative nonlinear sequences and making decisions by means of staggered reception procedures for processing “according to the form” of periodic intercorrelation and partial correlation functions. This result is achieved by the fact that in the device of the third decision circuit, the buses of the corresponding parallel outputs of the corresponding gates are connected to the corresponding buses of the first and second parallel inputs of the final adder, the output of which is connected to the input of the decision device, the first and second outputs of which are the decisive outputs of the device.

EFFECT: reducing the search time based on the delay of spread spectrum signals (SSS) and increasing the reliability of SSS reception and processing of decisions.

1 cl, 20 dwg

Description

The invention relates to methods and devices for data processing and decision-making in broadband radio communications and radio navigation (SHRSRN), where the stage of effective and reliable reception and decision-making on the appropriate criterion for the optimal reception of spread spectrum information signals (SRS), manipulated by some pseudo-random sequence, is necessarily preceded by synchronization stage [1, 2].

From the point of view of implementing this synchronization in SRSRN, a method of searching for SRS by delay is known, which uses a priori information about the location and structure of segments of pseudo-random sequences [2] to reduce the average search time, where the current signal delay is determined by the threshold detection of the value of the cross-correlation function between some short reference sequence and a regularly located segment of a similar structure of the received signal.

The most important disadvantages of this method are, firstly, its applicability only for linear recurrent M-sequences and for which their segment structure has been studied, and secondly, the threshold assessment is carried out against the background of comparison with very large levels of lateral bursts of the segment of the cross-correlation function, which is noticeable reduces the likelihood of correctly detecting current energy.

Also close to the claimed one is the method of searching for SRS, the essential features of which are the weighted summation of the responses of several digital matched filters tuned to several different PSP elements with an a priori known structure, having minimal cross-correlation with respect to each other and unevenly located along the length of the received manipulation sequence . In this case, the summation weights are determined by the order of the segments, and the current delay is determined by the fact that the threshold value of the weighted sum of responses of matched filters is exceeded [3]. This method has a number of disadvantages:

a reduction in the average search time is ensured only under close to ideal interference conditions, when the probability of a false detection or missing a PSP segment is very small;

the use of a limited class of PSPs, studied in detail from the point of view of the cross-correlation properties of the constituent segments;

significant hardware costs for building a block of digital matched filters to search for long-length memory bandwidths.

A device is known that implements a method for accelerated search of broadband signals according to the patent [4]. This device performs:

the use of a priori information about the relationship between the value of the clock number of the current delay of the received signal and the clock of detection of the total values of cross-correlation between the received and reference sequences;

search by delay of signals manipulated by derivative nonlinear recurrent sequences (RPS) is carried out in parallel through 2 channels, in one of which a sequentially repeating length component is used as a reference in a different as a result of of the PVCF values accumulated in each of the 2 channels, the maximum is selected and the corresponding numbers of mutual shift cycles are recorded relative to the initial corresponding and further according to the received determine the values of cyclic shifts from ₁ and ₂ generating components according to the following relationships:

then, through the parallel formation of 2 sequences of repeating producing components of length generated with cyclic shifts from ₁ and from ₂ , respectively, as well as symbol-by-symbol modulo 2 summation of these 2 sequences form the reference derivative sequence the resulting cyclic shift C which, at the control stage, eliminates the time mismatch of the received and reference derivative signals (RPS), and its value C is determined by the values of c ₁ and c ₂ in accordance with the expressions:

The decision to capture the PNP signal by delay is made upon the fact that the PVCF value of the received and received reference derivative PNP signal exceeds the set threshold, otherwise the search continues.

However, in this device:

- in general, a priori information about the structure of the PVKF of PNP is not taken into account and is not used, which leads, firstly, to the “blind” accumulation of the energy of the side peaks of the PVKF and thus to a significant number of “runs” (increase in the number p) and ultimately - to an increase in search and detection time, including due to a slow increase in the signal-to-noise ratio (S/N) at the output of the fast search device (FSD) for decision making, and secondly, the above information is not taken into account to speed up search, detection and synchronization;

- the first summation (accumulation) in the prototype parallel adder occurs only through cycles after the start of each stage of the run, i.e. information is lost that can be “removed” during these first beats;

- “accumulation” of maximum peaks of PVKF is carried out “blindly”: obviously “zero” (or very small) side bursts of the PVKF are added up (in all shift cycles, except one of clock cycles) with particular pronounced maxima of PVKF which leads either to a decrease in search reliability, or to an increase in search time due to a lower “final” (*) S/N ratio. Thus, to increase the final ratio in search channels, i.e. To increase the reliability of decision making, it is necessary to increase the number of runs of p. Moreover, to significantly increase this final ratio and the number p should increase not “by”, but “by” times. Consequently, the search and detection time for PSP increases significantly;

- selection of the maximum value of PVCF among the incoming side peaks of the PVCF (and comparison) in the digital comparator of the prototype occurs only at the final stage of the sweep (in the best case, the sweep of one entire PNP (L or pL, where p is the specified number of sweeps, i.e. p _min =1)) for cycles until the end of the run. Thus, a priori information about the structure of the PVCF is lost during the entire sweeping stage, which could be used to significantly speed up the search due to energy accumulation not periodically through clock cycles, but bar by bar, i.e. in each search cycle;

Also close to the claimed device is a device that implements a method for accelerated search of broadband signals according to the patent [5].

This device eliminates a number of shortcomings of the previous analogue and implements a number of additional actions that improve the quality of the process of entering into synchronism, namely:

- a priori information is used about the structure of the PVKF PNP and private PVKF _1,i , PVKF _2,j , formed in the “counter-inverse” correlation mode along all possible i, j subchannels of the 1st and 2nd channels for receiving the incoming PNP with producing components PC-1 and PC-2;

- parallel primary accumulation of values of PVKF _1,i , PVKF _2,j is carried out, and extrapolation (prediction) of the structure of private PVKFs is implemented at each receiving clock according to the pattern of extrapolation functions of 2 channels as functions of the sequence of numbers subchannels with private peaks at every clock moment;

- moreover, 2-factor extrapolation control and delay synchronization control are carried out without directly determining the current time delay of the received PNP.

However, this device does not use the capabilities of its main essential features for the implementation and implementation of the stage of effective and reliable optimal reception of SRS, manipulated by PNP based on the use of the determinism of the correlation functions of PNP and the principles of diversity reception theory (DRT) with a new the form of separation “in form” of the structure of the PVKF and the FKF of the PNP, which would allow, through the implementation of “Brennan’s law of addition” [9], to ensure high reliability and efficiency of the reception of SRS manipulated by the PNP.

The closest to the claimed device is a device that implements the method of the third decisive circuit for accelerated search and efficient reception of broadband signals according to the patent [6]. This device realizes exactly the potential features of the above-mentioned analogue device through the use of the principles and elements of the theory of the third decision circuit (TRC), set out in [8, 9], using when receiving within the framework of the TRC “in the analog final mode of single-channel reception and solutions" with diversity of channels K ₁ , K ₂ and their subchannels i and receiving “in the form” of structures, respectively, PC ₁ and PC ₂ (and their cyclic shifts), and their PVKF _1,i , PVKF _2,j with the adoption of the most plausible decision (“friend or foe” signal) SChS _result with the “discrete final method” two-channel." This jointly ensures a significant reduction in search time based on the CRS delay, and an increase in the reliability of receiving processing and decision making with a parallel implemented mode of “control and correction of synchronization” without stopping the process of receiving and processing the CRS. At the same time, high imitation resistance and structural secrecy of the SRS are ensured at all stages of receiving the SRS (search, synchronization, processing, decision making) due to both the use of the PNP itself and the corresponding implemented method of receiving and processing within the framework of the TRS.

However, this well-known “prototype device”, despite the fact that although it uses its distinctive features based on the TRS theory in the interests of increasing the efficiency and reliability of SRS and PNP reception, at the same time, functioning (within the TRS) in the “final mode of single-channel reception and decisions” ensures the adoption of two private single-channel decisions SChS _K-1 SChS _K-2 after running exactly the entire received PNP of period L based on the final levels at the outputs of “synchronous” subchannels:

accumulation of private peaks PVKF received by channels K ₁ and K ₂ PNP with the error probabilities of these decisions

where Ф [⋅] is the tabulated Crump function (or “probability integral”); γ is a coefficient that takes into account the level of orthogonality of the PSP (in our case - PNP) and is equal within C ₁ , C ₂ - delay values of cyclic shifts generating components PC ₁ , PC ₂ after entering into synchronism in the interests of making the final two-channel discrete decision "SChS" _result with the probability of error

As stated above, in the prototype device, as part of the implementation of the TRS of reception and decision making, the analog “final mode of single decision and reception” (“IRORP”) is used, the analytical and mathematical model of the effectiveness of which is described in [8, 9]. It is also shown there in [8, 9] that this mode “loses” in noise immunity to another analog mode of decision making and reception, namely the “final mode of two-channel decision and reception” (“IRDRP”). Indeed, in the IRDRP mode, the decision is made based on an assessment of the signal-to-interference ratio (“s/n”) being the sum

received after a “run” when taking all the APN taken. And how easy it is to establish, taking into account Crump’s analytical function, that since the excess over each of the terms on the right side of (4) is equal to approximately two times, this leads to a decrease in the probability of errors more than an order of magnitude compared to each of the probabilities on the right side of expression (5):

In addition, in the prototype solution And are accepted on the basis of the obtained values of the “s/p” ratios when adding the resulting ratios “s/p” in each branch (subchannel) throughout the entire period of the PNP “run”, i.e. -L _res . And since (taking into account the above) the relationship depend on duration generating PNP elements (simple NLRP), then in the prototype method to reduce the influence on these relationships, firstly, and to increase the reliability of reception, secondly, a discrete method is used - the “final two-channel discrete solution” SChS _IT0G with the probability (see formula (3)).

In this regard, it is important to assess the analytical dependence of the values (3) from various combinations of values those. evaluation of gain in reception reliability when implementing a discrete method of two-channel decision-reception in the prototype method, depending on the values In table 1 (Fig. 1) and in Fig. 2 these dependencies are presented in the table and graphic forms

Let us analyze these dependence data from the point of view of the gain in reliability of SCHSIT0G, i.e. V in the IRDRP mode compared to the IRDRP mode and the discrete method of 2-channel decision and reception, i.e. - with

1. If the prototype device had not used the “discrete method of the final 2-channel decision-reception” for fixing the SChS _TOTAL with the probability then the algorithm for making the final decision would be associated with using a decision on one of two channels k ₁ or k ₂ , and then the decision would be made with the probability where f _i is the function of the algorithm for selecting one of the channels (k ₁ or k ₂ ) for making the final decision. Values depend on duration generating elements (simple NLRP) [8, 9]. And noticeable differences in meanings will occur when there are noticeable differences in values and high levels of interference in the reception channels k ₁ and k ₂ . But according to [8, 9], significant differences between - are inappropriate from the point of view of ensuring the best ensemble, stealth, imitation-resistant characteristics and PNP parameters. Therefore, it can be objectively stated that in practice should differ by no more than (10-30)%, therefore the values of P _osh1 and P _osh2 will then differ by (10-30)%.

Taking into account that, as stated above: 1) R _osh1 ; P _osh2 in practice are approximately either equal or differ by (10-30)%; 2) the use of the IRDRP mode allows you to reduce (increase the reliability of decision making) by an order of magnitude; 3) keeping in mind the data in Table 1 and Fig. 1, we can conclude that the use of the IRDRP mode allows: to reduce the likelihood of error the final solution SCHSIT0G on average by an order of magnitude (this gain is especially visible at average values and in the general case, depending on the values this winning will be from 8 to 20 times.

In addition, from the point of view of the evidentiary reliability of the scientific and theoretical significance of the proposed device, another well-known analogue device should be analyzed [9]. In it, by ensuring a break in statistical and correlation connections between elements involved in decision making in the prototype device, through:

making preliminary private decisions in the IRORP mode in each branch for one run of cyclic shifts PC ₁ , PC ₂ with probabilities

savings for the period of receiving the entire PNP (for L _res ) and making, after running the entire PNP, channel preliminary decisions in each branch (i,j) KPR _1,i , KPR _2,j with probabilities

where k is the number of runs during the period L of cyclic shifts in subchannels with {PKPR _1,i , PKPR _2,j }=“no”, - averaged probability values

making channel decisions using the final single-channel method with probabilities

where μ is the number of runs over a period L s - average values the final decision “SChS _TOTAL ” is made with the probability

which is lower than the similar probability for the prototype device [6]. However, in this known analogue device [9], the gain in reception reliability, compared to the prototype device [6], is not unambiguous with the specifications of the area and boundaries of application of this analogue device [9], namely: it does not take into account analytical relationships and mutual influence on quantities parameter-values as part of Lpe3 and combinations Indeed: influence calculated using Crump functions (formulas (6)), accordingly to the values is “hyperbolic”, i.e. change for example, 2 times leads to a change approximately by an order of magnitude (10 times) (see Fig. 3); denoting for convenience of reasoning in expressions for combinations we point out that the influence of the magnitude of combinations on in expressions (7) is carried out both when the parameter k changes and when the fixed values n = const change (within the limits of changes in k) according to a law close to the normal law (see Fig. 3), which is known from the “combinatorics” section of mathematics [16 ], and: the influence of the parameter n in the value of the combination for fixed (k=const)≤n is expressed either in a decrease or in a rise in the top of the “bell” of the normal law (see Fig. 3), and the maximum will be only for k=n/2, for other combinations of k and n the values will decrease sharply. So when n changes by a factor of two will change by “m⋅10” times, m=1, 2,…, i.e. according to the “hyperbolic” law (see Fig. 4).

Based on the above, the following conclusions can be drawn:

1) influence of values in expressions (14) for and in expressions (15) for will be maximum (with the number of summed elements-commands) only at k=n/2, so this influence will decrease with a decrease in either the value of n, or the value of k<n/2, or with an increase in k>n/2;

2) parameters and (k)=(k ₁ ,k ₂ ) are determined by: the structure of the PNP and its duration number as part of PNP; specific values (i.e. types, types of simple NLRP);

3) thus dependencies in expressions (6, 7) from: L, k, μ, - are multi-parameter and non-linear, and therefore have areas and boundaries of the values of these parameters (and their mutual influences), which can lead to an increase in the reliability of reception, i.e. reduction those. therefore - to the feasibility of using the modes implemented in the analogue device [9] to increase the reliability of reception.

In this regard, the authors conducted relevant studies and computer modeling of multiparameter, multidimensional nonlinear dependencies which showed that an appropriate area of application for an analogue device [9] with the aim of increasing the reliability of taking PNP (i.e. reducing ) compared to the prototype device [6] is: values N _l1 , N _l2 as part of the duration L of the PNP should be the value while the values should not be only odd numbers and should differ from each other in value by no more than 15%; in all other cases of values as part of the PNP, the feasibility of the specified analogue device [7] essentially disappears (see Fig. 6).

As you can see, the area of feasibility, with the aim of increasing the reliability of reception, is to use an analogue device [9] compared to the use of a prototype device [6], although it is not limited in values L, but limited to: the area of relations l ₁ and l ₂ within range of values range of values This area limits the feasibility of using an analogue device [9], i.e. the application and implementation of the “single mode of single-channel decision and reception” and the “discrete method of final single-channel decision making” in an analogue device is very significant, because this scope excludes the use of a huge range of lengths to ensure increased reliability of APN intake.

In this regard, more universal for use, in the interests of increasing the reliability of reception in relation to the prototype device [6], extending to all ranges of values and their relationships, meanings , is, as research has shown, the “final mode of 2-channel decision and reception” described in [9]. The essence of this mode is that the “final decision” is made based on addition during the period of running the entire PNP with the probability of error

where γ is the orthogonality coefficient, equal within [10], Ф[.] - Crump function.

It is this mode that the proposed device is designed to implement. As stated above, the closest in terms of the set of characteristics to the claimed device is the prototype device according to the patent [6].

The actions of this prototype device with the claimed device are similar to the following set of actions:

As part of the search, discovery and synchronization phase:

- use of a priori information about the relationship between the value of the clock number of the current delay of the received signal and the clock of detection of the total values of cross-correlation between the received and reference sequences;

- search by delay of signals manipulated by derivative nonlinear sequences (DNS) is carried out in parallel through 2 channels, in one of which a sequentially repeating length component is used as a reference in a different -

- as a result of of the values of the periodic intercorrelation function (PVCF) accumulated in each of the 2 channels, the maximum is selected and the corresponding numbers of mutual shift cycles are recorded relative to the initial corresponding and then, based on the obtained i _max and j _max , the values of the cyclic shifts from ₁ and ₂ generating components are determined according to the following relationships:

then, through the parallel formation of 2 sequences of repeating producing components of length generated with cyclic shifts from ₁ and c ₂ , respectively, as well as symbol-by-symbol modulo 2 summation of these 2 sequences form the reference derivative sequence the resulting cyclic shift C which, at the control stage, eliminates the time mismatch between the received and reference derivative signals (RPS), and its value C is determined by the values of c ₁ and c ₂ in accordance with the expressions:

- the decision to capture the PNP signal by delay is made upon the fact that the PVCF value of the received and received reference derivative PNP signal exceeds the set threshold, otherwise the search continues;

- moreover, a priori information is used about the structure of the PVKF PNP of duration L=l ₁ ×l ₂ the structure of private PVKF _1i , PVKF _2j formed through parallel, simultaneous, in “back-to-back” correlation mode across all possible i, j subchannels respectively, the first (1) and second (2) - channels for receiving incoming PNP with various automorphisms (cyclic shifts) of segments (producing components (PC-1 and PC-2) in the form of simple nonlinear recurrent sequences (NLRP) of duration l ₁ and l ₂ - PC _1i and PC _2j , i=1,…, l ₁ , j=l,…, l ₂ ;

- simultaneous parallel primary accumulation of values of private PVKF _1i , PVKF _2j is carried out in subchannels i and j of the search of the 1st and 2nd channels in each correlation cycle during the analysis time T _an1 =p ₁ l ₁ , T _an2 =p ₂ l2 , where p ₁ and p ₂ are the number of runs producing components PC-1, PC-2, p _1min =p _2min =L and the summation of the accumulated values in each channel at the end of the primary accumulation substage, to implement the extrapolation substage;

- moreover, extrapolation (prediction) of the structure of private PVKF, PVKF in the form of extrapolation into each k _1st , k _2nd clock moments (after the substage of primary accumulation) of private peaks R _chp1 , R _chp2 in the 1st and 2nd channels, respectively at the outputs of certain extrapolated search subchannels with extrapolated numbers set according to the extrapolation functions SE ₁ , SE ₂ subchannels of the 1st and 2nd processing channels:

- as functions of the sequence of subchannel numbers and with private peaks R _chp1 , R _chp2 at their outputs in every k _1st , k _2nd clock cycle:

Moreover, 2-factor control of extrapolation is implemented on the majority principle: by the factor of extrapolated subchannel numbers and with partial peaks R _chp1 , R _chp2 and by the factor of accumulation levels

- and accumulation is carried out at the outputs of 2 channels of identified extrapolated private peaks at the extrapolated outputs ix and jx of the search subchannels of the 1st and 2nd processing channels, respectively, at each k-th (k ₁ =k(mod l ₁ ) and k2=k(mod l ₂ )) reception clock;

moreover, control of the establishment of synchronization by delay is implemented by generating a reference signal of the PNP without directly determining the current time delay of the received PNP, but by such a combination of numbers of synchronization cycles with the generating lines, in which i _max and j _max are, in essence, extrapolated numbers of subchannels i _max =N _k1 , γ _max =N _k2 respectively with partial peaks at their outputs and after positive 2-factor extrapolation control;

- within the framework of the reception and decision-making stage:

- since the stage of receiving-processing and decision-making “friend or foe” signal (FSS) is carried out after entering into synchronism, i.e. coherent, hence the accumulation at each clock moment (i, j) of private peaks as the ratio (s/w) _OUT in each clock cycle (I, j) at the output of the receivers of channels K ₁ and K ₂ And in each subchannels i and j is carried out coherently (synchronously) and optimally, which is reflected by symbols ₁ and ₂ for in conditions of uncorrelated reception in two channels K ₁ and K ₂ and their subchannels due to the use of generating components PC ₁ and PC ₂ that are different in shape;

- separately in each channel K ₁ and K ₂ according to Brennan’s addition law with spacing of channels K ₁ and K ₂ and their subchannels i and reception “in shape” of structures PC ₁ and PC ₂ , respectively, and their cyclic shifts during the reception time (period L) of the entire PNP, the final (resulting) levels of accumulation of private peaks at the outputs of synchronous (c ₁ and c ₂ ) subchannels are obtained in channels K ₁ and K ₂ , respectively

Where - partial peaks of PVKF (s/w) _out ) at the outputs of channels K ₁ and K ₂ , respectively, at clock moments i and j, respectively, runs in synchronous subchannels c ₁ and c ₂ - cyclic shifts in synchronous subchannels after entering into synchronism; -averaged values; n and m are the number of runs in subchannels, respectively

- in the process of coherent reception and processing, control and correction of synchronization is ensured due to the fact that accumulation and in other subchannels as well as in synchronous subchannels with shifts from ₁ and ₂ channels K ₁ and K ₂ , respectively, but the results of these accumulations are the final accumulation levels respectively in ix subchannels of channel K ₁ , and in jx subchannels of channel K ₂ , for the entire period of admission (period L), the PNP will be respectively equal to:

Where - averaged values, - which are used for

synchronization control, namely: after receiving the entire PNP in each channel K ₁ , K ₂ , the final levels of accumulation in each of the subchannels are compared with the final accumulation levels in synchronous subchannels, respectively and for any i and j the condition will always be satisfied with correct, imitative, stable synchronization, respectively and if it is determined that for some (or some) subchannel (subchannels) this condition is not met, i.e. it turns out that then for such (such) subchannel (subchannels) this fact is recorded as a “desync signal” (DSS) equal to 1, i.e.

- if in the process of “reception-processing” of the PNP for any of the subchannels i* and j* in K ₁ and K _2, the sum of CPC during the control time T _CONTR turns out to be greater than or equal to, respectively and/or those.

then a decision is made to conduct a “control analysis”, when for such subchannels i* and j* their cyclic shifts are checked for compliance with relation (2), and if this relation is satisfied, then the “compliance signal” CC=1 (CC _1i =1 and CC _2j =1) is fixed; moreover, if in the process of receiving PNP for the selected majority number (MF) of periods T _CONTROL : MC = (5, 7, 9, ...) (odd number), - such correspondence signals from any subchannels will accordingly receive the number N _cc ≥( 3, 5, 7...), then a decision will be made to change the cyclic shifts of PC ₁ and (or) PC ₂ in channels K ₁ and K ₂ , i.e. to replace the used synchronous subchannels with subchannels with cyclic shifts accordingly, to exit the “control analysis” mode. Thus, an adaptive correction of clock synchronization will be carried out to the corresponding numbers cycles without stopping “reception-processing”. Otherwise, no timing correction is made;

- if in the process of “reception-processing” of the PNP during the time TK0Ntr it turns out that for and more than the number of subchannels in each of the channels K ₁ and K ₂ , if expression (15) is valid, then this will indicate a failure of synchronization due to interference, and then a decision is made to stop “receiving and processing” information and moving to the search stage and synchronization

To implement these similar actions, the claimed device has the following similar features with the prototype device, namely, a third decisive circuit device for accelerated search and effective reception of broadband signals, containing: two correlative-type processing channels identical in composition, and the correlation processing is implemented on the basis of acousto-electronic convolvers (AEC), the received signal is supplied to one input of each channel; Moreover, each processing channel contains a reference sequence generator, the first output of this generator of each channel is connected to the corresponding input of the derivative signal generator, the output of which is connected to one of the inputs of the delay synchronism control circuit, the other input of which is the input of the received signal, and the input of the reference sequence generator each channel is connected to the output of the corresponding shift calculator c ₁ and c ₂ , and in each processing channel the reference sequence generator is made in the form of a generator of all possible automorphisms (cyclic shifts) issued in parallel across a group of second outputs, respectively, and output from the first output of one of the automorphisms of the support sequence of the generating repeating component of length respectively; block of digital subcorrelators (DSPC), which contains, respectively, for each channel subcorrelators, each of which contains: a series-connected acoustoelectronic convolver (AEC), one input of which is the first input of the subcorrelator and is connected to the first input of the processing channel, and the second input is the second input of the subcorrelator and is connected to one of the second outputs of the reference sequence generator; an amplifier and an analog-to-digital converter (ADC), the output of which is a parallel output bus and is the output of the subcorrelator and the corresponding output of the BTsK, the outputs of which is a parallel output bus, are connected to the corresponding inputs of the accumulation and extrapolation circuit (SNE), which contains, respectively, for one and the other processing channels for l ₁ and l ₂ search subchannels, the inputs of which are the corresponding inputs of the SNE, and the outputs are connected to the corresponding first inputs of the central digital comparator (DCC), the first input of which is connected to the output of the first key, and l ₁ and l ₂ outputs (for one and the other channel, respectively) are connected, respectively, to the inputs of the digital adder and to the first key inputs of the key block (KB), containing, respectively, l ₁ and l ₂ keys, the second inputs of which are connected to the output of the first key, and the outputs of the keys BC are connected to the corresponding inputs of the shift calculator c ₁ and c ₂ , respectively, the output of which is the output of the SNE and the processing channel and is connected to the input of the corresponding reference sequence generator, and the output of the digital adder is connected to one input of the first key, the other input of which is connected to the output of the accumulator-adder, input which is connected to the output of the check block, which is a block (set) of two-input AND elements, the first the inputs of which are connected to the corresponding outputs of the central circulation center and the inputs of the subchannel number selection block (BVNP), which is a cross-block and a clock delay block connected in series, whose outputs are connected to the second check block inputs; Moreover, each search subchannel of the accumulation and extrapolation circuit (SNE) contains a digital parallel adder, the first inputs of which are connected to the corresponding parallel output bus of the BPCP, and the second inputs are connected, respectively, to the outputs of the corresponding matching elements, the first inputs of which are clock, the second inputs are connected, respectively, to the outputs of a random access memory (RAM), the inputs of which are connected to the outputs of a digital parallel adder and the corresponding first inputs of the second switch, the second input of which is connected to the output of the first counter, the input of which is a clock one, and the input of the second counter, the output of which is connected to one input of the circuit. And, the output of which is connected to the output of the control panel, and the second input is connected to the output of the digital comparator, the inputs of which are connected to the outputs of the second key; and the device also contains: the first and second channels for receiving and making decisions as receiving parts of the first and second processing channels and containing the first and second blocks, respectively parallel adders (BPS-1 and BPS-2), parallel buses respectively, the inputs of which are connected respectively to tires on parallel outputs, respectively, of the first and second blocks of digital subcorrelators (BTsPK-1, BTsPK-2), and buses from (1st to ) and from (1st to ) accordingly parallel outputs of BPS-1 BPS-2 are respectively connected to the first and second groups by according to tires inputs, respectively, of the first and second blocks of digital comparators (BTsK-1, BTSK-2) and the corresponding ones (1st to ) and from (1st to ) tires on respectively parallel inputs of the first and second nodes from (1st to ) and from (1st to ) respectively valves (UV-1, UV-2), the control input of each of which is connected respectively to (1st to ) and from (1st to ) outputs, respectively, of the first and second blocks of keys of accumulation and extrapolation circuits (SNE) of the first and second processing channels, respectively, and the corresponding ones from (1st to ) and from (1st to ) tires by respectively parallel outputs corresponding to (1st to ) and from (1st to ) respectively, the first and second UV-1 and UV-2 are connected, respectively, to the third and fourth group by according to tires inputs BTSK-1 and BTSK-2, respectively, and outputs from (1 to ) and from (1 to ) which are respectively connected to (1 to ) and from (1 to ) inputs, respectively, of the third and fourth BCC-3 and BCC-4, outputs, respectively, from (1 to ) and from (1 to ) which are connected respectively from (1 to ) and from (1 to ) inputs respectively of the first and second comparator-analyzer (KA-1 and KA-2) and from (1 to ) and from (1 to ) inputs, respectively, of the first and second blocks of majority comparators (BMK-1 and BMK-2), outputs, respectively (1st to ) and from (1st to ) which are connected respectively from (1st to ) and from (1st to ) inputs, respectively, of the first and second corrective delay calculators (KVZ-1 and KVZ-2), respectively, with ₁ and c ₂ , the outputs of which are connected, respectively, to the input of the first and second reference sequence generators GOP-1, GOP-2, and the output of the first and the output the second KA-1 and KA-2 are connected, respectively, to the input of the first and the input of the second threshold device (PU-1 and PU-2), the outputs of which are connected, respectively, to the first and second inputs of the receiving coincidence circuit (RCC), the output of which is blocking the reception of PNP output and connected to the blocking inputs of the first and second blocks of parallel adders BPS-1 and BPS-2, respectively, and the third input of the PSS is a release input and connected to the release output of the synchronization control circuit (SCS), the second inputs GOP-1 and GOP-2 connected respectively to the outputs of the first and second corrective delay computers KVZ-1 and KVZ-2.

The technical result to which the invention is aimed is that the claimed device of the third decisive circuit for accelerated search and efficient reception of broadband signals solves the problems of fast search and synchronization of signals manipulated by PNP, efficient reception and processing (and making a “friend or foe” decision ) an elementary message signal, represented by the PNP code form to expand the SRS spectrum, but with greater efficiency (in terms of reliability) than the prototype device, namely:

1) reducing the likelihood of error (increasing the reliability) of the final decision on average by an order of magnitude;

2) expansion of the scope of increasing the reliability of reception to all areas of duration values elements generating PNP - NLRP and their relationships.

The basis of the proposed device is, along with the use of the properties of the fine internal structure of the PNP, its producing components, simple NLRP, the determinism of the structure of the PVKF NLRP, elements of the theory of the third decisive scheme of reception-processing and decision-making, and also the implementation of the final mode of dual-channel decision and reception (IDRP).

This makes it possible to achieve a set of characteristics that determine the best technical result of the following set of properties compared to the prototype device:

1. The code structure of the PNP determined by the construction rule, the deterministic structure of both the PVCF and the frequent CF (FCF) of the PNP, the use based on their application of two-channel (K ₁ , K ₂ ) and ( )-subchannel (according to branches in K ₁ , K ₂ channels) diversity “in form” of the reception-processing and decision-making procedure makes it possible to implement in the claimed device of the “third decision circuit” an accelerated search and effective reliable reception of broadband signals known in the theory of the third decision circuit “the final mode of a two-channel decision and reception", thereby ensuring an increase in the reliability of reception-processing and decision-making on average by an order of magnitude, together with a significant reduction in search time based on the SRS delay and an expansion of the scope of increasing the reliability of reception to all areas of duration values elements generating PNP - NLRP and their relationships.

2. Ensuring high imitability and structural secrecy of the SRS at all stages of receiving the SRS (search, synchronization, processing, decision making) through both the direct use of PNP, which has a high level of imitation resistance and structural secrecy, and the corresponding above-mentioned mode and method of receiving and processing within the framework of the “third decisive scheme”;

3. Since the implementation of the device does not require a preliminary selection of the internal structure of the PSP in the form of a PNP due to the fact that the producing components PC-1, PC-2 in the form of simple NLRP are used as supporting segments of the PNP, and thus the internal structure of the PSP “quasi-uncontrollably” changes with each processing step in real time, and the reception-processing procedure is carried out, while by means of dividing “in form” the PVKF and the CPVKF in the “final mode of a two-channel decision and reception”, thereby ensuring [9] additionally high imitability of the reception-processing stage and decision making.

4. The inventive device can be built using both traditional elements and elements of acousto-electronic technology that meet stringent requirements for energy intensity, time and weight-size parameters [11].

The achievement of the specified technical result is based on the implementation of the following distinctive actions by the claimed device:

- after taking the entire PNP, the accumulated values are summed up getting the value:

- given value are used in the final mode of 2-channel decision and reception (IRDRP) to make the final most plausible decision “friend or foe” signal (SChS _ITOG ) using the “maximum likelihood” criterion with the probability of error

The implementation of the proposed device is based on:

1) common to the claimed device and the prototype device: features of the PNP code structure, determined by their formation rule; features and properties of determinism of PVKF PNP as a function of time; general features and properties of the “third decision circuit” (TRC) method for receiving-processing and decision-making, ensuring increased reliability of receiving-processing and decision-making, set out in detail in [6, 7, 8, 9] and illustrated in Fig. 1-12;

2) distinctive features and properties of the “final mode of 2-channel decision and reception” (IRDRP) used in the claimed device, theoretically presented and analyzed in [8, 9], which allows: to increase the reliability of the final solution of the SES _TOTAL on average by an order of magnitude and expand the areas of increasing reception reliability to all areas of duration values elements generating PNP - simple NLRP and value relationships

To implement the proposed device, the following distinctive features have been introduced into a known prototype device [6] with similar above-mentioned features:

corresponding from (1st to ) and from (1st to ) tires by respectively parallel outputs corresponding to (1st to ) and from (1st to ) respectively the first and second UV-1 and UV-2 are connected respectively to (1st to ) and from (1st to ) tires on parallel, respectively, first and second inputs of the final adder (IS), the output of which is connected to the input of the deciding device (DR), the first and second outputs of which are the decisive outputs (“Yes” and “No”) of the device as a whole.

The diagram of the proposed device is shown in figure 16a, b, c.

The search, detection and synchronization process is implemented by the device in two stages: the search and detection stage, consisting of two substages - the primary accumulation substage and the extrapolation substage; synchronization stage.

This process is carried out by two simultaneously operating processing channels identical in structure for the first and second producing components (PC-1, PC-2), as well as a delay synchronization control circuit 3 and a derivative signal generator 4 (GPS) common to these channels. Each processing channel contains, respectively: a block of digital subcorrelators (DSPC) 16 (DSPC ₁ ) and 1 (DSPC ₂ ); reference sequence generator (RPG) 5 (RPG ₁ ) and 2 (RPG ₂ ); accumulation and extrapolation scheme (SNE) 17 (SNE ₁ ) and 18 (SNE ₂ ). Each BTsPK (BTsPK ₁ , BTsPK ₂ ) contains subcorrelators (PCR) 6 (for the 1st channel of subcorrelators for channel 2 - Moreover, each subcorrelator contains an acoustoelectronic convolver (AEC) 6-1, an amplifier (AC) 6-2, an analog-to-digital converter (ADC) 6-3. Each SNE (SNE ₁ , SNE ₂ ) contains: search subchannels (SNE) 7 (for the 1st channel of search subchannels for channel 2 - central digital comparator (CDC) 8; key 9; subchannel number selection block (BVNP) 10, containing a cross block 10-1 and a block of delay lines (BLZ) 10-2; accumulator-adder (NS) 11; key block (BC) 12, containing keys for the 1st and 2nd channels, respectively; verification device (UT) 13; digital adder (DA) 14; delay calculator 15 from ₁ and _2, respectively, for the 1st and 2nd channels. Each search subchannel (SSC) contains: a parallel adder (SA) 19, a random access memory (RAM) (consisting of memory elements 21), each line of which has a number of elements 21 that allows you to digitally store the maximum level value of the PVKF, and each column contains N memory elements, and for the 1st channel and for the 2nd channel counter 20; key 22; digital comparator (DC) 23; scheme “I” 24; counter 25; matching patterns 26.

The result of the work of each processing channel at the end of these two stages is the determination of the values c ₁ and c ₂ of the cyclic shifts of the producing components PC-1 and PC-2, i.e. determination of those automorphisms (cyclic shifts) for GOP-1 (5) and GOP-2 (2), respectively, which will have to be issued at their first outputs in GPS (4) at the synchronization control stage to ensure that generator 4 generates a reference derivative signal with the resulting central shift C, eliminating delay mismatch.

The process of effective coherent reception of PNP and decision making is implemented by the receiving parts (54 and 55) of the first and second processing channels PC-1 and PC-2 as the first and second channels of reception and decision making, the structure and composition of which are almost identical and are presented in Fig. 16. c: (27…29) and (30…32) - respectively the first and second blocks of parallel adders (BPS-1 and BPS-2); (33…35) and (36…38) - respectively the first and second valve assemblies (UV-1 and UV-2); 39 - final adder (IS); 40 - decisive device (RU); 41 and 42 - respectively, the first and second blocks of digital comparators (BTsK-1 and BTSK-2); 43 and 44 - respectively the third and fourth blocks of digital comparators (BTsK-3 and BTSK-4); 45 and 46 - respectively, the first and second blocks of majority comparators (BMK-1 and BMK-2); 47 and 48 - respectively, the first and second corrective delay calculator KVZ-1 KVZ-2 respectively with ₁ and with ₂ , 49 and 50 - respectively the first and second comparator-analyzers (KA-1 and KA-2); 51 and 52 - first and second threshold devices (PU-1 and PU-2), respectively; 53 - receiving coincidence circuit (RCC).

The result of the operation of the first and second channels of reception and decision making as receiving parts (54 and 55) of PC-1 and PC-2, respectively, is the issuance of signals from the outputs of the switchgear (40) either “Yes” (“there is” its own PNP) or “No” (“no” to your PNP). Moreover, during the reception process: blocks (41, 43, 45, 47) and (42, 44, 46, 48) carry out a parallel synchronization “correction” mode, respectively, along the first and second processing channels (PC-1 and PC-2) with the output “adjusted” delay values accordingly respectively, from the outputs of KVZ-1 and KVZ-2 (47 and 48), respectively, to the first and second generators of GOP, (5) and GOP2 (2); and blocks (41, 43, 49, 51) and (42, 44, 50, 52) with block 53 carry out a synchronization check (control) mode (in conditions of a significant level of interference) with the output of block 53 receiving a “blocking” signal ( in case of synchronization failure) and the beginning of the repeated stage of entering into synchronism.

The process of effective coherent reception of SRS in the form of PNP and decision making with a parallel mode of control and synchronization correction is implemented within the scope of the TRS method using the final mode of two-channel reception and decision. This process is implemented by simultaneously operating, identical in structure and composition, two reception and decision-making channels, which are the receiving parts of two corresponding processing channels, and interact with certain of their elements. Each channel for receiving and making a decision receives, respectively, from BTsPK-1 (16) and BTsPK-2 (1) in digital form according to their respective input buses by inputs in each of the corresponding ADCs (6-3) values to their respective parallel adders of the first and second blocks BPS-1 and BPS-2 (27...29 and 30...32), respectively. Next: a set of blocks of the first and second nodes of the valves UV-1 and UV-2, respectively (33...35 and 36...38), receiving control (opening) output pulses, respectively, from the BC (12) - SNE circuits] (17) - and similar SNE2 block 18; final adder (IS) (39); decision-making device (RU) (40), - provide effective reception and decision-making: there is (“Yes”) or (“No”) its signal, - according to its corresponding outputs “Yes” and “No”. In parallel with reception using blocks: the first and second blocks of digital comparators (BTsK-1 and BTSK-2) (41 and 42); third and fourth blocks of digital comparators (BTsK-3 and BTSK-4) (43 and 44); the first and second blocks of majority comparators (BMK-1 and BMK-2) (45 and 46); first and second corrective delay calculator (KV3-1 and KV3-2) (47 and 48), respectively synchronization correction is carried out with the issuance of correction values respectively in GOP-1 (5) and GOP-2 (2). Also in parallel with the reception and using blocks: the first and second KA-1 and KA-2 (49 and 50); first and second threshold devices PU-1 and PU-2 (51 and 52); receiving MSS matching circuit (53), - synchronization is checked (monitored) under conditions of a significant level of interference on two reception channels with the issuance of a decision signal to resume the search, detection and synchronization stage at the output from the MSS.

We will describe the operation of the device taking into account the above-mentioned similar and distinctive actions and features, as well as taking into account the fact that the operation of each channel is essentially the same.

1 Search and discovery stage.

1.1 Substage of primary accumulation.

In each channel, one input of the AEC 6-1 of each subcorrelator 6 receives the received signal _S in the form (repeating in time in the general case) SRS, manipulated by PNP (SRS-PNP), and the other inputs of the corresponding AEC 6-1 receive in counter -inverse mode from the second corresponding (ix and jx) outputs of generators 2 and 5 reference signals representing signals manipulated by generating lines (repeated cyclically) ix and jx of automorphisms of generating components PC-1 and PC-2, respectively. With each clock cycle, from each i-th and j-th AEC 6-1 of the 1st and 2nd channels, a voltage proportional to the energy of convolutions of segments of length is removed, respectively reference lines moving towards each other The AEC output signals are amplified by amplifiers 6-2 and converted to an ADC 6-3 with a sampling frequency equal to the PSP frequency, so that from the outputs of the ADC 6-3 we obtain the digitized values of private PVKF-1 _i , and PVKF-2 _j . The first values of these private PVKFs (cycles k ₁ =k ₂ =l) through parallel adders (PS) 19 without changes (since at this moment nothing has yet arrived from the outputs of RAM 21 to the other inputs of the PS) are written in parallel to the first bits (elements memory 21) registers of RAM 21. The total number of registers (the number of memory elements in a line) of RAM must correspond to the number of bits of the maximum possible accumulated value of PVKF. The number of bits N in the registers is equal to the number of shifts for which private PVCFs will be accumulated, i.e. for 1st channel and for channel 2

For the first cycles, respectively, for the 1st and 2nd channels, the AEC subcorrelators are initially filled with their automorphisms PC-1 and PC-2 from the corresponding second outputs of generators 5 and 2, respectively. And starting from clock cycles And respectively, for the 1st and 2nd channels, the substage of primary accumulation is carried out. With each cycle (k ₁ , k ₂ ), the register cells of RAM 21 through PS 19 are filled in parallel with new digital values of the PVKF so that after beats and cycles in the 1st and 2nd channels, respectively, cells 1…N of RAM 21 of all search subchannels of control panel _i , control panel _j will be filled respectively, the values of the automorphic partial PVKF-1 _i , PVKF-2 _j . In the next clock cycle (k _1st , k _2nd ), the values of the automorphic partial PVCFs obtained from the outputs of the BCPC 16 are summed up in the PS 19 with the values of these PVCFs located in the last N-th line of RAM memory cells, due to the elements 26 opening with a clock pulse _{. _}

Thus, in the first line of RAM 21 of each control panel 7 the first maximum R _chp1 and (and R _chp2 ) may appear through initial measures, i.e. in the moment and only after another cycles, the possible primary maximum will be added to the second (in a row) similar maximum through elements 26 in PS 19. Counter 20 overflows in clock cycles until the end of the analysis time respectively in the 1st and 2nd channels. Key 22 opens for clock cycles until the end of the analysis time according to the overflow signal from the counter 20 and passes to the input of the digital channel CC 23 in each i-th (and j-th) control panel 7 the first value of the accumulated private subchannel sum respectively Based on the same overflow signal from counter 20, counter 25 of the number of subsequent beats

This is the first value in the Central Committee 23 is remembered as a reference one, with which the next second, accumulated partial “subchannel” sum is compared in the next clock cycle The first and second values of these amounts are compared in the Central Committee 23 and the larger of these values is selected as a reference. So, in subsequent cycles, each CC 23 selects the largest private subchannel sum accumulated in the i-th PCP 7 behind clock cycles in the 1st channel and the amount in the j-th PCP 7 in the 2nd channel. This selection ends when counter 25 overflows in beats The overflow signal of the counter 25 opens the coincidence circuit 24, which passes from the output of the i-th (and j-th) CC 23 in a parallel code to the output of the control panel 7 the last (maximum) reference value, to the corresponding first parallel i-th input of the central digital comparator 8. Thus, from all central control centers 23 of all control panels 7, partial sums are received at the outputs of the central digital comparator central digital comparator 8 at the corresponding end of the analysis time _Tan1 CCC 8 carries out: 1) summation of the values accumulated for T _an1 and T _an2 in each subchannel of control panel 7 of both channels of private “subchannel” sums and if this is the value then 2) CCC 8 chooses “maximum maximorum” - extremum from certain control panels 7 of both channels and produces, according to the corresponding number of this control panel 7, its output to the corresponding input of the BVNP 10, a signal that reflects the number N _k1 (and N _k2 ) of the control panel 7, in which the extremum E ₁ (and E ₂ ) is recorded. If S ₁ <S _n1 (and S ₂ <S _n2 ), then the process of primary accumulation continues at a different number p ₁ (and p ₂ ) until this condition is met. This ends the substage of primary accumulation. This substage, while maintaining a given level of signal-to-noise ratio for decision making, as for the prototype, will be reduced in time by times (for 1st channel) and times (for channel 2).

1.2 Extrapolation sub-stage. BVNP 10 based on the received number N _k (N _k1 - for the 1st channel N _k2 - for the 2nd channel) PKP 7 in the form of a signal at its specific input (N _k ) transmits this signal with a delay of one clock cycle in the delay block 10-2 via a cross-connect (cross-block 10-1) that implements the corresponding dependencies And to such its output N _k+1 , which corresponds to the number N _k+1 /PKP, in which the next (close to the extremum in value) maximum of the partial peak of the PVKF should be observed in the next (k+1) cycle

The number N _k+1 calculated in this way in BVNP 10, i.e. the predicted (extrapolated) number N _k+1 in the form of a signal from one of the outputs of the BVNP 10, corresponding to N _k+1 , is received at one of the first inputs of the UP checker 13 and stored until the next cycle k+1. At the moment of the k-th, (k+1)-th and other cycles after them, from the corresponding N _k , N _k+1 and other outputs of the central circulation center 8, a parallel code is sent to the central control center 14, carrying information in digital code about the energy of partial maximum bursts side peaks of PVKF at the outputs of N _k , N _k+1 -m and other PCP 7. These energy values are summed up and stored for subsequent accumulation with other bursts in subsequent cycles. At the same (k+1)-th clock moment, from the corresponding N _k+1 -th output of the central control center 8, a signal about the selected N _k+1 /th PCP with the maximum peak PVKF is received to one of the second inputs of the UP 13. UP 13 compares control panel numbers corresponding to number N _k+1 , received through one of the first inputs and one of the second inputs of UP 13. If these numbers match, then from the output of UP 13 to the input of the accumulator-adder NS 11 the symbol “1” is received, and if the numbers do not match, then the symbol “0”. NS 11 arithmetically accumulates the symbols “1” and “0”, sums them up (as potential signals) during a certain h=l ₁ number of cycles, and if this sum exceeds a given threshold P _h for this number of cycles (according to the underlying majority principle: or etc., i.e. M is the majority coefficient), then from the output of NS 11 the signal “our ₁ ” is sent to the first input of key 9. During the same number of clock cycles CS 14 accumulates the energy of the amplitudes of bursts of partial maximum side peaks PVKF from each PKP 7 in which this maximum was detected. And if the amount , the specified threshold (TP) in the CC 14 will be exceeded after h-cycles then the “our ₂ ” signal is received from the output of the CS 14 to the 2nd input of the key 9. Key 9 is unlocked when the signals “our ₁ ” ₁ and “our ₁ ” ₂ are received at both its inputs from the outputs of the UP and CS, respectively. Thus, the signal “ours!” is received from the output of key 9. (in the second channel - the signal “our ₂ ”) (signal “about the correctness of the prediction”) to the 2nd input of the central control circuit 8 for its locking in the next clock cycle, and then to the first inputs of the keys 12.

2. Synchronization stage. Under the influence of the signal “our ₁ ” and “our ₂ ”, the keys 12 go into the open state. And through a certain switch 12, the second input of which receives at this time a signal from a certain output of the central control center 8, a signal passes to a certain input of the computer from ₁ to 15, corresponding to N _k with a maximum those. value N _k per clock which will determine the value of the cyclic shift from ₁ for PC-1 relative to the received PNLRP, since number N _k of the subchannel in which at this moment there will be a maximum side burst and determines i _max =N _k1 (for the 1st channel) and j _max =N _k2 (for the 2nd channel), the value of which is used in the calculation of _{c 1} and c ₂ , according to relation (1), producing the component PC-1 , PC-2 and thereby establishing the required total clock shift C according to relation (2). And CCC 8, as mentioned above, is locked at the moment and stops issuing the selected numbers N _k . Next, the resulting value from ₁ is sent to generator 5 GOP-1, which produces, at its first output to GPS 4, the automorphism of the generating component PC-1, corresponding to the shift from ₁ . In a similar way, the process of search, detection and synchronization occurs in the search channel along PC-2, only instead of c _1, c ₂ is calculated, which is supplied to generator 2 of GOP-2 to form PC-2 with a cyclic shift from ₂ . The symbols of the generated PC-1 and PC-2 (automorphisms PC-1 and PC-2, corresponding to numbers c ₁ and c ₂ cyclic shifts) are summed modulo 2 in GPS-4 and thereby provide a reference PNLRP with the resulting shift C, eliminating mismatch in delay between the received and reference signals when checking the fact of synchronism in control circuit 3. This ends the synchronization phase.

3. Stage (process) of effective coherent reception of SRS in the form of PNP and decision making.

This stage begins after entering into synchronism, which is fixed by the appearance of a control pulse at the output of one of the keys 12 _i BC (12), which goes to one of the UV-1 valves (33...35) and similarly to one of the UV-2 valves (36... 38) and essentially starts the acceptance process. Digital values arriving via the output buses of BTsPK ₁ (16) and BTsPK ₂ (1) at each reception cycle to the corresponding input buses of the first (27...29) and second (30...32) BPS-1 and BPS-2, accumulate in the process of receiving PNP (“n” PC runs), and “m” PC runs _2j ) on each corresponding of parallel adders PS _1i and PS _2j (27...29 and 30...32) with obtaining, during the period of the PNP run, on the output buses of PS _1i and PS _2j , values The valve units UV-1 and UV-2 (blocks 33…35 and 36…38) solve the problem of passing beyond these values only to those input buses, respectively, of the first and second inputs of the IC (39), which correspond to the value i=c ₁ and j= with ₂ , i.e. synchronous subcorrelators (SSC) 6-i and 6-j. Values received at the corresponding (with ₁ =i)th and (with ₂ =j)th first and second inputs of the IC (39) is summed in IS (39) to obtain the value which enters the RU (40) to make a decision “Yes” or “No” with probability P _osh based on the “maximum likelihood” criterion. Thus, the final (during the period L of the run of the received PNP) mode of two-channel reception and solution using the TRS method, including that described in [9], is implemented. This actually ends the stage of taking one ANP and begins taking the next ANP through the specified method of taking TRS.

In the process of receiving PNP, correction and synchronization control modes are used in parallel, taking into account the corresponding interference levels.

The parallel synchronization correction mode is implemented in parallel with the process of coherent reception of PNP using blocks 41...58 - in the first and second channels of reception and decision making. Since getting the values is carried out continuously with a period T _prog =L _res at the outputs of all PS _i and PS _j , then these values (except for the values at the outputs which is ensured by the operation of the HC (33...35 and 36...38)), are used respectively by the first and second BCC (41 and 42) to compare the accumulated values arriving at the corresponding inputs of the first input buses BTSK-1 (41) and BTSK-2 (42) from the corresponding UV-th (33...35 and 36...38) with the values And arriving through one of the corresponding inputs of the second input buses BCC-1 (41) and BCC-2 (42). And if in one of the i*-x and j*-x digital comparators, respectively, BCC-1 (41) and BCC-2 (42) it turns out (as a result of comparison) that then at the output of such i*-th and j*-th digital comparators (DC) BCC-1 (41) and BCC-2 (42) the signal “there is a mismatch signal” will appear Signals arriving behind T _control from the outputs of BTsK-1 (41) and BTsK-2 (42) are accumulated in each CC, respectively, of the third and fourth BCC-3 (43) and BCC-4 (44), and if during the time T _counter in any CC the accumulated value becomes (for BCC-3) and (for BCC-4), then at the output of their corresponding CC, i.e. at the corresponding output of BCC-3 (43) and BCC-4 (44), an excess signal (SP) equal to “SP” = “Yes” = 1 will appear. These signals SP _1,i and SP _2j , arriving at the corresponding outputs of BCC-3 (43) and BCC-4 (44) to the corresponding inputs of the first and second BMK-1 (45) and BMK-2 (46) are accumulated in the corresponding MCs , which, for a given majority number of MF={5,7,9,...} periods T _counter, select those (i*,j*)-th reception subchannels for which, during the MF period, the corresponding number N _{of SPs} of such SPs has accumulated: The fact of selection of such subchannels is fixed by the signal “Yes” = 1 at the corresponding output of BMK-1 (45) and BMK-2 (46) and the corresponding input of the first and second KVZ-1 (47) and KVZ-2 (48), respectively, delays C ₁ * and C ₂ *. The calculated delays C ₁ * and C ₂ * are respectively supplied to GOP-1 (5) and GOP-2 (2) from the outputs of KVZ-1 and KVZ-2 (47 and 48) to change automorphisms PC-1 and PC-2. Thus, the synchronization is corrected during the process of receiving PNP, and the operation of the device for effective reception of PNP continues (as described above).

In parallel with the synchronization correction process, synchronization is checked (monitored) (in conditions of a significant level of interference). For this purpose, the signals SP _1,i and SP _2j - from the outputs of BCC-3 (43) and BCC-4 (44) are supplied to the corresponding inputs of the first and second KA-1 and KA-2 (49 and 50), which register the incoming signals only from different inputs (“analysis” function). The recorded signals are summed up for the set observation time T _set and after T _set . the accumulated numbers of these signals as are issued to the input of the first and second threshold devices PU-1 and PU-2 (51 and 52) with set thresholds, respectively respectively. And if then from the outputs of PU-1 and PU-2 (51 and 52) signals “Yes” = 1 are sent to the first and second inputs of the MSS matching receiving circuit (53), respectively. If the “Yes” = 1 signals arrive simultaneously at the first and second inputs of the PSS (53), then this will indicate a failure of synchronization due to interference, and the PSS (53) produces at its output the signal “stop receiving PNP, begin the search and detection stage ”, which as a “blocking signal” is sent to the blocking inputs of BPS-1 and BPS-2 (27...32), thereby stopping the operation of channels for receiving PNP. After this, re-entry into synchronism begins (as described earlier).

After re-entering into synchronism, the “unblocking signal” is sent from control circuit 3 to the third (unblocking) input of the PSS (53), thereby stopping the supply of the blocking signal from the output of the PSS (53), and the process of receiving the PNP is resumed.

In fig. 1 (Table 1) shows the dependence

In fig. 2 shows the gain in reliability graphically , that is - in IRDRP mode compared to IRORP mode and discrete method of two-channel solution and reception depending on probabilities

Figure 3 shows the dependence from signal/noise ratio calculated using the Crump function.

In fig. 4 shows the dependence from to for fixed values n=8,10.

In fig. 5 shows the dependence from n at a fixed value k=n/2.

In fig. Figure 6 shows the areas of feasibility of using the prototype device and the proposed device depending on the values at and number meanings as part of the PNP.

In fig. Figure 7 shows a model of the rule for forming a PNP.

In fig. 8 shows the dependences: average sample accumulated value private automorphic PVKF _1i PNP with with automorphisms i PC l ₁ for all possible values i=0,...,l ₁ at PNP run periods equal to p=1,...,15, i.e. for p ₁ =13,...39 runs of PC-1 with l ₁ (Fig. 8, a) and the average sample value of the sum under the same conditions (Fig. 8, b).

In fig. Figure 9 shows a table of PVKF values of PNP of various types with producing lines.

In fig. Figure 10 shows graphs of the dependence of the general PVKF of PNP of the KZKZ type with its copies for some lengths

In fig. Figure 11 shows graphs of the dependence of: private PVKF PNP type K3K3 of length L = 77 with generating lines composed of KKV (Fig. 11, a); private PVKF PNP type K1K1 length L=221 with producing lines composed of KKV (Fig. 11, b); private PVKF PNP type K1K3 length L=323 with producing lines composed of KKV (Fig. 11, c); private PVKF PNP type K3K1 length L=143 with producing lines composed of KKV (Fig. 11, d).

In fig. Figure 12 shows a numerical model for obtaining simultaneously, in parallel, automorphic private PVKFs of the incoming PNP (with with automorphisms (cyclic shifts) of the generating component (PC) with

In fig. Figure 13 shows a computer model of partial automorphic PVKF PNPs with its automorphisms (cyclic shifts) PCs with for PNP length

In fig. 14 shows the dependence of the error probability under different modes of TRS implementation and durations L of PNP.

In fig. Figure 15 shows the order of correlation of segments of the incoming PNP and the reference signal (RS) at two adjacent processing cycles.

In fig. 16a, b, c, shows a diagram of the device.

In fig. 17 shows the dependences of the equivalent linear complexity different types of PSPs (K3K1, K3K3, K1K3, K1K1) and known linear PSPs (Golda, Kasami, M-sequences) on their length L.

In fig. Figure 18 shows the dependence of the probabilities of successful delay synchronization on the degree of distortion of the received signal (as a percentage of the total number of PRP symbols) for PNP lengths L=77 and various L*=L⋅K, K=5, 10, 100, 1000 when using the method- prototype with 32 runs of PNP lengths (dashed lines) and when using the proposed method with one and three runs of PNP lengths.

The possibility of realizing the advantages of the proposed method is confirmed by the following technical indicators and their digital values:

1) the results of simulation modeling of the process of accumulating PVKF of segments of the received SRS-PNP with segments of the reference generating line being updated (with each clock cycle of the PSP). The process of mutual correlation in the AEC of segments of the received and reference signals at two adjacent processing cycles is illustrated in Fig. 15 (θ ₁ and θ ₂ - AEC integration time, τ _e - duration of an elementary PNP symbol).

2) the possibility of reliable choice at the substage of primary accumulation of accumulated private subchannel and channel sums S ₁ and S ₂ , which is confirmed by those shown in Fig. 8 dependencies that demonstrate that even with the number of runs of the entire PNP no more than 3, there is a pronounced increase and and most importantly, a pronounced increase in S1 and _S2 above the interference level. This is confirmed by the expressions: the values of the accumulated private PVCF in each search subchannel of the 1st and 2nd channels, respectively

where [⋅], (⋅) - numbers of measures of the beginning of the segment relative to the initial arbitrary shift, - relative values of PVKF between segments with [⋅] length accepted by SRS-PNP and segments the same lengths of the support generating lines of automorphisms PC-1, PC-2,

- values of the sums S ₁ and S ₂ of accumulated private subchannel sums

- probabilities correct choice of extremes from l ₁ and l ₂ values is determined for each search subchannel of the 1st and 2nd channels:

Where - densities of the normal probability distribution of private values accumulated in the search subchannels of the first and second channels in clock cycles with the corresponding PC-1, PC-2; function density of the normal probability distribution of the PVCF values accumulated in the search subchannels of the 1st and 2nd channels in shift cycles that do not correspond to the synchronization of the PNP segments with the reference PC-1, PC-2;

3) the possibility of reliable extrapolation of subchannel numbers with maximum

by control factor for extrapolation of subchannel numbers:

a) the probability of correct extrapolation of one subchannel into one i-th and j-th clock cycles of the first and second channels:

b) the probability of correct extrapolation of subchannel numbers when using the majority control principle:

by accumulation level control factor:

a) probability of correct extrapolation:

b) the probability of correct extrapolation of the extrapolation substage:

The overall probability of correct synchronization is given by:

The ability of the proposed device to provide, in a small number of accumulation periods, a received signal with a high probability of delay synchronization is confirmed by those obtained as a result of simulation modeling (for PNP lengths L=77 and L*=L⋅5=385) and shown in Fig. 12 dependences of the probability of successful synchronization _Рос on the degree of distortion of the received signal (as a percentage of the total number of PRP symbols). Comparison (with equal bases (L) of the SRS) of the value of the achieved relative search time, expressed in the number of periods of analysis of the SRS, with a similar indicator for known methods (including the prototype), indicates the advantage of the proposed method in the search time of the SRS by a delay of approximately 20 -30 times before convolver search [2] using known PSPs, 100 times or more before multi-stage search [2], 100 times or more before sequential cyclic search [2] and 10 times or more before prototype [6].

The implementation of high imitation resistance of the signals used is confirmed by those shown in Fig. 11 dependences of the equivalent linear complexity of different types of PNPs (K3K1, K3K3, K1K3, K1K1) and known linear PSPs (Golda, Kasami, M-sequences) on their length. The advantage in equivalent linear complexity is approximately 5 times or more for lengths and increases with increasing PSP length.

The possibility of providing the proposed method and device with effective reception of SRS in the form of PNP and making a decision using in the final mode two-channel reception and decision within the framework of the TRS method, described in particular in [9], is confirmed by those obtained as a result of simulation modeling using relations (18, 19) and shown in Fig. 14 dependencies of the probabilities _Posh of erroneous reception of PNP durations when using the proposed method and device (graphs III) and without their use, but using spatial diversity (SD) with the corresponding number of diversity branches Q and correlation coefficients R of diversity branches (graphs I, II).

As can be seen from the analysis of the graphs, the TRS implemented by the proposed device makes it possible to increase the noise immunity (according to _Rosh ) of SRS reception in the form of PNP by 3...5 orders of magnitude compared to the known classical methods of diversity reception (for example, “PR”) and by one to two orders of magnitude compared to known analogue methods and a prototype. And increasing noise immunity is “akin to” increasing the power of the signal _Pc at the output of the TRS, which, therefore, provides a corresponding increase in the throughput C (according to Shannon) [9]. It should also be noted that this increase in C is also due to the acceleration of search detection and synchronization provided by the proposed device. Thus, we can objectively talk about the achievement by the proposed method of high efficiency of taking SRS in the form of PNP in terms of parameters _P or C. Moreover, these advantages are achieved over a significantly expanded range of (almost all possible) duration values elements generating PNP - NLRP and their ratios in comparison with the prototype and analogues, which significantly increases the practical feasibility of widespread use of the proposed device.

The construction of the proposed device is possible (as well as a prototype device) within the framework of a signal processor on a modern high-speed element base with a high degree of integration, including acousto-electronic convolver technologies [11]. At high clock frequencies of the memory bandwidth f _{memory bandwidth} , exceeding the performance capabilities of the ADC, the conversion functions can be distributed among several (m) ADCs, so that each of them provides conversion at the sampling frequency Digital comparators can be implemented using ICs such as full adders. RAM made on the basis of shift registers has sufficient speed and does not require special distribution and switching devices. NLRP reference sequence generators are implemented both on the basis of theoretical and technical methods outlined in [12, 13], and on direct, patented technical solutions according to AS: SU 1401475 A1, SU 1457650 A1, SU 1537022 A1, SU 1470095 A1, - and the patent of the Russian Federation RU 2024053 C1.

The checking device (13) in FIG. 16a represents a set of two-input AND elements, and the accumulator-adder (11) in FIG. 16a can be built on the basis of two counters (counter “1” and clock counter) and a comparing (threshold) device. The implementation of new blocks and nodes introduced into the prototype device is similar to the implementation of similar elements of the prototype device circuit. So: valve nodes are a collection (union into a node) of valves; digital comparator blocks (DC) are a combination of digital comparators; “receiving” CC means performing the function of a CC when receiving PNP; majority comparators are ordinary central control centers, the execution of functions of which leads to the execution of the function of majority selection of input signals; the comparator-analyzer performs the traditional functions of a central control unit with the output of the corresponding “compared” solution; corrective delay calculators are the same calculators as the delay calculators from ₁ and ₂ of the prototype device, only they are used to correct synchronization, and not to enter into synchronization (as in the prototype device).

That is, additional adjectives to the words “comparator” and “calculator” only mean the role of this function for the operation of the device, without affecting the essence of the construction of their technical electrical circuits.

The remaining elements of the device are the known simplest elements of discrete technology.

The inventive device can be used both independently and to reduce search time and increase the efficiency and reliability of receiving SRS manipulated by PNP, while complementing traditional devices that use the correlation level along the entire length of the reference and received signals to detect the fact of delay synchronization and the fact of receiving its own SRS and implementing known cyclic multi-stage or other search and reception methods. The applicability of this method and the device that implements it is, first of all, associated with the use of SRS manipulated by PNP based on KKV codes. At the same time, high structural secrecy of the synchronization and reception stage is ensured, as well as the possibility of quickly adapting the radio link to the information and interference environment by changing the value of the PNP length with small discreteness.

Information sources:

1. Varakin L.E. Communication systems with noise-like signals [Text], - M. “Radio and Communications”, 1985. - 384 p.

2. Zhuravlev V.I. Search and synchronization in broadband systems [Text], V.I. Zhuravlev, M., “Radio and Communications”, 1986

3. Snytkin I.I. Delay synchronization in digital processing of ultra-long recurrent sequences [Text] / I.I. Snytkin, V.I. Burym, A.G. Serobabin, News of higher educational institutions. Radioelectronics, No. 7, 1990

4. Patent No. 2297722 Russian Federation, MPK8 H04L 7/08, G06F 17/15. Method for accelerated search of broadband signals and device for its implementation: No. 2005114601/09; application 05/13/2005; publ. 04/20/2007 / Fedoseev V.E., Snytkin I.I., Varfolomeev D.V.; applicant SVVAIU. - 32 s.; ill. - Text: immediate.

5. Patent No. 2514133 Russian Federation, MPK8 H04 L7/08, G06 F17/10. Method for accelerated signal search and device for its implementation: No. 2012108704/08; application 03/06/2012; publ. 04/27/2014/ Snytkin T.N., Snytkin I.P., Spirin A.V.; BAS branch. - 38 s.; ill. - Text: immediate.

6. Patent No. 2718753 Russian Federation, MPK8 H04L 7/08, G06 F7/10. The device of the third decisive circuit for accelerated search and efficient reception of broadband signals: No. 2019124942; application 10/28/2019, publ. 04/28/2020, bulletin. No. 11 / Snytkin I.I., Snytkin T.I., Kokoreva O.S.; KVVAUL. - 42 s.; ill. - Text: immediate.

7. Patent No. 2766859, Russian Federation, MPK8 H04L 7/08, G06 F17/10. The device of the third decisive circuit for accelerated search and effective reception of broadband signals: No. 2020134561; application 20.10.2020; publ. 03/16/2022 bulletin. No. 8 / Snytkin I.I., Snytkin T.I., Zakharenko G.I., Kokoreva O.S., KVVAUL. - 47 s.; ill. - Text: immediate.

8. Snytkin I.P., Snytkin T.I. Development of elements of the theory of the third decisive scheme for receiving derivatives of nonlinear recurrent sequences [text]. Nonlinear world No. 5, volume 12, 2015, pp. 78-84. Publishing house "Radiotekhnika".

9. Snytkin T.I. “Analogue decision-making modes for acceptance in the theory of the third decision circuit” [text]. Nonlinear world No. 3, 2018, pp. 15-19. Publishing house "Radiotekhnika".

10. Fink L.M. The theory of discrete message transmission. Soviet Radio Publishing House, 1970, p. 728.

11. Dolgov V.I. The use of acoustoelectronic convolvers for signal processing in communications technology [Text] / V.I. Dolgov - Foreign radio electronics No. 8, 1990

12. Snytkin I.I. Theory and practical application of complex signals of nonlinear structure. Part 4. [Text] / I.I. Snytkin - Moscow Region, 1989

13. Snytkin I.I. Theory and practical application of complex signals of nonlinear structure. Part 3. [Text] / I.I. Snytkin - Moscow Region, 1989

14. Sverdlik M.B. Optimal discrete signals [Text], “Sov. radio", M., 1975

15. Kuzmin I.V., Kedrus V.A. Fundamentals of information theory and coding. Kyiv, Higher School, 1977, p. 280.

16. Handbook of mathematics. G. Korn, T. Korn. Under the general editorship of I.G. Aramovich. Translation from the second American edition. Ed. “Science”: Moscow, 1974 - 832 p.

Claims (1)

The device of the third decisive circuit for accelerated search and effective reception of broadband signals, containing two identical correlator-type processing channels, and the correlation processing is implemented on the basis of acoustoelectronic convolvers (AEC), the received signal is supplied to one input of each channel; Moreover, each processing channel contains a reference sequence generator, the first output of this generator of each channel is connected to the corresponding input of the derivative signal generator, the output of which is connected to one of the inputs of the delay synchronism control circuit, the other input of which is the input of the received signal, and the input of the reference sequence generator each channel is connected to the output of the corresponding shift calculator c ₁ and c ₂ , and in each processing channel the reference sequence generator is made in the form of a generator of all possible automorphisms (cyclic shifts) issued in parallel across a group of second outputs, respectively, and output from the first output of one of the automorphisms of the support sequence of the generating repeating component of length respectively; block of digital subcorrelators (DSPC), which contains, respectively, for each channel subcorrelators, each of which contains: a series-connected acoustoelectronic convolver (AEC), one input of which is the first input of the subcorrelator and is connected to the first input of the processing channel, and the second input is the second input of the subcorrelator and is connected to one of the second outputs of the reference sequence generator; the amplifier and the analog-to-digital converter (ADC), the output of which is a parallel output bus and is the output of the subcorrelator and the corresponding output of the BCPC, the output of which is a parallel output bus, are connected to the corresponding inputs of the accumulation and extrapolation circuit (SNE), which contains, respectively, for one and the other processing channels for l ₁ and l ₂ search subchannels, the inputs of which are the corresponding inputs of the SNE, and the outputs are connected to the corresponding first inputs of the central digital comparator (DCC), the first input of which is connected to the output of the first key, and l ₁ and l ₂ the outputs (for one and the other channel, respectively) are connected, respectively, to the inputs of the digital adder and to the first key inputs of the key block (KB), containing, respectively, l ₁ and l ₂ keys, the second inputs of which are connected to the output of the first key, and the outputs of the keys BC are connected to the corresponding inputs of the shift calculator c ₁ and c ₂ , respectively, the output of which is the output of the SNE and the processing channel and is connected to the input of the corresponding reference sequence generator, and the output of the digital adder is connected to one input of the first key, the other input of which is connected to the output of the accumulator-adder, input which is connected to the output of the check block, which is a block (set) of two-input AND elements, the first the inputs of which are connected to the corresponding outputs of the central circulation center and the inputs of the subchannel number selection block (BVNP), which is a cross-block and a clock delay block connected in series, the outputs of which are connected to the second check block inputs; Moreover, each search subchannel (SSC) of the accumulation and extrapolation circuit (SNE) contains a digital parallel adder, the first inputs of which are connected to the corresponding bus of parallel outputs of the BPCP, and the second inputs are connected, respectively, to the outputs of the corresponding matching elements, the first inputs of which are clock, the second inputs are connected respectively, with the outputs of a random access memory (RAM), the inputs of which are connected to the outputs of a digital parallel adder and the corresponding first inputs of the second switch, the second input of which is connected to the output of the first counter, the input of which is a clock one, and the input of the second counter, the output of which is connected to one input an AND circuit, the output of which is connected to the output of the control panel, and the second input is connected to the output of a digital comparator, the inputs of which are connected to the outputs of the second switch; and the device also contains: the first and second channels for receiving and making decisions as receiving parts of the first and second processing channels and containing the first and second blocks, respectively parallel adders (BPS-1 and BPS-2), parallel buses respectively, the inputs of which are connected respectively to tires on parallel outputs of the first and second blocks of digital subcorrelators (BTsPK-1, BTsPK-2), respectively, and buses from 1st to and from 1st to accordingly parallel outputs of BPS-1 BPS-2 are respectively connected to the first and second groups by according to tires inputs respectively of the first and second blocks of digital comparators (BTsK-1, BTSK-2) and the corresponding ones from 1st to and from 1st to tires on respectively, parallel inputs of the first and second nodes from 1st to and from 1st to respectively valves (UV-1, UV-2), the control input of each of which is connected respectively from 1st to and from 1st to outputs, respectively, of the first and second blocks of keys of accumulation and extrapolation circuits (SNE) of the first and second processing channels, respectively, and the corresponding ones from the 1st to and from 1st to tires by respectively parallel outputs corresponding from 1st to and from 1st to respectively, the first and second UV-1 and UV-2 are connected, respectively, to the third and fourth group by according to tires inputs respectively BTSK-1 and BTSK-2, and outputs from 1 to and from 1 to which are respectively connected from 1 to and from 1 to inputs of the third and fourth BCC-3 and BCC-4, respectively, outputs from 1 to and from 1 to which are connected respectively from 1 to and from 1 to inputs, respectively, of the first and second comparator-analyzer (KA-1 and KA-2) and from 1 to and from 1 to inputs, respectively, of the first and second blocks of majority comparators (BMK-1 and BMK-2), outputs, respectively, from 1st to and from 1st to which are connected respectively from 1st to and from 1st to inputs, respectively, of the first and second corrective delay calculator (KVZ-1 and KVZ-2), respectively, with ₁ and with ₂ , the outputs of which are connected, respectively, to the input of the first and second reference sequence generators GOP-1, GOP-2, and the output of the first and the output of the second KA-1 and KA-2 are connected, respectively, to the input of the first and the input of the second threshold device (PU-1 and PU-2), the outputs of which are connected, respectively, to the first and second inputs of the receiving coincidence circuit (RCC), the output of which is an output blocking the reception of PNP and is connected to the blocking inputs of the first and second blocks of parallel adders BPS-1 and BPS-2, respectively, and the third input of the PSS is a release input and is connected to the release output of the synchronization control circuit (SCS), and the second inputs of GOP-1 and GOP-2 are connected respectively, with the outputs of the first and second corrective delay calculator KVZ-1 and KVZ-2, characterized in that the corresponding ones from the 1st to and from 1st to tires by respectively parallel outputs corresponding from 1st to and from 1st to respectively, the first and second UV-1 and UV-2 are connected, respectively, from the 1st to and from 1st to tires on parallel, respectively, first and second inputs of the final adder (IS), the output of which is connected to the input of the deciding device (DR), the first and second outputs of which are the decisive outputs (“Yes” and “No”) of the device as a whole.

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