RU2808390C1 - Digital sign correlator - Google Patents

Abstract

FIELD: radio engineering; measurement technology.

SUBSTANCE: invention can be used in devices for measuring the correlation coefficient of a random signal, in devices for estimating the parameters of a random signal of control and information transmission equipment, intended for correlation analysis of random processes represented by digital codes. The technical result of the invention is the developing of a device for calculating the cross-correlation function of two signals, which has a small hardware volume compared to similar digital devices. The technical result is achieved by connecting the outputs of each code comparison circuit through a gate and a switch with a shift register, the bit outputs of which are connected to matching circuits, the second inputs of which are connected to the outputs of the decoder, and the outputs through a collecting circuit and an additional matching circuit are connected to the second counter, the second The gate inputs are connected to two control trigger outputs. A feature of the proposed device is the use of only one additional random signal generator.

EFFECT: developing of a device for calculating the cross-correlation function of two signals, which has a small hardware volume compared to similar digital devices.

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Description

The invention relates to the fields of radio engineering and measurement technology and can be used in devices for measuring the correlation coefficient of a random signal, in devices for estimating the parameters of a random signal of control and information transmission equipment, intended for correlation analysis of random processes represented by digital codes.

A large number of correlators are described in [Zhovinsky V.I., Arkhovsky V.F. Correlation devices. M.: Energia, 1974], however, many of them are complex in technical implementation, have a large hardware volume and low performance, the closest analogue is a digital correlator [Patent RU 2735488 C1 Russian Federation, IPC G06F 17/15 (2006.01) digital correlator / O.V. Chernoyarov et al./ Federal State Budgetary Educational Institution of Higher Education Maikop State University (RU). - No. 2020113740, application. 04/03/2020, published: 11/03/2020 Bulletin. No. 31].

The proposed correlator differs in that it uses a single uniformly distributed random number generator coupled to two comparison circuits connected via gates and a switch to a shift register used as a delay device. Moreover, its bit outputs are connected through coincidence circuits, the second inputs of which are connected to the decoder, with a common collecting circuit. The latter is connected to the output counter through an additional coincidence circuit.

The essence of the invention is illustrated by a drawing, which shows a functional diagram of a signed digital correlator, where:

1, 2 - code generators for the signals under study;

3, 4 - code comparison schemes;

5, 6 - valves;

7 - generator of uniformly distributed random numbers;

8 - clock generator;

9 - control trigger;

10 - frequency divider;

11 - first counter;

12, 13 - switches;

14 - shift register;

15 - matching schemes;

16 - collective diagram;

17 - additional matching circuit;

18 - second counter;

19 - decoder.

The operation of the proposed device is as follows.

At clock times set by generator 8 through trigger 9, the current value of the random function under study from generator 2 is compared in circuit 4 with a uniformly distributed random number generated at each clock time by generator 7. A pulse appears at the output of circuit 4 if the current value of the random code of the input signal is not less than the random number. The sequence of binary signals “1” and “0” thus generated at the output of circuit 4 is supplied through gate 5 and switch 12 to the k-bit shift register 14. The information in the shift register for each clock pulse is shifted one bit to the right. The information stored in the shift register is fundamental for obtaining the correlation function of the random process under study. The outputs of the shift register are connected to the inputs of the coincidence circuits 15, which are alternately polled by signals from the decoder 19 with a frequency of ƒ/N, where ƒ is the frequency of receipt of clock pulses from the trigger 9.

The polling device works as follows.

The input of the frequency divider 10 receives pulses with a frequency ƒ from a trigger 9 connected to a clock pulse generator 8. Pulses with a frequency of ƒ/N appear at the output of the divider and are sent to the input of counter 11 with n digits. The number of bits n is chosen so that 2 ⁿ = k. The outputs of the counters are connected to the inputs of the decoder. Resolution potentials appear at the outputs of the decoder, with the help of which sequential interrogation of coincidence circuits 15 is carried out. The outputs of the coincidence circuits are connected to the inputs of the collecting circuit 16, the output of which is connected to the input of the output counter 18 through the coincidence circuit 17. The counter 18 registers the current values of the correlation function. The output counter 18 is the output of the entire circuit.

When determining the cross-correlation function, the current values of the random functions under study from generators 1 and 2 are supplied to the inputs of comparison circuits 3 and 4, where they are compared with the values of uniformly distributed random numbers generated by generator 7 of uniformly distributed random numbers.

A pulse appears at the output of each comparison circuit if the current value of the corresponding random function is not less than the value of the random signal. Each of the valves 5 and 6 opens for the passage of a pulse from the output of the corresponding comparison circuit after one clock cycle, that is, at the moment the enabling potentials are supplied from the outputs of the control trigger 9. This method of interrogating comparison circuits is equivalent to using two uniformly distributed random number generators, since each subsequent random number does not depend on the previous one.

The mode for calculating the autocorrelation function is as follows: switch 13 in position AK, switch 12 in position b.

The sequence of double symbols “1” and “0” generated at the output of circuit 3 enters the k-bit shift register 14, which performs the function of a dynamic memory device. The information in the shift register for each signal from the output of control trigger 9 is shifted to the right by one bit. The outputs of the shift register are connected to the first inputs of the coincidence circuits 75, the second inputs of which are alternately supplied with polling signals from the decoder 19 with a frequency of ƒ/N.

Further operation of the circuit proceeds as described above.

When calculating the cross-correlation function, switch 13 is set to position VC, and switch 12 to position a . In the coincidence circuit 17, the signals arriving at its inputs from the output of gate 6 and the signals from the output of circuit 16 are multiplied in pairs, that is, the output signals of gate 5 delayed in the shift register 14.

The technical and economic efficiency of the proposed probabilistic coordinate calculator consists in reducing its hardware volume while maintaining the accuracy characteristics and the ability to process the input signal in real time.

Claims (1)

A signed digital correlator, characterized by the fact that the circuit includes two generators of the signals under study, two code circuits, two gates, two switches, two counters, a uniformly distributed random number generator, a shift register, a control trigger, a frequency divider, a decoder, and a clock pulse generator , coincidence circuits, a collective circuit and an additional coincidence circuit, at the beginning of the operation of the circuit, the values of the signals under study are written to the generators of the signals under study, the outputs of which are loaded onto the corresponding inputs of the code comparison circuits, the outputs of which are loaded onto the inputs of the corresponding gates, the second control inputs of which are loaded from the control output trigger, the gate outputs are loaded onto the inputs of the first switch, at the same time the output of the second gate is also loaded onto the first input of the second switch, the output of the first switch is loaded onto the input of the shift register, the parallel outputs of which are loaded onto the first inputs of the matching circuit, the second inputs of which are loaded onto the decoder outputs, onto the control inputs of which are loaded, the outputs of the first counter, the information input of which is loaded on the output of the frequency divider, the input of which is also loaded on the output of the control trigger, the serial output of the shift register is loaded on the second input of the second switch, the output of which is loaded on the first input of the additional coincidence circuit, on the second input which is loaded with the output from the collecting circuit, the inputs of which are loaded with the outputs of the coincidence circuit, the output from the second counter is the output of the entire circuit.

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