RU2808097C1 - System for formation and processing of radio signals in short wave range - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: invention is used to construct circuit and design solutions for signal conditioners, solid-state power amplifiers and HF antenna-feeder systems. The result is achieved by proposing a system for generating and processing radio signals in the short-wave range, in which a digital computer is connected to user interfaces through a power amplifier with a receiver, and four analogue-to-digital converters are designed to operate synchronously from one master oscillator and the ability to select the conversion frequency in range from 65 to 250 MHz for operation in the main Nyquist window, while this architecture is designed to receive radio signals from four different antennas simultaneously to build a radio receiver and the ability to use adaptive processing algorithms.

EFFECT: improvement in the quality of information reception in conditions of fast and slow fading of signals present in the ionospheric radio channel, as well as compensation for interference and adaptation in frequency.

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Description

The present invention relates to the field of radio engineering and communications, and can be used to construct circuit and design solutions for signal conditioners, solid-state power amplifiers and HF antenna-feeder systems.

In the field of information transmission and processing, digital technologies play a major role. In radio communications, digital technologies have become most widespread when using personal computers to modulate and demodulate radio signals. Thus, almost the entire amount of signal processing work was transferred to software, which defined the term Software Defined Radio (SDR). The goal of this approach is to create a system that can receive and transmit almost any radio signal using software that is a priori flexible and adaptive. Currently, SDR technologies are widely used in radio and cellular communications, where real-time support for a variety of changing radio protocols is required.

Various methods for generating and processing signals are known. For example, RF patents No. 2527943, 2305295, 2432580, 2001107088, 2110809, US 6469657 B1, 10/22/2002. US 6148195 A, 05/10/1998. WO 2005045459 A3, 07/07/2005. US 6903685 B1, 06/07/2005.

A device for optimal processing of signal sequences with carrier frequency modulation is known. RF Patent No. 2237908 October 10, 2004 (Prototype). A device for optimal processing of sequences of wideband signals with carrier frequency modulation contains parallel channels, each of which includes a bandpass filter, a quadrature phase detector, a 90-degree phase shifter, a delay line, an analog-to-digital converter, a buffer memory device, a moving target selection filter unit, N blocks delays, N switches, output channels, each of which contains a compression filter, a module determination block, a threshold block.

However, neither analogues nor the prototype provide improved information reception in conditions of signal fading, due to its propagation over the radio channel, as well as compensation for interference and adaptation to frequency.

The purpose of the invention is to improve the reception of information in conditions of signal fading, due to its propagation over a radio channel, as well as compensation for interference and adaptation in frequency.

The goal is that the signal generation and processing system is made in the form of two modules, while the first frequency conversion module is a four-channel analog-to-digital converter (ADC), which contains a low-pass filter (LPF), a digitally controlled amplifier , bandpass filter (PF), analog-to-digital converter and reference oscillator, with the low-pass filter connected in series with a digitally controlled amplifier, PF and ADC, the second module is a digital signal processing (DSP) and control unit, which includes a digital computer consisting of digital signal processor and processor core, while the digital computer is connected by its inputs to an ADC and its output to an interpolating digital-to-analog converter (DAC), which is connected to a reference oscillator, and the digital computer is connected to user interfaces and through a power amplifier to a receiver, with four analogue digital converters, operate synchronously from one master oscillator, and to eliminate intersymbol interference and work in the main Nyquist window, the conversion frequency is selected in the range from 65 to 250 MHz, while this architecture allows receiving a signal from four antennas simultaneously to build a radio receiver, and synchronous Reception of signals from four different antennas allows the implementation of modern adaptive processing algorithms.

Thus, the signal generation and processing system (SFOS), in contrast to analogs and the prototype, provides improved information reception in conditions of signal fading as it propagates over a radio channel, as well as interference compensation and frequency adaptation.

The block diagram of the proposed SFOS is presented in Fig.1.

1 - frequency conversion module;

2 - digital signal processing and control module;

3 - user interfaces;

4 - reference generator;

5 - radio receiver;

6 - power amplifier;

7 - low pass filters;

8 - amplifier with digital control;

9 - bandpass filters;

10- analog-to-digital converter;

11 - digital-to-analog converter;

12 - digital computer.

The frequency conversion module 1 contains: a low-pass filter 7, a digitally controlled amplifier 8, a bandpass filter 9, an analog-to-digital converter 10, a digital-to-analog converter 11 and a reference oscillator 4.

DSP and control module 2 provides a high-speed interface for communication via fiber-optic communication lines (FOCL) of several SFOS hardware platforms. In this case, one of the platforms is installed in close proximity to the antennas. After pre-processing, the signals are transmitted over considerable distances to another platform. On this platform, analog-to-digital conversion module 10 can be omitted, or a module with additional optical interfaces can be installed instead.

Four-channel input and output low-pass filters 7 provide signal selection, i.e. transfer of the spectrum of signals coming from antenna elements to the low frequency region. The input analog filters are a low-pass filter 7 with a cutoff frequency of 30 MHz, having a suppression level of no worse than 80 dB.

The digitally controlled amplifier 8 converts the level of the signal arriving at its input to the value necessary for subsequent conversion and digital processing (in the receiving path) or for radiation (in the transmitting path). Analogue amplifiers with digital control 8 have a linear amplitude-number characteristic (AFC) in the band from 0 to 30 MHz with the ability to change the gain in the range from 0 to 100 dB.

Bandpass filters 9 provide bandwidth depending on the type of manipulation used , Where - bandwidth occupied by the signal and - carrier frequency; ADC 10 and DAC 11 provide a quantization step of no more than 1.5×10 ^-5 and operate from a reference oscillator with a clock frequency of ~168 MHz and a reference oscillator frequency of the optical interface of ~125 MHz. The use of DAC 11 with interpolating filters at an input sampling frequency of 250 MHz and quadruple interpolation will make it possible to achieve a digital-to-analog conversion frequency of 1 GHz. As a result, the generated signal, even at the upper limit of the HF range, will have good spectral characteristics. The use of a modern DAC with interpolating filters at an input sampling frequency of 250 MHz and quadruple interpolation will make it possible to achieve a digital-to-analog conversion frequency of 1 GHz. As a result, the generated signal, even at the upper limit of the HF range, will have good spectral characteristics.

Digital computer 12 is implemented on FPGA technology and provides various user interfaces (Ethernet, asynchronous serial interface, etc.), while the clock frequency of the reference oscillator of the DSP circuits is -200 MHz.

If the width of the signal spectrum in which information is transmitted does not exceed tens of kilohertz, then, as already noted, it is advisable to implement algorithms for generating and receiving modem signals on a signal processor. The algorithms are implemented for signals presented in complex form with the center of the spectrum located at zero frequency (the so-called shifted signal - BaseBand). Transferring the signal spectrum from BaseBand to the frequency range in which radio transmission occurs does not require much algorithmic complexity, but the computational resources are quite significant. If the frequency of the radio signal does not exceed several hundred megahertz, it is possible to directly work with such a signal in digital form. It is necessary to transfer the signal for transmission up the spectrum and down for reception. For this purpose, digital blocks are used - converters DUC (Digital Up Converter) and DDC (Digital Down Converter), respectively.

There is a wide range of DUC/DDC ICs available, but they are all designed for a narrow or specialized application. Some applications may require higher computational accuracy, greater dynamic range, or deeper filtering, which existing ASICs can provide. The use of FPGA allows you to obtain a fully configurable solution. With this approach, DUC/DDC blocks are implemented with any characteristics, and what is most valuable, the implementation option will not be “frozen”, but can be upgraded and modified for other applications. For example, with sufficient FPGA resources, it is possible to implement simultaneous multi-channel reception and transmission.

Algorithms for modulation and demodulation proper for HF channels are characterized by relatively low information speed and high computational complexity, large branching, and the presence of fuzzy logic elements. Such algorithms are well implemented in software on signal processors, but some routine operations can be implemented on FPGAs.

A functional diagram of a DSP and control module with distributed processing on an FPGA (FPGA) and a processor (Fig. 2) is proposed, consisting of:

13- DDC blocks;

14 - adjustable delay line;

15 - adaptive filter;

16-decemation filter;

17 - digital AGC;

18 - clock signaling systems;

19- module for correlation signal processing and framing;

20 - operator module;

21 - configuration, monitoring and control module;

22 - a set of demodulators, decoders;

23 - a set of modulators, encoders;

24 - DSSS generation modules (Direct Sequence Spread Spectrum - direct sequence method for expanding the spectrum);

25 - signal level regulator of the signal transfer block to the carrier;

26 DUC blocks;

27 - transfer to carrier;

28 - carrier transmission generator;

29 - symbol rate generator;

30 - module for receiving/transmitting data and control commands via fiber-optic communication lines;

31 - interface for receiving/transmitting data flow, control and monitoring commands.

The signal arriving at the input of the receiving path is fed to the DDC 13 block. The block suppresses interference in the mirror reception channel by more than 100 dB and completely eliminates interference at zero frequency. The principle of digital conversion in the DDC 13 block comes down to obtaining from a broadband complex digital signal (at a very high sampling rate) a single target signal, the band of which is significantly narrower than the band of the source signal. The architecture of the block, which ensures the implementation of digital filtering at a high data flow rate, requires a large computing resource and is performed only in hardware. It is implemented on a Digital Signal Processing (DSP) FPGA with built-in hardware multipliers.

The adjustable delay line 14 allows you to correct the phase shifts of the signal resulting from the passage of the signal through the transmission channel. Adaptive filter 15 performs the operation of convolving input samples with coefficients. Decimation filter 16 allows you to reduce the signal sampling frequency.

The digital AGC block 17 automatically sets the signal level for its subsequent processing.

The clock synchronization system 18 ensures equal signal processing speeds (encoding and decoding of samples, combining and dividing digital streams) at the transmitting and receiving stations.

The correlation signal processing and signal framing module 19 allows you to divide the input stream into separate information words. After framing, each information word, depending on the received signal, is sent to the digital demodulation and decoding unit 22.

The operator module 20 allows, depending on the type of message, switching within the processor unit to user interface modules 3.

When transmitting a signal, the operations are performed in reverse order, changing the sampling rate if necessary to increase the transmission speed.

The circuit shown in Fig. 2 is controlled via fiber optic link 30 using an FPGA from Xilinx. The system state is displayed on the interface for receiving/transmitting data flow, control and monitoring commands 31.

The distribution of the functional load between the FPGA and the processor is done taking into account the algorithmic complexity, the required speed of operation, as well as the location of the functional element in the overall scheme of the data and signal processing pipeline.

When implementing the proposed system, a configuration is provided i.e. Multiplexers are installed in the transmission and reception path, allowing you to change the composition of functional elements in the processing pipeline, for example, in the reception path, “bypass” the clock synchronization system or exclude the DSSS signal generation module from the transmission path.

The diagram does not show the logical connections between the processor and the functional elements in the FPGA, which are used to configure, configure, control and monitor them 21. For example, the adaptive filter 15 performs the operation of convolving input samples with coefficients at a fairly high speed, and the coefficients themselves are at a slower rate are calculated in the adaptation subroutine and loaded into the filter under processor control.

Complex algorithms such as demodulation, 22 decoding, speech compression, etc. taking into account the low information speed, they are implemented in the form of software modules for the processor. The processor is also responsible for working with user interfaces and general system management.

In order to increase the stability of the communication channel to the physical phenomena of the propagation environment, a frame structure of the modulated signal has been introduced, while maintaining its continuity. A variant of the frame format is presented in Fig. 3.

Here, the Header and Pilots service fields do not carry user data, but are intended to facilitate and improve the quality of demodulation of PayLoad Blocks user data fields. This is achieved thanks to the following:

- the type of modulation of the Header and Pilots fields allows them to be demodulated at a fairly low quality of the transmission channel;

- Pilots fields have predefined values;

- the Header field has strong autocorrelation properties and carries encoded information about the type of modulation and noise-resistant coding of PayLoad Blocks fields.

Using these properties on the receiving side, the quality of demodulation is improved by estimating the frequency and phase of the signal, symbol rate, signal-to-noise ratio, etc., using known parameters. In addition, establishing and maintaining communication is easier and more reliable when the signal parameters transmitted in the Header field are known.

The principle of transmitting additional service information in a reliable information container also makes it possible to implement adaptation in the transmission speed of user data depending on reception conditions.

Structurally, the SFOS hardware platform is implemented on six separate boards (Fig. 4).

The DSP and control modules for the receiving and transmitting paths are two independent Xilinx Virtex-7 boards, each containing up to two million logical cells, with an internal exchange rate of up to 2.8 Tb/s.

ADC 10 and DAC 11 boards for the receiving and transmitting paths are two independent 16-bit FMC144 boards measuring 85x60 mm, allowing up to four independent channels with a conversion speed of 370 Msps for the ADC and 2.5 Gsps for the DAC.

Thus, the signal generation and processing system provides improved information reception in conditions of signal fading as it propagates over a radio channel, as well as compensation for interference and adaptation in frequency.

Claims (1)

A system for generating and processing radio signals in the short-wave range, made in the form of two modules, the first module being a four-channel analog-to-digital converter (ADC), which contains a low-pass filter (LPF), a digitally controlled amplifier, a band-pass filter (PF), an analog-to-digital converter and a reference oscillator, with a low-pass filter connected in series with a digitally controlled amplifier, a filter filter and an ADC, the second module is a digital signal processing and control unit, which includes a digital computer consisting of a digital signal processor and a processor core, while The digital computer is connected by its inputs to the ADC, and by its output to an interpolating digital-to-analog converter, which is connected to a reference oscillator, and the digital computer is connected to user interfaces and through a power amplifier to the receiver, while four analog-to-digital converters are configured to operate synchronously from one master generator and the ability to select a conversion frequency in the range from 65 to 250 MHz for operation in the main Nyquist window, while this architecture is designed with the ability to receive radio signals from four different antennas simultaneously to build a radio receiver and the ability to use adaptive processing algorithms.

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