RU2629655C2 - Manufacturing method of semiconductor structure - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: in the manufacturing method of semiconductor structure, a p-type silicon wafer with orientation (100) is oxidized in an atmosphere of dry oxygen, then phosphorus ions are implanted with an energy of 100-115 keV, a dose of 1*10¹⁵ cm^-2, followed by annealing at 1150°C under a nitrogen atmosphere with formation in the substrate of the n⁺-type conductivity region with a surface impurity concentration of 1*10¹⁹ cm^-3. Then a polysilicon layer is deposited on the surface of the plate and the plate is scanned with an Ar-laser beam with a power of 5-10 W at a speed of 90-100 cm/s in a direction perpendicular to the seed path, resulting in local melting of the polysilicon followed by crystallization of the epitaxial layer. After the epitaxy process, the protective SiO₂ layer is removed and a field-effect transistor is formed using standard technology.

EFFECT: reduced flaw density, improved fabricability, instrument parameters and quality, increased percentage yield of serviceable devices.

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Description

The invention relates to the field of technology for the production of semiconductor devices, in particular to a technology for manufacturing a semiconductor structure of silicon on a dielectric with a low density of defects.

A known method of creating a structure of silicon on a dielectric [US Patent 5061642, MKI H01 L 21/477] by implanting O ₂ through a substrate to form an intermediate layer, then annealing the substrate in an atmosphere of nitrogen N ₂ , in each cycle of which temperatures are alternately alternating at 1100 ° C and 500 ° C. The cycle time is one minute, the number of cycles is 10. As a result, a SiO ₂ layer forms under the silicon layer. In such structures, due to the large number of thermal cycles, defectiveness increases and the parameters of the devices deteriorate.

A known method of manufacturing a structure of silicon on a dielectric [US Patent 5143862 USA, MKI H01 L 21/76] on a plate of single-crystal silicon using epitaxy. Using a combination of anisotropic deposition of SiO ₂ and isotropic etching create a structure with layers of SiO ₂ only on horizontal surfaces, including areas of previously created grooves. After that, using selective epitaxial deposition of Si, the grooves are filled to the level of the lower surface of the SiO ₂ mask, while epitaxial growth begins on the walls of the grooves free of SiO ₂ . Then repeat the process of selective epitaxial deposition of Si to the surface level of the mask of SiO ₂ . A thin oxide layer is grown on epitaxial Si, anisotropic etching of epitaxial Si is carried out through the windows to the SiO ₂ layer hidden beneath epitaxial Si, and these deep narrow windows are grown by thermal oxidation. As a result, the epitaxial regions turn out to be completely isolated (from below and from the sides) by the oxide from the substrate.

The disadvantages of this method are:

- increased density of defects;

- low manufacturability;

- significant leakage currents.

The problem solved by the invention: reducing the density of defects, ensuring manufacturability, improving parameters, improving quality and increasing the percentage of suitable products.

The problem is solved by creating an n ⁺ region in the Si wafer by implanting phosphorus ions with an energy of 100-115 keV, a dose of 1 * 10 ¹⁵ cm ^-2 , followed by annealing at a temperature of 1150 ° C in a nitrogen atmosphere, with deposition of a polysilicon layer and scanning of the wafer surface with an Ar beam 5-10 W laser with a speed of 90-100 cm / s.

The technology of the method consists in the following: a p-type silicon wafer with an orientation of (100) was oxidized in an atmosphere of dry oxygen, then phosphorus ions with an energy of 100-115 keV, a dose of 1 * 10 ¹⁵ cm ^-2 were implanted, followed by annealing at a temperature of 1150 ° C in a nitrogen atmosphere with the formation of an n ⁺ -type region in the substrate, with a surface impurity concentration of 1 * 10 ¹⁹ cm ^-3 . A window in the form of a track was opened in the oxide, while the exposed surface of the plate served as a seed region. A polysilicon layer was deposited on the wafer surface and a SiO ₂ layer was formed. Then, the wafer surface was scanned by an Ar laser beam with a power of 5-10 W at a speed of 90-100 cm / s in the direction perpendicular to the seed track, which resulted in local fusion of polysilicon followed by crystallization of the epitaxial layer. After the epitaxy process, the protective SiO ₂ layer was removed and the field effect transistor was formed using standard technology.

According to the proposed method, semiconductor structures were manufactured and investigated. The results are shown in the table.

Experimental studies have shown that the yield of suitable semiconductor structures on a batch of wafers formed in the optimal mode increased by 20.5%.

Effect: reducing the density of defects, ensuring manufacturability, improving parameters, improving quality and increasing the percentage of yield.

The stability of the parameters over the entire operating temperature range was normal and consistent with the requirements.

The proposed method for manufacturing a semiconductor structure by creating an n ⁺ region in the Si wafer by implanting phosphorus ions with an energy of 100-115 keV, a dose of 1 * 10 ¹⁵ cm ^-2 , followed by annealing at a temperature of 1150 ° C in a nitrogen atmosphere, with the deposition of a polysilicon layer and scanning The surface of the wafer with an Ar laser beam of 5–10 W power at a speed of 90–100 cm / s makes it possible to increase the yield rate and improve their quality.

Claims (1)

A method of manufacturing a semiconductor structure, including a silicon wafer, silicon dioxide, epitaxial growth and etching processes, characterized in that the semiconductor structure is formed by creating an n ⁺ -type region with a surface impurity concentration of 1 * 10 ¹⁹ cm ^{-3 by} implantation of phosphorus ions with an energy of 100-115 keV, a dose of 1 * 10 ¹⁵ cm ^-2 followed by annealing at a temperature of 1150 ° C in a nitrogen atmosphere, with the deposition of a polysilicon layer and scanning the surface of the plate with an Ar laser beam of 5-10 W power at a speed of 90-100 cm / s.