RU2611552C2 - Photodetector (versions) and production method thereof - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: invention relates to semiconductor electronics, in particular to production of structures of photoelectric receiving device (PRD), intended for conversion of optical radiation of a certain spectral range into an electric signal. Method of making a photodetector (PD) by forming on a substrate a topological pattern of photosensitive elements, anode and cathode areas, creation of metallization and passivating coating and contact pads, cutting and assembling photodetector chip in a housing, to ensure resistance of photodetector to dose effects and transient processes of ionising radiation substrate material used is a silicon-on-sapphire (SOS) hetero-epitaxial structure (HES) with thickness of epitaxial silicon layer of 5 mcm, n-type conductivity with specific resistance of 4.5 ohm⋅cm to 10 ohm⋅cm and concentration of main impurities of not less than 10¹⁵ cm^-3. In photodetector, formed by electric serial, parallel or serial-parallel connection of elementary diodes, to provide resistance to transient processes from effect of pulsed ionising radiation, topological layers are formed on SOS technology HES with thickness of epitaxial silicon layer 5 mcm, n-type conductivity with specific resistance of 4.5 ohm⋅cm to 10 ohm⋅cm, with concentration of main impurities of not less than 10¹⁵ cm^-3 and applied on opposite side of HES layer of polycrystalline silicon, and structures of elementary diodes are formed in order of alternation from bottom-up topological layers: "the active region", "n-pocket", "anode", "cathode", "metal", "passivation".

EFFECT: method of producing radiation-resistant optical radiation receiver (photodetector or detector) on silicon diode structures of "silicon-on-sapphire" (SOS) technology and its implementation.

36 cl, 15 tbl, 33 dwg

Description

The invention relates to the field of semiconductor electronics, in particular, to methods for manufacturing structures of photovoltaic receiving devices (FPUs) for converting light radiation of a specific spectral range into an electrical signal.

The most common solid-state photoelectronic products designed to convert optical signals into electrical signals are semiconductor photodiodes (PD). By the mechanism of action and parameters, they approach ideal photon-to-electron converters and have significant advantages over other types of photodetector devices (FPUs).

Radiation detectors (DIs) are referred to as converters of the energy of incident photons into the energy of electrical carriers or, more simply, into electrical signals (current or voltage). There is a wide variety of MDIs that differ in physical basis, hardware implementation, and functional characteristics. Each electro-optical system needs detectors that are optimally suited for special applications.

Typically, used MDIs can be classified as follows [1]:

(a) detectors of generated signals of physical processes:

- electro-optical detectors, including:

- individual (single) electro-optical cells;

- photoelectric multipliers (PMTs);

- semiconductor detectors (photoresistors);

- photovoltaic detectors (photodiodes);

- thermal detectors (bolometers);

(b) by the number of detectors in the common housing, including:

- single detectors;

- detector matrices:

- line of detectors (one-dimensional arrays);

- areal detectors (two-dimensional arrays).

Existing optical sensors of various varieties and configurations are not represented in the above classification - here are just some of the most famous radiation detectors.

The disadvantage of many of them is the insufficient level of radiation resistance to the effects of disordering (DD = Displacement Damage) from neutrons and protons, effects of the total absorbed dose (TID = Total Ionizing Dose) of gamma-ray radiation (γ-X-Ray), transient processes from these types of ionizing radiation (TREE = Transient Radiation Electrical Effects).

Phototransistors and laser diodes (LD) possess the least resistance to ionizing radiation (IR), which limits their use in FPUs and optical optical isolation circuits, such as optocouplers.

In FIG. 1 is a schematic representation of a photoconductive detector. To form the output signal, a load resistor is included in the photovoltaic FPU circuit (Fig. 2). In FIG. 3 (a) shows the incident time-rectangular δ-pulse of photon radiation with energy E _λ , in FIG. 3 (b) - the resulting current pulse from exposure to pulsed incident photon radiation.

Currently, in some cases, the so-called 3D vertical technology is used for modern semiconductor radiation sensors and readout electronics (PSiSE) [2]. The use of 3D vertical integration for PSiSE brings certain advantages for pixel semiconductor (PP) radiation sensors in "front-end" (cutting-edge) scientific experiments with high emissivity of particle accelerators and modern x-ray sources. These experiments impose very stringent requirements on the functioning of sensors and output electronics in terms of pixel pitch (display element), radiation resistance, signal-to-noise ratio, and high-intensity data transmission bandwidth. 3D vertical integration of two or more layers of sensors and devices of the technology “complementary metal-oxide-semiconductor” (CMOS) usually forces developers to stretch the formation process at the pixel level functionally and achieve a non-standard structure, where each layer is designed to implement specific functions.

In any case, modern integrated microelectronics plays a very important role for the development of pixel sensors for commercial information display applications. The functioning of the display devices is increased to a greater extent by connecting two or more layers with CMOS technology sensors and associated signal output electronics, which are coated with tin on the inverse side to increase reflection and are tiled to obtain a larger viewing area while eliminating the dead zone [3]. In recent years, as a result of research, it was found that 3D integration makes it possible to obtain advantages in the operation of a bunch of semiconductor radiation detectors in future experiments with high-energy particle accelerators [4]. In these applications, the fundamental problem is equipping the track of heavy charged particle (TLC) output with high resolution pixel sensors. These sensors, together with the signal output electronics, are required to reduce the pixel pitch (≤20 μm for these applications), a high degree of radiation resistance (PC), a large signal-to-noise ratio, minimum mass to reduce particle scattering, and low electrical dissipation power and ability to transmit high-intensity information. Along with the requirements for such applications, additional requirements are formulated for a unit cell covering each pixel from above in terms of signal-to-noise ratio and information transfer intensity. These functions include amplification, filtering, calibration, adjustment of the discrimination threshold, analog-to-digital conversion, compensation for zero level drift (also called “supporting” measures = sparspecification). 3D integration can solve the problems of integrating all these functions in one small pixel, avoiding the aggressive scaling of CMOS technology below the technological size of 100 nm [5], which is very expensive and unsuitable for developers of analog circuits.

In the future, two general research areas and technical solutions for the application of 3D vertical integration in high-energy physics were implemented. The first was considered as a classic concept of MAPS (Monolitic Active Pixel Sensors) CMOS technology for the generation of a charge signal and its collection in the depleted region of silicon. In this case, the vertical sensor of two (or more) layers of the CMOS technology is able to separate the front-fall analog electronics from the digital information output electronics, giving tangible advantages in pixel part sizes, functionality and performance. A differential output electronics architecture was developed to control a large data stream without the restrictions that appear if the digital part of the electronics was embedded in the same substrate as the sensor (as in the standard MAPS).

The second line of research probed the possibility of using 3D integration to combine layers made using various technologies, i.e. they connected the sensor constructions with a fully depleted high-resistance silicon substrate of the output electronics manufactured by the deeply submicron CMOS technology. This provides significant advantages in terms of radiation resistance and signal-to-noise ratio. Excluding track fixation (trecking) in experiments on high-energy physics, this technology was also used to fix the X-Ray distribution of such modern sources as XFEL (X-Ray Federal Electronic Laboratory, USA).

     3D vertical integrated technology is considered extremely promising in the design of MAPS. In the standard MAPS, which integrates poorly with the promotion of functioning in pixel cells, because eliminates the use of structures of p-type field-effect transistors (P-MOSFETs = P-Type-Metall-Oxid-Semiconductor Field Effect Transistors), instead of which they use locally connected N-type pockets that are equipped for collecting charge and signal electrodes (also N- type) and reduce the utilization rate. Multilayer sensor structures (coupled to a thin film with a vertical through jumper) can eliminate these typical MAPS limitations. In 3D MAPS devices, for example, the film can be made in the form of a main sensitive electrode and an analog circuit, while digital electronics are placed on the top film. In this case, they exclusively use CMOS technology electronics in a pixel cell, where most (and not all) P-MOSFETs and competing N-pockets are moved from the sensor film, reaching, in principle, 100% utilization. The multi-film structure reduces pixel pitch and sensor capacitance, allowing you to get the best compromise between noise level and power dissipation.

The VIPIX (Very Integrated Pixels) project planned to use 3D integration in MAPS with deep pockets of n-type conductivity (Deep N-Well = DNW)) [6]. In the pixel cell of this device, the charge collecting electrode was made in the form of a DNW structure, which is accessible to many CMOS processes. The electrodes were placed on top of an extended portion of the cell area. On this path, most of the analog and digital blocks are used in a pixel, which provides that the area of the standard structure of the N-pocket containing the structure of P-MOSFETs does not coincide with the DNW electrode with which it is equipped to collect the charge. 3D-ralization promises to receive a number of additional advantages for this type of instrument family: 1) most (but not all) P-MOSFETs structures with which N-pockets compete are moved from the film where sensitive sensors are placed, improving charge collection efficiency; 2) it becomes possible to increase the complexity and functionality of output electronics during operation of multi-film device structures [7]. For the VIPIX project, at the first stage in the direction of 3D development, a two-level DNS MAPS was developed with “one-on-the-other” communication of two heteroepitaxial structures (HES) of CMOS technology with design standards of 130 μm, made using the Tezzaron Semiconductor vertical integrated process [8]. This so-called through middle hole is close to 3D integration, where through holes through silicon (Trough-Silicon Vias = TSVs) for vertical bonding are carefully etched in CMP CMOS technologies after the stages of manufacturing transistors. High density TSVs (in increments of several microns) can be realized using this kind of process.

The main disadvantage of 3D technology sensors is the technological complexity of its reproduction.

In addition to AI sensors, FPUs for detecting laser radiation (LI) and microwave radiation were widely used [9]. The main sensors used are avalanche diodes (Impact Ionization Avalanche Transit Time = IMPATT), avalanche-span diodes (Trapped Plasma Avalanche Transit Time = TRAPATT), MOSFET technology structures and transistor oscillators. The control procedure for these emissions is as follows: the photosensitive material is illuminated with a photon source; incident radiation is absorbed in a given spectral range by sensitive layers; generate free charge carriers.

FPUs on GaAs are known to be of the p ⁺ -ni (AROC) -n ⁺ structure [10], in which an antireflecting Optical Coating = AROC i-layer is formed to reduce the intrinsic capacitance of the FPU, increase the electric field strength and the avalanche coefficient multiplication of charge carriers, which, in general, helps to increase speed and increase the amplitude of the voltage of the output pulse. In FIG. Figure 4 shows (c) the zone-energy diagram, (d) the AC voltage, (e) the injection and impurity currents [9]. Having a high level of resistance to the disorder effects (DD) of the crystal lattice of PP material from neutron and proton radiation due to the presence of a high-resistance i-layer of its own type of conductivity, these devices are highly sensitive to TREE effects, which manifest themselves as additive parasitic RIT leakages.

The closest technical solution, which is taken as a prototype, is an FPU optocoupler 66212 at a wavelength of 850 nm by Micropac Industries, Inc., which is implemented as a phototransistor detector, which, together with an optically coupled light emitting diode (LED) (LED = Light Emitting Diode), made using the GaAlAs technology with a wavelength of 850 nm in the form of a pin structure, and the GaAsAl structure is mounted in a sealed 4-pin lead-free crystal holder (LCC = Leadless Chip Carrier) [11]. To study structural damage (DD = Displacement Damage) due to degradation from the effects of the total absorbed dose (TID) on the proton beam accelerator LBNL BASE (Lowrence Berkeley National Laboratory / Berkeley Accelerator Space Effects) in June 2010 conducted tests. The current transfer coefficient (CTR = Current Transfer Ratio) of the amplifier was controlled as a function of proton fluence when measuring the output current I _CE depending on the forward current I _F. The devices were irradiated with electric displacement. When irradiated with a fluence of up to 2 × ^{10 12} proton / cm ² with an energy of 50 MeV, CTR degradation was observed for all tested devices. 90/99% confidence limits were calculated based on a simple standard deviation and one-dimensional confidence limits. A decrease in CTR from these specifications was observed between fluences of 4 × 10 ¹¹ proton / cm ² and 8 × ^{10 11} proton / cm ² at a voltage of V _CE = 1 V, as shown in FIG. 5. The CTR value is normalized to the maximum average peak CTR value before irradiation, which at V _CE = 1 V was 8.9.

The disadvantage of [11] is the lack of data on the resistance of the FPU and the optocoupler in general to TREE effects.

The technical result is the development of a method for manufacturing a radiation-resistant optical radiation detector (photodetector = FPU or detector) on silicon diode structures of the silicon-on-sapphire (SSC) technology and its implementation.

The technical result is achieved by the fact that in the method of manufacturing a photodetector (FPU) by forming on the substrate planar layers of the FPU and the topological pattern of the photosensitive elements, regions of the anode and cathode, creating metallization and passivating coatings and contact pads, cutting and assembling the FPU crystal in the housing as The substrate material uses heteroepitaxial structures (HES) of the silicon-on-sapphire (SSC) technology with an epitaxial silicon layer thickness of 5 μm, n-type conductivity with specific resistivity a phenomenon from 4.5 Ohm⋅cm to 10 Ohm⋅cm and a concentration of the main impurity of at least 10 ¹⁵ cm ^-3 .

In addition, a layer of polycrystalline silicon is applied to the inverse side of the hydroelectric power station.

In addition, the formation of the boundaries of individual photosensitive elements (PSEs) is performed by etching grooves along the perimeter of the PSE to the entire depth of the epitaxial silicon layer.

In addition, the etching of the grooves is carried out by deep plasma-chemical etching of silicon on a photoresist mask.

In addition, the formation of a topological pattern of the working layers of the anode and cathode region is carried out by contact photolithography with the need to combine the photolithography (PL) of the p-anode and n-cathode.

In addition, when the regions of the p-anode and n-cathode are formed, the epitaxial silicon film is first oxidized to a depth of 0.3 μm, and then films of silicon dioxide (SiO ₂ ) and silicon nitride (Si ₃ N ₄ ) are deposited by plasma-chemical deposition.

In addition, when forming the regions of the p-anode and n-cathode, photoluminescence is performed by opening an oxidized silicon epitaxial film (SiO ₂ + CVDSiO ₂ + Si ₃ N ₄ ).

In addition, during the formation of the p-anode regions, boron ions are implanted, ion energy E = 40 keV, dose D = 500 μClcm ^-2 , through a buffer oxide using a photoresist mask.

In addition, when forming regions of the n-cathode, phosphorus ions are implanted, ion energy E = 40 keV, dose D = 800 μClcm ^-2 , through a buffer oxide using a photoresist mask.

In addition, the resulting structure is annealed at temperatures from 850 to 950 ° C.

In addition, they choose the optimal ratio of the parameters of the technological processes of ion implantation - the dose of ions and the energy of ions and high-temperature annealing in the temperature range from 850 to 950 ° C.

In addition, an annealing process is performed with afterburner — a gradual increase in temperature, double annealing: 10 min in a nitrogen atmosphere at 850 ° C and 10 min in a nitrogen atmosphere at 950 ° C.

In addition, when creating metallization, an aluminum alloy with 1% silicon 1.0 μm thick is first sprayed by magnetron sputtering.

In addition, when forming a metallization pattern, a photocopying operation (PC) is performed, and then plasma-chemical etching (PCT) of aluminum and liquid etching of silicon chips are performed.

In addition, when creating metallization perform the operation of "burning metal" at a temperature of T = 450 ° C for 15 minutes in an atmosphere of dry nitrogen.

In addition, when creating a passivating coating of the PSE regions, a 1.0-μm thick FSS layer is deposited with a phosphorus content of 3% to 5%.

In addition, when creating metallization, including the formation of contact pads, the contact pads are opened by means of passivation FC and subsequent chemical etching of the FSS.

In addition, a test ruler containing a set of test elements is introduced into the structure of the FPU:

a resistor with a working area made on the area of the anode;

a resistor with a working region made on the cathode region;

single diode of a small area;

single diode of a small area, limited by a "groove";

three and ten parallel-connected diodes, limited by a "groove";

three and ten parallel-connected diodes, not limited to the "groove".

In addition, test resistors are made in the layers of the anode and cathode in the active region.

In addition, two types of test diodes are performed for the anode with the dimensions of an elementary diode 50 × 50 μm.

In addition, to control the quality of the formation of planar layers of the FPU, in the field of the crystal (chip) of the FPU, controlled elements and layer identifiers are introduced.

In addition, to symbolize the test resistors in the metallization layer, the symbol “R _K ” is performed for the resistor in the cathode layer, and the symbol “R _A ” is performed for the resistor in the anode layer.

In addition, to control the electrophysical parameters of the FPU, measurements are used by the probe station on test structures and on working crystals.

In addition, to separate the plates into crystals (chips), FPUs use the disk cutting method using a diamond-coated circular saw with a saw edge thickness of 0.036 mm while supplying deionized water.

In addition, the cutting depth is carried out to a depth of 2/3 to 3/4 of the thickness of the plate.

In addition, the FPU is placed in metal-glass cases.

The technical result is achieved by the fact that in the photodetector formed by an electrical serial, parallel or serial-parallel connection of elementary diodes, topological layers are formed at HPS technology of SPS with an epitaxial silicon layer thickness of 5 μm, n-type conductivity with a resistivity of 4.5 Ohms or more ⋅cm to 10 Ohm⋅cm, with a concentration of the main impurity of at least 10 ¹⁵ cm ^-3 and a layer of polycrystalline silicon deposited on the inverse side of the HES, and the structures of elementary diodes are formed in the order of alternating bottom-up topological layers: “active region”, “n-pocket”, “anode”, “cathode”, “metal”, “passivation”.

In addition, elementary diodes are isolated between each other through the “grooves” of a width of 20 μm through the sapphire layer.

In addition, the contact pads of elementary diodes are displayed outside the "grooves".

In addition, each of the elementary diodes is connected to the other pads from the diode matrix in the amount of 8 pieces, located uniformly on the periphery of each of the elementary diodes.

In addition, the contact pads are formed from top to bottom from passivation-metal layers.

In addition, the width of the exposed passivation region is 130 μm.

In addition, a test line with a set of test elements has been introduced into the FPU:

a resistor with a working area made on the area of the anode;

a resistor with a working region made on the cathode region;

single diode small area;

a single diode of a small area limited by a "groove";

three and ten parallel connected diodes, limited by a "groove";

three and ten parallel connected diodes, not limited to the "groove".

In addition, the test elements introduced into the field of the crystal (chip) of the FPU in the main design layers are formed with the dimensions:

in the layer "active region" 6.0 microns;

in the n-pocket layer, 2.6 μm;

in the layer "anode" 6.0 microns;

in the cathode layer 6.0 microns;

in the metallization layer 4.0 microns;

in the layer “passivation” is not controlled.

In addition, in a photodetector formed by electrical parallel connection of elementary diodes, twenty elementary diodes are connected in a group in parallel with the total size of one photosensitive element (PSE) (1.40 ± 0.01) × (1.40 ± 0.01) mm ² , while the size of the elementary diode is 68.0 × 1440.7 μm ² .

In addition, in the photodetector formed by electric series-parallel connection of elementary diodes, the FPU is made in the form of left and right PSEs, each of which contains twenty elementary diodes connected in a group in parallel.

The invention is illustrated by the following illustrations:

FIG. 1. Schematic representation of a photoconductive detector:

E is the photon energy flux;

R _L - load resistance;

V _L is the output signal of the detector;

a, b, h - length, width and height of the chip.

FIG. 2. The inclusion circuit of the load resistor.

FIG. 3. The resulting signal from the influence of pulsed incident radiation: a) a decreasing rectangular in time δ-pulse of photon radiation with energy E _λ ; b) the pulse of the output current of the detector (τ _Rise is the rise time of the leading edge of the pulse; τ _Fall is the fall time of the trailing edge of the pulse).

FIG. 4. (a) is the structure of the real diode p ⁺ -nin *, (b) is the electric field in the avalanche region, (c) is the band-energy diagram, (d) is the alternating current voltage, (e) is the injection and impurity currents [9].

FIG. 5. CTRs Mii 66212 as a function of input current and proton fluence as a parameter. CTRs show the average value for all tested devices. For all data, V _CE = 1 B [11]: X - Input Forward Current (A) - input current (A); Y - Normalized CTR - normalized current gain.

FIG. 6. The stage of opening areas for the formation of the p-anode and n-cathode.

FIG. 7. The stage of formation of the regions of the p-anode.

FIG. 8. The stage of formation of the regions of the p-anode and n-cathode.

FIG. 9. The stage of metallization formation.

FIG. 10. The stage of formation of passivation.

FIG. 11. Diagram of the unloading of the crystal of 2D301S-01 photodiodes (left) and 2D301S-02 (right) into the KT-2 type housing: 1. Anode left; 2. The cathode is left; 3. The cathode is right; 4. The anode is right.

FIG. 12. An example of the implementation of the "grooves".

FIG. 13. The appearance of the topology of the FPU.

FIG. 14. The topology of the test elements.

FIG. 15. View of the elementary photosensitive element of the PSE: (a) - a schematic representation of the elementary PSE; (b) - topology of elementary PSE.

FIG. 16. Configuration of controlled elements.

FIG. 17. An example of the withdrawal of the contact pad beyond the boundaries of the insulating "grooves": (a) - withdrawal of metallization outside the area bounded by the "grooves"; (b) - execution of contact pads outside the area limited by “grooves”.

FIG. 18. Layer IDs.

FIG. 19. The impulse current characteristics of single-element FPUs at an optical pulse repetition rate of 100 kHz.

FIG. 20. The impulse current characteristics of single-element FPUs at an optical pulse repetition rate of 1 MHz.

FIG. 21. The impulse current characteristics of two-element FPUs at a pulse repetition rate of 100 kHz.

FIG. 22. The impulse current characteristics of two-element FPUs at an optical pulse repetition rate of 1 MHz.

FIG. 23. Comparative results of measuring threshold power on single 2D301S-01 photodiodes of two technologies.

FIG. 24. The layout of the controlled points on the plate.

FIG. 25. The results of studies at the bench for laser studies of FPU parameters on silicon structures:

- below shows a laser pulse;

- The dark current response is shown at the top.

FIG. 26. The results of studies at the bench for laser studies of FPU parameters in the structures of the SSC:

- below shows a laser pulse;

- the dark current response is shown at the top

FIG. 27. The waveform of the signals at the FPU output when exposed to a radiation pulse from the LIU-10M installation (imp. No. 4361, C1 - FPU KNS No. 17, legal., C2 - FPU KNS No. 17, left., C3-FPU Si No. 13, right. , C4 - FPU Si No. 13, lion.).

FIG. 28. The waveform of the signals at the FPU output when exposed to a radiation pulse from the LIU-10M installation (imp. No. 4364, M2 - FPU Si No. 10, M3 - FPU KNS No. 4, M4 - FPU Si No. 11).

FIG. 29. The waveform of the signals at the output of the FPU when exposed to a radiation pulse from the Argument-1000 installation (imp. No. 1, M2 - FPU Si No. 10, M3 - FPU KNS No. 4, M4 - FPU Si No. 11).

FIG. 30. The waveform of the signals at the output of the FPU when exposed to a radiation pulse from the GIR-2 installation (imp. No. 1, C1 - FPU KNS No. 3, C2 - FPU Si No. 10, C3 - FPU KNS No. 4, C4 - FPU Si No. 11).

FIG. 31. The waveform of the signals at the output of the FPU when exposed to a radiation pulse from the GIR-2 installation (imp. No. 2, C1 - FPU KNS No. 1, C2 - FPU Si No. 8, C3 - FPU KNS No. 2, C4 - FPU Si No. 9).

FIG. 32. Change in the output voltage of FPU-KNS-1 No. 1, 2 and FPU-Si-1 No. 8, 9 in the process of exposure to a factor with characteristic 7. And ₇ .

FIG. 33. Changing the output voltage of FPU-KNS-2 No. 5 and FPU-Si-2 No. 12 in the process of exposure to a special factor with characteristic 7.I ₇ .

Concrete implementation example

A photodetector, in which a topological pattern of PSE is formed on the substrate material, anode and cathode regions are formed, metallization, a passivating coating and contact pads are created. The formed FPU chips at the initial hydroelectric power station are subjected to cutting and subsequent assembly of the scribed FPU chip into the housing. To ensure the FPU resistance to dose effects and transition processes of ionizing radiation (TREE), HPS technologies with an epitaxial silicon layer thickness of 5 μm, silicon type conductivity with a resistivity of 4.5 to 10 Ω⋅cm and a concentration of the main impurity are used as the substrate material not less than 10 ¹⁵ cm ^-3 .

To compensate for mechanical stresses at the interfaces between the layers of the hydroelectric station, SPS technologies apply a layer of polycrystalline silicon to the inverse side of the hydroelectric station.

To form the boundaries of individual PSEs along the entire depth of the epitaxial silicon film (Fig. 12), "grooves" are formed.

To implement the process of deep plasma-chemical etching of silicon grooves, the process of deep etching is carried out using a photoresist mask (FR).

The list of the main design layers is given in table. one.

The formation of the topological pattern of the working layers was carried out by contact photolithography with the need to combine photolithography (PL) of the p-anode and n-cathode (Fig. 13).

To form the regions of the p-anode and n-cathode, the epitaxial silicon film is first oxidized to a depth of 0.3 μm, then SiO ₂ and Si ₃ N ₄ films are deposited by CVD.

To form the regions of the p-anode and n-cathode, photoluminescence is performed by opening an oxidized epitaxial silicon film (SiO ₂ + CVDSiO ₂ + Si ₃ N ₄ ) (Fig. 6).

To form regions of the p-anode, boron ions are implanted (ion energy E = 40 keV, dose D = 500 µC⋅cm ^-2 ) through a buffer oxide using a photoresist mask (Fig. 7).

To form n-cathode regions, phosphorus ions are implanted (ion energy E = 40 keV, dose D = 800 µC⋅cm ^-2 ) through a buffer oxide using a photoresist mask.

In order to disperse an impurity, when the complete electrical activity of the impurity is achieved without significant diffusion of impurity atoms, the resulting structure was annealed at a temperature of 850–950 ° С (Fig. 8).

To obtain low values of dark current (not more than 0.05 μA) and sufficiently high values of current sensitivity (not less than 0.4 A / W), the optimal ratio of the parameters of the processes of ion implantation processes (ion dose and ion energy) and high-temperature annealing in the range 850-950 ° C. To take into account the differences in the coefficients of thermal expansion of the materials of layers of hydroelectric power stations, KNS technologies implement an annealing process with afterburner (a gradual increase in temperature), double annealing: 10 min in N ₂ atmosphere at 850 ° С and 10 min in N ₂ atmosphere at 950 ° С. In the table. Figure 2 shows the annealing modes for the initial HES with different values of the specific resistivity of silicon.

Based on the analysis of the data obtained, we can conclude that there are differences in the parameters of the FPU manufactured by various technologies, such as dark current and current sensitivity. From the data table. 2, it follows that FPUs made on silicon wafers have better characteristics, which is due to the features of the technology for producing epitaxial layers of single-crystal silicon in the manufacture of structures of the SSC technology. These features include increased defectiveness of films compared to bulk silicon, as well as the influence of internal mechanical stresses arising from the growth of 5 μm thick semiconductor films.

The results obtained demonstrate the absence of a direct dependence of the current sensitivity on the depth of the pn junction. The specific resistance of the initial structures contributes to a decrease in the level of current sensitivity.

To form a metallization pattern, a photocopying operation (PC) is performed, and then plasma-chemical etching (PCT) of Al and liquid etching of silicon chips are performed (Fig. 9).

To reduce the resistance of metal contacts, before the deposition of the FSS, the operation is “burning metal” at a temperature of T = 450 ° C for 15 minutes in an atmosphere of dry N ₂ .

To passivate the manufactured devices, a FSS layer was deposited with a thickness of 1.0 μm with a phosphorus content of 3 to 5%.

To form the contact pads, the contact pads are opened by means of FC passivation and subsequent chemical etching of the FSS (Fig. 10).

To form metallization, an Al alloy with 1% Si 1.0 μm thick is first sprayed by magnetron sputtering.

To control the technological operations of the formation of the FPU structure, a test ruler containing a set of test elements (Fig. 14) was introduced into its composition: a resistor with a working area made on the anode area; a resistor with a working region made on the cathode region; single diode of a small area; single diode of a small area, limited by a "groove"; three and ten parallel-connected diodes, limited by a "groove"; three and ten parallel-connected diodes, not limited to the "groove".

To determine the resistance of the FPU layers, test resistors are made in the layers PPlus (anode) and NPlus (cathode) in the active region.

To control the quality of the etching processes of the interlayer dielectric, metal and evaluate the performance of the FPU, two types of test diodes are performed for the anode with the dimensions of an elementary diode 50 × 50 μm (Fig. 15).

To control the quality of the formation of planar layers of the FPU in the field of the crystal (chip) of the FPU introduce controlled elements and layer identifiers. The configuration of the monitored elements is shown in FIG. 16. The sizes of the controlled elements are given in table. 3.

For the designation of test resistors in the Metall 1 layer, the symbol “R _K ” is performed for the resistor in the NPlus layer (cathode), and the symbol “R _A ” is performed for the resistor in the PPlus layer (anode).

To control the FPA, FPUs use measurements by a probe station on test structures and on working crystals.

To separate the plates into crystals (chips), FPUs use the disk cutting method using a diamond-coated circular saw with a saw edge thickness of 0.036 mm while supplying deionized water.

To optimize the depth of cutting it is carried out to a depth of 2/3 to 3/4 of the thickness of the plate.

For gluing chips in FPU cases, conductive glue is used, for example, TOK-2.

To ensure the passage of the light flux to the front surface of the FPU, they are placed in metal-glass cases similar to the cases of the FD-20-31 FGCE3.368.103TU or FD-20-33L AGTs.3.368.120TU photodiodes.

FPU formed by electrical serial, parallel or serial-parallel connection of elementary diodes (Fig. 15), in which to form the structure of an elementary diode topological layers are formed in the order of alternation from the bottom up: “active region” (Active (9)), “n- pocket) (Nwell (19)), P ⁺ drains (“anode”) (PPlus (51)), N ⁺ drains (“cathode”) (NPlus (54)), “metallization” (Metall (70)) Passivation (Ovgl (92)).

To ensure resistance to transients from pulsed ionizing radiation (TREE), topological layers are formed at hydroelectric power station technology of SPS with an epitaxial layer thickness of 5 μm, n-type conductivity with a resistivity of 4.5 to 10 Ohm⋅cm, with a concentration of the main impurity not less than 10 ¹⁵ cm ^-3 and a layer of polycrystalline silicon deposited on the inverse side of the HES.

To ensure electrical isolation, elementary diodes are isolated between each other through the “grooves” of 20 microns wide through the sapphire layer (Fig. 12).

To ensure contact conditions, the contact pads are outside the "grooves" (Fig. 17).

To ensure the connection of each of the elementary diodes on the periphery with the other of the diode matrix, the contact pads in the amount of eight pieces are located evenly on the periphery of each of the elementary diodes.

In order to protect the contact pads from adverse operating conditions, the contact pads are formed from top to bottom from the passivation - metallization layers.

To ensure electrical connection of the contact pads of adjacent elementary diodes, the width of the opened passivation region is 130 μm.

To control the technological operations of the formation of the FPU structure, a test ruler with a set of test elements was introduced into its composition (Fig. 14): a resistor with a working area made on the anode area; a resistor with a working region made on the cathode region; single diode of a small area; single diode of a small area, limited by a "groove"; three and ten parallel-connected diodes, limited by a "groove"; three and ten parallel-connected diodes, not limited to the "groove".

To control the quality of formation of planar FPU layers, the introduced controlled elements (Fig. 16) introduced into the field of the crystal (chip) of the FPU (Fig. 16) are formed in the main design layers with dimensions: in the "active layer" 6.0 microns; in the n-pocket layer, 2.6 μm; in the layer "anode" 6.0 microns; in the cathode layer 6.0 microns; in the metallization layer 4.0 microns; in the layer “passivation” is not controlled.

FPU formed by electrical parallel connection of elementary diodes, in which to increase the current sensitivity of the entire device as a whole twenty elementary diodes are connected in a group in parallel with the total size of one PSE (1.40 ± 0.01) × (1.40 ± 0.01) mm ² , while the size of the elementary diode is 68.0 × 1440.7 μm ² .

For unpacking the FPU chip into the case, for example, of the КТ-2 type, the FPU cathode is connected to the case “3” terminal, and the FPU anode is connected to the case “4” terminal (Fig. 11).

FPU formed by electrical series-parallel connection of elementary diodes, in which to increase the current sensitivity of the entire device as a whole, the FPU is made in the form of left and right PSFs, each of which contains twenty elementary diodes connected in a group in parallel.

For unpacking the FPU chip into the KT-2 case, the cathode of the left FPU is connected to the output “2” of the case, the anode of the left FPU is connected to the output “1” of the case, the cathode of the right FPU is connected to the output “3” of the case, and the anode of the right FPU is connected to the output "4" of the body (Fig. 11).

To realize the strength of the welded crystal leads to the traverses of the leads in the case, ultrasonic welding is used, for welding, choose the aluminum wire AK-0.9 PM-30 (A) and use additional equipment in the form of a retaining ring that lowers the resonant frequency of these traverses, worn on the traverses before unwrapping.

The spread of the electron phase transitions on the plate during measurements on the SSS structures was 10-12%. This is due to the imperfection of the initial film and the misregistration of the layers during the formation of photolithographs, which is a feature of the contact FLG method.

For subsequent packing, plates EFO-01-05 (bulk silicon) and EFO-02-02 (KNS) were selected.

After operations on the assembly of crystals in the casing (cutting plates on crystals, mounting in the casing, welding out the leads and welding the covers), the EFP measurements were performed. The results of measurements of the dark current, current sensitivity, measured on FPU, made using silicon technology and according to planar SPS technology - single-element FPU, are given in table. 2, two-element FPU - in table. 3.

To study the impulse characteristics, we measured the characteristics of the FPU of different versions in a pulsed current mode at frequencies of 1 kHz, 100 kHz, and 1 MHz. Oscillograms of the output signals of single-element FPU according to SSC technology are presented in FIG. 19 (100 kHz), FIG. 20 (1 MHz) two-element FPU according to SSC technology - in FIG. 21 (100 kHz), FIG. 22 (1 MHz), respectively.

According to the oscillograms in FIG. 19-22, the following parameters were determined:

- the amplitude of the signal U _m ;

- duration t _0.5 at the level of 0.5 U _m ;

- the duration of the front t _0.1-0.9 at the level of (0.1-0.9) U _m ;

- the duration of the decline t _0.9-0.1 at the level of (0.9-0.1) U _m .

In the table. Figure 4 shows the results of measurements of the dark current and current sensitivity of a single-element FPU made using silicon technology and planar SPS technology.

In the table. Figure 5 shows the results of measurements of the dark current and current sensitivity of a two-element FPU made using silicon technology and according to planar SPS technology.

In the table. Figure 6 shows the results of measurements of the electric parameters of FPUs using silicon technology at optical pulse repetition frequencies from 1 kHz to 1 MHz.

In the table. 7 shows the results of measurements of the electric parameters of the FPU according to the planar SPS technology at optical pulse repetition frequencies from 1 kHz to 1 MHz.

In the table. Figure 8 shows the values of the photoelectric coupling coefficient between the PSE of two-element FPU on SPS samples.

The results of measurements of the FPU electrical parameters by silicon bulk technology at optical pulse repetition frequencies from 1 kHz to 1 MHz are presented in Table. 6, and FPU according to planar SPS technology - in table. 7.

The measured intrinsic time constant was 40 ns. The data on the study of the photoelectric coupling coefficient between the PSE of FPU on SPS samples are given in table. 8. Thus, at a light emission power of 6.94 μW, the photocurrent on bulk silicon is 14.782 μA, and on SPS structures it is 9.443 μA.

The threshold power measurements were carried out on single 2D301S-01 photodiodes. For measurements, we took samples made using both SSC technology and bulk silicon samples. The threshold power was measured by measuring the photocurrent when a calibrated power was applied to a sample of light. So, when the output power of the emitter is 0.1 mW, the radiation power incident on the PSE is 0.00694 mW or 6.94 mW.

The measurement results are presented in table. 9 and in FIG. 23. Moreover, in the table. Figure 9 shows only the minimum and maximum values of the threshold power.

To study the resistance of the FPU to the effects of factor 7.I7, 10 points in 5 zones were measured on modeling installations on each plate (the arrangement of controlled points on the plate is shown in Fig. 24). The electron-beam phase intensities of crystals of single photodiodes 2D301S-01 were measured. The measurement results are summarized in table. 10 and tab. eleven.

In the table. 10 and tab. 11 contains only data on the maximum and minimum values of the measured values of the dark and photocurrents.

The durability of the packaged products is determined on the test complex RIK 0401. According to the method similar to that used when testing the crystals on the plate, a complex of measurements of the dark current values was carried out through each level value 0.2 × 6U _C by factor 7.I ₇ .

^*) When measuring the dark current, we studied the dynamics of its change during the exposure dose (the value in the upper line of the corresponding column of the table), as well as the degree of restoration of the parameters after a short-term (about 1 min) termination of exposure (value in the lower line).

^*) When measuring the dark current, we studied the dynamics of its change during the exposure dose (the value in the upper line of the corresponding column of the table), as well as the degree of restoration of the parameters after a short-term (about 1 min) termination of exposure (value in the lower line).

After the factor 7.I ₇ reached the level of 6U _{C, the} source was turned off and the photocurrent was measured. The measurement results are presented in table. 12-15. The tables show the maximum and minimum values of the dark current and photocurrent.

A study of the resistance of FPU to the effects of factor 7. And ₆ on the effects of TREE was carried out using a laser simulator "Radon-8N" from the laser hardware-software complex LAPK-0501 according to the general certified methods RD 319.03.22-97 and OST 11.073.013 ( part 10, method 1000-1).

Under the influence of a laser pulse, a change in the Dark Current parameter was recorded. Examples of laser pulse exposure are shown in FIG. 25 and FIG. 26.

Then, studies were conducted on the level of resistance of experimental FPU samples to the effects of factors with characteristics 7.I ₆ (Fig. 27, Fig. 28, Fig. 29), 7., And ₁ (Fig. 30, Fig. 31), 7.I ₇ (Fig. 32, Fig. 33). The objects of research were FPU in hull design on silicon wafers and on SPS, including one or two PSEs. Before and after the studies, the following FPU parameters were controlled: photocurrent; the amplitude of the photosignal; the duration of the signal at a level of 0.5 of the amplitude value; the duration of the front of the photo signal at a level of from 0.1 to 0.9 of the amplitude value; the duration of the decline of the signal at a level of from 0.1 to 0.9 of the amplitude value.

Studies of the influence of factors with characteristics 7.I ₆ , 7.I ₁ , 7.I ₇ and the FPU work showed the following:

Studies on the impact of a factor with a characteristic of 7. And ₆ were carried out to a level of 0.6 × 5us. After exposure to residual effects, SPS-based FPU samples were not found to be functional. The degradation of the parameters of the Si-based samples that remained functional did not exceed 5%.

Studies on the impact of a factor with characteristic 7.and ₁ were carried out to a level of 1.1 × 3us. After exposure, the degradation of the FPU of the SPS technology did not exceed 4%, while the degradation of the FPU on Si amounted to more than 80% (that is, the FPU on Si lost their operability). At the time of exposure, the output voltage on the FPD both on the basis of bulk Si and on the basis of SPS increased by 2.5–4.5 times. The shape of the output voltage repeated the shape of the radiation pulse, the duration of which at half maximum was approximately 450 μs.

Studies on the impact of a special factor with characteristic 7.I ₇ were conducted up to the level of 6us. In the process of exposure to radiation from the installation, a test container with the FPU installed in it was placed in the radiation field. The exposure lasted for 33 minutes, during which the exposure level of 6us factor ₇ was reached at the facilities. And ₇ .

After exposure, the photo signal degradation of Si-based FPUs was 10–20%. The degradation of FPU based on SPS did not exceed 7%, while for samples with one photosensitive area, the restoration (increase) of the photo signal was 15–25% compared with the level before exposure.

Analyzing the data on the resistance of FPU chips on the plates, we can conclude that the current sensitivity is affected by factor 7. And ₇ does not affect. Changes in the parameters before and after exposure remain within the error of positioning the source of factor 7.and ₇ relative to the crystal. As for the dark current, the situation here is not so clear. On the plate from the batch EFO-01-04, made using bulk silicon technology, an increase in the dark current is observed during the exposure, however, after the exposure is removed, the initial parameters are restored. On crystals made using the KNS technology (batch EFO-02), the restoration of the initial parameters is slower. Based on the data obtained, for finished samples, conclusions can be drawn that are generally similar to those obtained when testing FPU chips on a wafer. It is also possible with a high degree of probability to assume that during encasing, the resistance of crystals to WWF increases due to the shielding effect.

Investigations were made of the resistance of experimental samples to the effects of factor 7. and ₆ in terms of resistance to TREE effects. From the results obtained, it is seen that the FPU samples (made on bulk Si and on SSC structures) remained operational after exposure to a laser pulse. The recovery time of the silicon sample is about 150 μs. The recovery time of a sample fabricated on KNS structures is ~ 0.5 μs.

From the above results it is seen that the factor with characteristic 7.I ₇ influences the parameters of the FPU, however, not as significant as the factor with characteristic 7.I ₁ .

The voltage degradation of Si-based FPUs was 10–20%. The degradation of FPU based on SPS did not exceed 7%, while the samples with one photosensitive area showed a restoration (increase) of voltage by 15–25% compared with the level before exposure.

Thus, a sufficiently high level of resistance of FPU KNS to the influence of factors with characteristics 7.I ₇ , 7.I ₆ , 7.I _{1 is} shown, unlike FPU on bulk silicon.

Literature

1. Menn Nafthaly. Practical Optics / Elsevier Academic Press: Burlington, MA, USA; San Diego, CA, USA; London, UK, 2004 .-- P. 334.

2. Re Valeric 3D Vertical Technologies for Advanced Semiconductor Radiation Sensor and Readout Electronics // 4th IEEE International Workshop on Advances in Sensors and Interfaces 28-29 June 2011 Borgo Egnazia Savelletri di Fasano, (Brindisi), Italy IEEE Catalog Number: CFP11IWI-USB ISBN: 978-1-4577-0622-6. - pp. 33-36.

3. Berdermann E. For the NoRDHDia, "Advance Diamond Particle Detector", Nuclear Physics News, Vol. 19, No. 1 (2009), 79-86.

4. Adam W. et al for RAD42 collaboration, "The Development Diamiond Tracking detector for LHC", NIMA, 514 (2003), 79-86.

5. Popov V.P., Ilnitsky M.A. Efficiency and reliability of CMOS transistors with nanometer-sized elements under radiation exposure / Proceedings of the 1st Russian-Belarusian scientific and technical conference "Elemental base of domestic radio electronics" dedicated to the 110th birthday of OV Loseva / Ed. A.E. Seedling. - N. Novgorod: NIZHNY NOVGOROD RADIO LAB. 2013. In 2 volumes T. T. 1.P. 102-108.

6. Patti, L. et al, "Monolitic Pixel Detectors in 0.13 μm CMOS Technology with Sensor Level Continuous Time Charge Amplification and Shaping" Nucl. Instr. Meth., Vol. A568 (2006), pp. 159-166.

7. Patti, L. et al, "Vertical Integrated Deep N-well CMOS MAPS With Sparsification and Time Stamping Capabilities For Thin Charged Particle Trackers", Nucl. Instr. Meth., Vol. A624 (2010), pp. 79-86.

8. Patti, R.S. "Thre-Dimensional Integrated Circuits and Future of System-in-Chip Design", Proceedings of the IEEE, Vol. 94, No. 6 (2006), pp. 1214-1224.

9. Menzer Mark A. Applied Optics Fundamentals and Device Applications Nano, MOEMS, and Biotechnology / NY, FL USA: CRC Press Taylor & Francis Group, 2011. P. 675.

10. Blash, K.P. et al., Monolitic optical integrated control circuitry for GaAs MMIC-based phased arrys, Proc. SPIE 578, September, 1985.

11. Cochran Donna J., Boutte Alvin J., Campola Michael J., Carts Martin A., Casey Megan C., Chen Dakai, LaBel Kenneth A., Ladbury Raymond L., Lauenstein Jean-Marie, Marshall Cheryl J., O'Bryan Martha V., Timothy R. O'Bryan, Pellish Jonathan A., Sanders Anthony B., and Xapsos Michael A. Recent Total Ionizing Dose and Displacement Damage Compendium of Candidate Electronics for NASA Space Systems / 2010 IEEE Radiation Effects Data Workshop Record, L. Scheick, Editor, New Jersey, IEEE, 2010.

Claims (54)

1. A method of manufacturing a photodetector (FPU) by forming on the substrate planar layers of the FPU and the topological pattern of photosensitive elements, regions of the anode and cathode, creating metallization and passivating coatings and contact pads, cutting and assembling the FPU crystal in the housing, characterized in that as The substrate material uses heteroepitaxial structures (HES) of the silicon-on-sapphire (SSS) technology with a thickness of the epitaxial silicon layer of 5 μm, n-type conductivity with a resistivity of 4.5 Ohm cm d 10 ohm-cm and the concentration of basic impurities are less than 10 ¹⁵ cm ^-3. 2. The method according to p. 1, characterized in that a layer of polycrystalline silicon is applied to the inverse side of the HES. 3. The method according to p. 1, characterized in that the formation of the boundaries of individual photosensitive elements (PSE) is produced by etching grooves along the perimeter of the PSE to the entire depth of the epitaxial layer of silicon. 4. The method according to p. 3, characterized in that the etching of the grooves is carried out by deep plasma-chemical etching of silicon on a photoresist mask. 5. The method according to p. 1, characterized in that the formation of a topological drawing of the working layers of the region of the anode and cathode is carried out by contact photolithography, subject to the need to combine photolithography (PL) of the p-anode and n-cathode. 6. The method according to p. 5, characterized in that when the regions of the p-anode and n-cathode are formed, the epitaxial silicon film is first oxidized to a depth of 0.3 μm, then films of silicon dioxide (SiO ₂ ) and silicon nitride (Si ₃ N ₄ ) plasma chemical deposition. 7. The method according to p. 6, characterized in that when forming the regions of the p-anode and n-cathode, PL is performed by opening an oxidized epitaxial silicon film (SiO ₂ + CVDSiO ₂ + Si ₃ N ₄ ). 8. The method of claim. 7, characterized in that the formation region of the p-anode perform implantation of boron ions, the ion energy E = 40 keV, D = dose ^-2 mkKl⋅sm 500, through the buffer oxide mask photoresist. 9. The method according to p. 8, characterized in that during the formation of the n-cathode regions, phosphorus ions are implanted, ion energy E = 40 keV, dose D = 800 μC⋅cm ^-2 , through a buffer oxide through a photoresist mask. 10. The method according to p. 9, characterized in that the resulting structure is annealed at a temperature of from 850 to 950 ° C. 11. The method according to p. 10, characterized in that the optimal ratio of the parameters of the processes of ion implantation is selected - the dose of ions and the energy of ions and high-temperature annealing in the temperature range from 850 to 950 ° C. 12. The method according to p. 10, characterized in that they implement the annealing process with afterburner - a gradual increase in temperature, double annealing: 10 min in a nitrogen atmosphere at 850 ° C and 10 min in a nitrogen atmosphere at 950 ° C. 13. The method according to p. 1, characterized in that when creating a metallization, an aluminum alloy with 1% silicon 1.0 μm thick is first sprayed by magnetron sputtering. 14. The method according to p. 13, characterized in that when forming the metallization pattern, a photocopying operation (PC) is performed, and then plasma-chemical etching (PCT) of aluminum and liquid etching of silicon chips are performed. 15. The method according to p. 14, characterized in that when the metallization is created, the operation is “burning metal” at a temperature of T = 450 ° C for 15 minutes in an atmosphere of dry nitrogen. 16. The method according to p. 1, characterized in that when creating a passivating coating of the regions of the PSE, the FSS layer is deposited with a thickness of 1.0 μm with a phosphorus content of 3% to 5%. 17. The method according to p. 1, characterized in that when creating metallization, including the formation of contact pads, open the contact pads by conducting FC "passivation" and subsequent chemical etching of the FSS. 18. The method according to p. 1, characterized in that the structure of the FPU introduce a test line containing a set of test elements: a resistor with a working area made on the area of the anode; a resistor with a working region made on the cathode region; single diode of a small area; single diode of a small area, limited by a "groove"; three and ten parallel-connected diodes, limited by a "groove"; three and ten parallel-connected diodes, not limited to the "groove". 19. The method according to p. 18, characterized in that the test resistors are made in the layers of the anode and cathode in the active region. 20. The method according to p. 18, characterized in that the test diodes of two types are performed for the anode with the dimensions of an elementary diode 50 × 50 microns. 21. The method according to p. 1, characterized in that to control the quality of the formation of planar layers of the FPU in the field of the crystal (chip) of the FPU introduce controlled elements and layer identifiers. 22. The method according to p. 19, characterized in that for the designation of the test resistors in the metallization layer for the resistor in the cathode layer, the symbol "R _K " is performed, and for the resistor in the anode layer, the symbol "R _A " is performed. 23. The method according to p. 1, characterized in that for monitoring the electrophysical parameters of the FPU, measurements are used by the probe station on test structures and on working crystals. 24. The method according to p. 1, characterized in that for the separation of the plates into crystals (chips) FPU use the method of disk cutting using a circular saw blade with a diamond coating with a thickness of the edge of the saw 0,036 mm while supplying deionized water. 25. The method according to p. 24, characterized in that the cutting depth is carried out to a depth of 2/3 to 3/4 of the thickness of the plate. 26. The method according to p. 1, characterized in that the FPU is placed in metal-glass cases. 27. A photodetector formed by an electrical series, parallel or parallel-parallel connection of elementary diodes, characterized in that the topological layers are formed at HPS technology of SPS with an epitaxial silicon layer thickness of 5 μm, n-type conductivity with a resistivity of 4.5 Ohm⋅ cm up to 10 Ohm⋅cm, with a concentration of the main impurity of at least 10 ¹⁵ cm ^-3 and a layer of polycrystalline silicon deposited on the inverse side of the HES, and the structures of elementary diodes are formed in alternating order from top to topological layers: “active region”, “n-pocket”, “anode”, “cathode”, “metal”, “passivation”. 28. The photodetector according to claim 27, characterized in that the elementary diodes are isolated between themselves through the "grooves" of a width of 20 μm through the sapphire layer. 29. Photodetector p. 28, characterized in that the contact pads of elementary diodes are outside the "grooves". 30. The photodetector according to claim 29, characterized in that each of the elementary diodes is connected to the other pads from the diode array in the amount of 8 pieces, arranged uniformly on the periphery of each of the elementary diodes. 31. The photodetector according to claim 30, characterized in that the contact pads are formed from top to bottom from passivation-metal layers. 32. The photodetector according to claim 31, characterized in that the width of the opened passivation region is 130 μm. 33. The photodetector according to claim 27, characterized in that a test ruler with a set of test elements is included in the FPU: a resistor with a working area made on the area of the anode; a resistor with a working region made on the cathode region; single diode small area; a single diode of a small area limited by a "groove"; three and ten parallel connected diodes, limited by a "groove"; three and ten parallel connected diodes, not limited to the "groove". 34. The photodetector according to claim 33, characterized in that the test elements introduced into the field of the crystal (chip) of the FPU in the main design layers are formed with the dimensions: in the layer "active region" 6.0 microns; in the n-pocket layer, 2.6 μm; in the layer "anode" 6.0 microns; in the cathode layer 6.0 microns; in the metallization layer 4.0 microns; in the layer “passivation” is not controlled. 35. The photodetector according to claim 27, formed by electric parallel connection of elementary diodes, characterized in that twenty elementary diodes are connected in a group in parallel with the total size of one photosensitive element (PSE) (1.40 ± 0.01) × (1.40 ± 0.01) mm ² , while the size of the elementary diode is 68.0 × 1440.7 μm ² . 36. The photodetector according to claim 27, formed by an electric series-parallel connection of elementary diodes, characterized in that the FPU is made in the form of left and right PSEs, each of which contains twenty elementary diodes connected in a group in parallel.

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