RU2592887C1 - Method for phase automatic frequency control with filtration - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: method for phase automatic control enables synchronisation from single-phase initial signal with interference. System includes units of: first order phase filtration, second order band-rejection filter, first order low-pass filtering, integration, multiplication, digital filters coefficients calculation, four-quadrant arctangent. Use of discrete methods for physical implementation with the help of microprocessor devices enables performing comparison and calculation of non-linear functions with acceptable accuracy and computational resources. Filters are implemented with variable coefficients and have the first and the second orders. Due to relatively low sensitivity of the phase filter to the frequency change the reference phase can be fastly identified from the initial signal. Use of discrete integrator with feedback by integration coefficient enables the synchronised frequency signal fast setting to the operational mode. Use of discrete filter with variable coefficients and taking into account the phase transition through limiting values enables efficient filtration of the synchronised phase without its shift relative to the phase of the initial signal fundamental harmonic. This method makes it possible to build on its basis systems of control by harmonic components in single- and multiphase systems and by symmetrical components in multiphase systems. Main application of this method is in control of conversion equipment, it can also be used for fast synchronisation in communication equipment and other applications with the requirements of high speed of operation by setting up to the main frequency and reference phase identification.

EFFECT: improved performance of practical fast synchronisation up to one-two periods of synchronised frequency signal, interference filtering in generated signals of synchronised phase and frequency.

1 cl, 1 dwg

Description

The method relates to converting, computing and communication technology. It can be used for converters, communication systems, and other applications where phase-locked loop is used to transition to a synchronously rotating coordinate system in the reference phase or modulation-demodulation is performed based on the reference orthogonal signal.

A large number of different methods are known for constructing phase locked loop systems, for example, / 1 /. This method uses a discrete second-order differential equation, quadrature transformations with a PI controller. The disadvantage of this method is the lack of phase filtering, there is no quick recovery of the phase of the original signal, the dependence of the settings of the PI controller on the frequency of the original signal, synchronization is performed for 2 periods.

There is also known a method in which quick synchronization is performed when the mains voltage disappears and is resumed / 2 /. This method uses the assumption that there is no change in the phase of the generated voltage due to a sufficiently large inertia of the frequency change, using a resonant link that performs free oscillations when the voltage is lost, but if there are generators with a rapidly changing phase, this method will not be fast enough.

There is a method in which phase adjustment is performed using a controlled quadrature filter for synchronization, however, it is necessary to use an orthogonal input signal, there is no filtering and constant time control of the compensator, which is subject to frequency estimation based on uncontrolled dynamic links / 3 /.

A known method in which the frequency of the input orthogonal signal is estimated using double integration, filtering and harmonic suppression device / 4 /. This method has the disadvantage that an orthogonal signal is necessary, filtering is performed for selected harmonic components, there is a complex algorithm for harmonics extraction based on harmonic oscillators, several coefficients must be adjusted.

The closest analogue to the proposed method is a method of constructing a PLL system based on / 5 /. This prototype method uses the Clarke transform from a three-phase source signal, leading it to an orthogonal one, then the square of the phase is restored from this signal, then the square root is found and the phase of the original signal is restored, then the trigonometric functions are calculated using this phase at single and double frequencies on the basis of which the second harmonic filter coefficients are formed and the quadrature signal is generated, after which the reference signal is generated Which can be used for synchronization. Additionally, in this method there is the possibility of dividing the initial three-phase signal into symmetrical components in the form of direct, reverse and zero sequences, the main purpose of the prototype is to isolate the generalized vector from the initial three-phase signal.

The disadvantage of this method is that it lacks the ability to ensure the formation of an instant phase from a single-phase signal with high speed under given initial conditions. There is also no interference filtering of the synchronized signal. For the prototype method requires a three-phase source signal. There is no automatic maintenance of the given coefficients of discrete dynamic elements, which implies their initial selection or calculation.

The objective of the invention is the creation of a phase-locked loop system for a single and multiphase source signal, the formation of the reference phase and its filtering with high speed using digital signal processing, as well as the absence of any tuning and selection of coefficients in a wide range of synchronization frequencies.

The proposed method of phase-locked loop with the original signal, filtered phase filter, multiplied by the received value with the original signal, filtered band-stop filter, generating a control error in the DC component of the multiplication result with a zero reference signal and integrating the error with the obtained value of the synchronized frequency, based on the generated the values of the synchronized frequency signal are calculated coefficients of discrete filters, then calculated by the values of the coefficients come in as parameters for phase filtering, band-pass filtering and low-frequency filtering, while the reference phase is calculated with the four-quadrant arctangent from the original signal and the signal after phase filtering, along with this, the synchronized frequency is integrated, and a signal is generated the recovered phase, then the difference between the recovered phase and the reference is calculated, the obtained phase difference is filtered by a low-pass filter obtaining a filtered phase difference, and then computes the phase difference between the reconstructed and filtered phase difference thus obtained the required phase synchronized.

When searching for similar patented devices, no structural solutions were identified with the equivalent claimed method of phase-locked loop with filtering features. Thus, the proposed method meets the criterion of scientific novelty.

The fundamental difference of the proposed phase-locked loop is the presence of elements in the form of digital filters of the first and second orders with variable coefficients, calculated by the given formulas and allowing the fast formation of the reference orthogonal signal, frequency isolation and filtering of the reference phase based on the input signal with a sinusoidal main component and interference. The use of digital filters with variable coefficients allows for a high synchronization speed with a rapid change in the frequency of the input signal. The value of the clock frequency can reach up to a quarter of the sampling frequency. Additionally, the method contains a discrete integrator, which is used as a controller with a variable coefficient and serves to reduce to zero the DC component at the output of the multiplication unit by controlling the phase difference between the original signal and the signal passed through the phase filter. The PLL system has a signal switching implemented as conditional transitions used to implement a first-order digital low-pass filter that reduces interference on a sawtooth phase signal taking into account its transition through boundary values corresponding to angles of ± 180 el. hail. The use of filtering can significantly reduce interference, while there is no significant shift in the instantaneous value of the restored phase relative to the sinusoidal component of the original signal.

In FIG. 1 shows a general diagram of the proposed method, where the following blocks are present: 1 - a digital filter that implements the phase filtering function, 2 - a block of multiplication of two signals, 3 - a digital filter that implements the function of a band-stop filter, 4 - an error signal generating unit in the form of a difference signal values, 5 - block of the zero signal of the reference to the constant component of the error signal, 6 - block of a digital integrator with automatically adjustable gain, 7 - block for calculating the coefficients of digital filters, 8 - block is calculated I of the four-quadrant arctangent of the two arguments of the instantaneous reference phase, 9 is a discrete integrator that restores the phase of the synchronized frequency, 10 is a block for generating the difference between the reconstructed phase and the phase between the signals at the input and output of the phase filter, 11 is a digital filter that generates a signal of the filtered phase difference, 12 - a summing unit forming the desired filtered phase.

и поступает на выходной порт 3 блока 1.There is a phase filter unit 1 that implements the phase rotation function of the initial signal “s” at a synchronized frequency of -90 e. hail. The filter is a first-order IIR filter with coefficients in the form of the corresponding numerical values “b ₀ ”, “b ₁ ” and “ a ₁ ” that vary in time, the initial signal is fed to input 1 of block 1, the calculated values of the coefficients are fed to the input port bus 2 of block 1, the output signal is generated based on a digital filter of the form

and arrives at the output port 3 of block 1.

The arithmetic multiplication unit 2 implements the multiplication of the original signal by the signal received from the output of the phase filter 1. At the same time, the output is a constant component depending on the phase between the signal input and passed through the phase filter, as well as a variable component with doubled frequency, while the constant component equal to zero if the signal from the output of the phase filter is shifted by 90 el. hail. in relation to the original signal at the synchronized frequency.

, исходный сигнал поступает на входной порт 1 и формируется на выходном порте 3 блока 3.Digital filter 3, which implements the function of band-stop filtering with a center frequency equal to twice the synchronized frequency. The doubled frequency is contained in the signal after passing through the block of arithmetic multiplication 2, the signal from which goes to block 3. Filter 3 with the given values of the coefficients "b ₀ ", "b ₁ ", "b ₂ ", " a ₁ " and " a ₂ " time-dependent suppression of the second harmonic and the selection of the constant component. The coefficients arrive in the form of values on the input port 2. Filter 3 is implemented as a discrete filter of the form

, the initial signal arrives at input port 1 and is formed at output port 3 of block 3.

There is a block 4 for receiving the error signal as the signal difference from the multiplication block 2 with a zero value of 5. Thus, a control error is generated in the DC component proportional to the sine of the deviation of the phase difference at the input and output of the phase filter by -90 e. Hail. for the integrator 5. With a zero control error, the phase difference at the output and output of the phase filter 1 is -90 el. hail.

. Коэффициент ki(y) зависит от выходного значения интегратора и вычисляется как

, где ƒd - значение частоты дискретизации в Гц, «y» - сигнал с выходного порта 2 интегратора 6, Ki - неотрицательная постоянная, определяющая быстродействие и устойчивость и имеющая значение по умолчанию Ki=2, значение m для простоты расчетов выбирается целым числом 1 или 2, при этом использование квадратичной зависимости позволяет реализовать более высокую скорость синхронизации, также возможно применение заданной постоянной времени интегрирования ki(y)=Ki=const, в этом случае скорость синхронизации слабо зависит от синхронизируемой частоты и параметр Ki подлежит начальному выбору. Интегратор имеет задание начальных условий в первый момент времени в виде значения частоты ƒ₀, выбираемой произвольно, при этом имеется возможность задать ее значение до половины частоты Найквиста и, рациональней, задать близкой к предполагаемой частоте синхронизации.There is an integrator unit 6, which integrates the error signal after 4. The input signal "x" is supplied to port 1 of the integrator 6, the output "y" is formed on port 2. The integrator is implemented as a transfer function

. The coefficient ki (y) depends on the output value of the integrator and is calculated as

, where ƒd is the value of the sampling frequency in Hz, “y” is the signal from the output port 2 of integrator 6, Ki is a non-negative constant that determines the speed and stability and has a default value of Ki = 2, the value m is chosen by integer 1 or 2, the use of a quadratic dependence makes it possible to realize a higher synchronization speed, it is also possible to use a given integration time constant ki (y) = Ki = const, in this case, the synchronization speed is weakly dependent on the synchronized frequency and pairs tr Ki to be the initial choice. The integrator has the task of setting the initial conditions at the first moment of time in the form of a frequency value ƒ ₀ , chosen arbitrarily, while it is possible to set its value to half the Nyquist frequency and, more rationally, set it close to the expected synchronization frequency.

, где f(t) - синхронизируемая частота, затем эти сигналы используются для вычисления коэффициентов по выражениям:

b₁=1 для фазового фильтра;There is a block for calculating the coefficients of digital filters 7, which calculates the coefficients "b ₀ ", "b ₁ ", "b ₂ ", " a ₁ " and " a ₂ " for the second order or "b ₀ ", "b ₁ " and " a ₁ ”for the first order in the digital filters of blocks 1, 3 and 9. The coefficients are selected so that the block contains the input signal port 1, which is the output of the integrator 6. The input signal from port 1 is a frequency function depending on the samples“ f ” with a constant step in time. Next, calculations are performed by the formulas

, where f (t) is the synchronized frequency, then these signals are used to calculate the coefficients from the expressions:

b ₁ = 1 for a phase filter;

- для фильтра низкой частоты;

- for a low-pass filter;

a ₁=b₁= -2·b₀·C₂, a ₂=2·b₀-1.for the band-pass filter, the coefficients are defined as C ₂ = 2 · C ² -1,

a ₁ = b ₁ = -2 · b ₀ · C ₂ , a ₂ = 2 · b ₀ -1.

A rational calculation of the coefficients with minimization of the division operations and calculation of trigonometric functions is carried out. The trigonometric functions of the double argument are calculated using the reduction formulas, thus, it is sufficient to determine the values of the sine and cosine for the fundamental frequency.

The function of calculating the arctangent of the double argument (four-quadrant arctangent) 8 generates the signal of the unfiltered reference phase "γ" from the samples of the input synchronized signal "s" and the same signal that passed through the phase filter 1.

. Интегратор имеет сброс на ненулевые начальные условия при спаде выходного сигнала до выполнения неравенства γ₁≤-2·π, при этом устанавливается новое выходное значение γ1=2·π, причем установка производится по переходу неравенства от ложного значения к истинному (передний фронт).There is a discrete integrator 9 with input port 1, which receives samples of the synchronized frequency "f" from block 6 and output port 2, on which the output signal of the restored phase "γ ₁ " is generated. The integrator implements the basic transfer function

. The integrator has a reset to nonzero initial conditions when the output signal drops to the inequality γ ₁ ≤-2 · π, and a new output value γ1 = 2 · π is set, and the installation is performed by the transition of the inequality from a false value to a true one (leading edge).

There is a block of difference 10, which forms the difference between the frequency-restored phase γ1 and the absolute phase γ. The phase difference is fed to the input port 1 of the low-pass filter 11.

, где корректировочный коэффициент «с» является зависящим от задержанных на один отсчет значений «x» и «y». Определяется разница между входным отсчетом x_n и его задержанным значением на один такт x_n-1 значением как dx=x_n-x_n-1, затем определяется условие: если dx≥π, то с=2·π, также если dx≤-π, то с= -2·π, иначе с=0.There is a low-pass filter 11 with phase transition correction. The phase difference is fed to input port 1 from the difference unit 10, the coefficients of the digital filter are fed to input port 3 from the coefficient generating unit 6, the resulting signal of the filtered phase difference is generated at output port 2. The low-pass filter is implemented on the basis of a digital filter

, where the correction factor “c” is dependent on the values “x” and “y” delayed by one count. The difference between the input sample x _n and its delayed value by one cycle x _n-1 value is determined as dx = x _n -x _n-1 , then the condition is determined: if dx≥π, then c = 2 · π, also if dx≤ -π, then c = -2 · π, otherwise c = 0.

There is a block of difference 12, which subtracts the filtered phase difference by the low-pass filter 11 from the reconstructed phase after the integrator 9. At the output of the block of difference 12, the required synchronized phase signal γ _f is generated.

A phase locked loop with filtering works as follows.

The initial synchronizing signal in the form of samples is fed to the input of the phase filter 1, after which the source and filtered signals are multiplied by the multiplication unit 2, the resulting signal is then filtered by the band-stop filter 3, then an error signal is generated by the subtraction unit 4 between the signal of the zero signal of the reference 5 from the signals from the output of the band-stop filter 2 and is integrated by a discrete integrator 6, after which the generated synchronized frequency signal is fed to the coefficient generation unit spark filters 7, the calculated coefficients go to filters 1, 3 and 9, the initial signal and the signal from the phase filter 1 go to the arctangent calculation block 8, from the output of which the reference phase is formed, the synchronized frequency signal from the output of the integrator 6 is integrated by block 9, from the output of which the recovered phase is obtained, then the difference between the recovered phase and the reference phase is formed by block 10, which is filtered by a low-pass filter 11, from the output of which a filtered phase difference is formed, then NOSTA unit 12 between the reduced and filtered phase difference and the obtained phase filtered. The result of the application of the method is the synchronized frequency and the filtered phase from the original synchronization signal.

The application of the method allows for phase-locked loop with a given input signal containing the main harmonic and interference. The input signal is fed to the input of the phase-locked loop system; in this case, the instantaneous reference phase is formed, which is calculated from the initial signal and is orthogonal to the synchronized frequency, if the synchronized frequency is close to the main frequency of the initial signal, it is possible to obtain a reference phase with sufficient quality to ensure control processes or demodulation for a time that is a quarter of the period of the synchronized frequency, if filtering is used, then during the half-period. The steady-state mode for the synchronized frequency and the almost exact correspondence of the synchronized phase to the phase of the main harmonic of the initial signal occurs already after a period from the frequency of the initial signal, thereby providing improved performance and quality, including the possibility of synchronization from a single-phase signal compared to the prototype.

Information sources

1. China Patent CN 103825302.

2. China Patent CN 103825300.

3. US patent 8816729.

4. US patent 8751177;

5. US patent 8532230.

Claims (1)

A phase locked loop method with filtering, including band-block filtering, integration, calculation of digital filter coefficients, characterized in that the original signal is filtered by a phase filter, then the received signal is multiplied with the original signal, and then filtered by a band-block filter, then an error signal is generated between the zero reference signal and the signal from the band-stop filter, then the control error is integrated, based on the generated value of the sync signal coefficients of discrete filters are calculated, then the calculated values of the coefficients come as filtering parameters for the phase, band-stop filters and low-pass filter, while the reference phase is calculated by the four-quadrant arctangent of the original signal and the signal from the phase filter, after which the synchronized frequency is integrated , the signal of the restored phase is formed, then the difference between the restored phase and the reference is calculated st, the obtained phase difference is filtered by a low-pass filter to obtain a filtered phase difference, after which the difference between the reconstructed phase and the filtered phase difference is calculated to obtain the desired synchronized phase

Images