CN109510619A - Enhanced phaselocked loop for the detection of single-phase mains voltage synchronizing information - Google Patents
Enhanced phaselocked loop for the detection of single-phase mains voltage synchronizing information Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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Abstract
For the enhanced phaselocked loop of single-phase mains voltage synchronizing information detection, belong to field of conversion of electrical energy, the present invention is to solve the problems, such as that existing phaselocked loop is difficult to accurately estimate power grid amplitude, frequency and phase angle when single-phase mains voltage includes harmonic wave and direct current offset.Single-phase mains voltage is input to the Second Order Generalized Integrator with DC offset estimator, obtains the filter value and orthogonal signalling for not including the input network voltage of direct current offset；The filter value of acquisition and orthogonal signalling are input to the enhanced phaselocked loop of two-phase, obtain the amplitude of single-phase mains voltage, the On-line Estimation value of frequency and phase angle；It is separately added into the first cascade time delayed signal in the Frequency Estimation ring and Amplitude Estimation ring of the enhanced phaselocked loop of two-phase and eliminates filter and the second cascade time delayed signal elimination filter, to eliminate influence of the input harmonics to estimated result.The present invention is used for the online accurate estimation under non-ideal grid conditions.
Description
Technical field
The present invention relates to a kind of phaselocked loops for the detection of single-phase mains voltage synchronizing information, belong to field of conversion of electrical energy.
Background technique
Power electronic equipment is increasing, and current civilian single-phase power grid is because increased by the power electronic equipment accessed
The problems such as influence, there are biggish mains by harmonics and direct current offsets.Therefore, non-ideal grid conditions are the synchronous letter of power grid
Breath, the accurate online real-time estimation including amplitude, frequency and phase angle bring biggish difficulty.
PHASE-LOCKED LOOP PLL TECHNIQUE for single-phase mains voltage synchronizing information real-time estimation mainly includes single-phase enhanced phaselocked loop
With the two-phase synchronous rotating frame phaselocked loop based on virtual orthographic signal.There are transient state estimated bias for single-phase enhanced phaselocked loop
Greatly, the problems such as transient state transient process is longer.And it is needed in the two-phase synchronous rotating frame phaselocked loop based on virtual orthographic signal
Complicated Rotating Transition of Coordinate, calculation amount is larger, has high requirement to the arithmetic speed of controller, it is hard to improve system indirectly
Part cost.
In addition, the single-phase enhanced phaselocked loop of standard and the two-phase synchronous rotating frame locking phase based on virtual orthographic signal
Ring not can solve the influence of Voltage Harmonic and direct current offset to estimated amplitude, frequency and phase angle, especially direct current
Offset can generate the cyclic swing of fundamental frequency in estimated amplitude, frequency and phase angle, if using low-pass filter
It filters out, will cause system dynamic response performance severe exacerbation, significantly reduce its practical value.It is main to wrap in existing solution
The pre-filtering scheme filtered out before harmonic wave and direct current offset are input to phaselocked loop is included, and in amplitude and frequency, phase angle
Estimate that influence of the filter to filter out harmonic wave and direct current offset is added in ring.But above scheme not can be well solved list
The calculating of the poor two-phase synchronous rotating frame phaselocked loop based on virtual orthographic signal of mutually enhanced phaselocked loop dynamic response performance
The problems such as complicated.
Summary of the invention
It is difficult to the invention aims to solve existing phaselocked loop when single-phase mains voltage includes harmonic wave and direct current offset
The problem of accurate estimation power grid amplitude, frequency and phase angle, provide a kind of increasing for the detection of single-phase mains voltage synchronizing information
Strong type phaselocked loop.
Enhanced phaselocked loop of the present invention for the detection of single-phase mains voltage synchronizing information, the phaselocked loop are as follows:
Single-phase mains voltage is input to the Second Order Generalized Integrator with DC offset estimator, obtains and does not include direct current
The filter value and orthogonal signalling of the input network voltage of offset；
The filter value of acquisition and orthogonal signalling are input to the enhanced phaselocked loop of two-phase, obtain the width of single-phase mains voltage
Value, the On-line Estimation value of frequency and phase angle；
The first cascade time delayed signal is separately added into the Frequency Estimation ring and Amplitude Estimation ring of the enhanced phaselocked loop of two-phase
It eliminates filter and the second cascade time delayed signal eliminates filter, to eliminate influence of the input harmonics to estimated result.
Obtain the detailed process of the filter value and orthogonal signalling that do not include the input network voltage of direct current offset are as follows:
Step 1, the starting in cycle estimator acquire single-phase mains voltage uin, subtract the filter value u of a cycle estimatorα
With the direct current offset estimated value u of a upper cycle estimatordcAfterwards, the filtering error u of this cycle estimator is obtainederr；
The filtering error u of this cycle estimatorerrThe first integrator being input in DC offset estimator, obtains this estimation
The direct current offset estimated value u in perioddc；
Step 2, the filtering error u by this cycle estimator obtained in step 1errMultiplied by COEFFICIENT K1, subtract an estimation week
The orthogonal signalling u of phaseβ, difference is input to second integral device, obtains the filter value u of this cycle estimator after being multiplied with angular frequencyα；
The filter value u of this cycle estimatorαIt is input to third integral device after being multiplied with angular frequency, obtains this cycle estimator
Orthogonal signalling uβ。
Obtain the detailed process of the On-line Estimation value of the amplitude of single-phase mains voltage, frequency and phase angle are as follows:
The filter value u of step 3, this cycle estimator for obtaining step 2αWith the orthogonal signalling u of this cycle estimatorβSubtract respectively
Remove the instantaneous estimation value y of a cycle estimatorαAnd yβ, obtain the instantaneous value evaluated error e of this cycle estimatorαAnd eβ；
The instantaneous value evaluated error e of this cycle estimatorαAnd eβIt is input to the calculating enhanced lock of two-phase in the first point multiplication operation device
The frequency error e of the Frequency Estimation ring of phase ringω；
The frequency error e of Frequency Estimation ringωIt is input to the first cascade time delayed signal and eliminates filter, the first cascade is delayed
The output valve that signal eliminates filter is input to proportional integrator, the original frequency ω of the output and setting of proportional integrator0Phase
Add, obtains frequency estimationBy frequency estimationThe 4th integrator is inputted, phase angle estimated value is obtained
The instantaneous value evaluated error e of step 4, this cycle estimatorα、eβWith phase angle estimated valueIt is input to the second point multiplication operation
The amplitude error e of Amplitude Estimation ring is calculated in deviceA；
Amplitude error eAIt is input to the second cascade time delayed signal and eliminates filter, the second cascade time delayed signal is eliminated into filtering
The output valve of device is input to the 5th integrator, obtains Amplitude Estimation value
By the Amplitude Estimation value of acquisitionWith phase angle estimated valueIt is input in multiplier, obtains this cycle estimator uαAnd uβ
Instantaneous estimation value yαAnd yβ。
The frequency error e of the Frequency Estimation ring of the enhanced phaselocked loop of two-phase is calculated in first point multiplication operation deviceωSpecific side
Method are as follows:
The amplitude error e of Amplitude Estimation ring is calculated in second point multiplication operation deviceAMethod particularly includes:
Multiplier obtains this cycle estimator uαAnd uβInstantaneous estimation value yαAnd yβMethod particularly includes:
Advantages of the present invention:
1, input harmonics be can be realized simultaneously, direct current offset filters out, to realize single-phase electricity under non-ideal grid conditions
The online accurate estimation of net voltage magnitude, frequency and phase angle；
2, it is used for single-phase mains voltage amplitude, the On-line Estimation of frequency and phase angle using the enhanced phaselocked loop of two-phase, calculated
Amount effectively improves dynamic response performance while significant decrease.
Detailed description of the invention
Fig. 1 is the schematic diagram of the enhanced phaselocked loop of the present invention for the detection of single-phase mains voltage synchronizing information；
Fig. 2 is the schematic diagram that the first cascade time delayed signal eliminates filter and the second cascade time delayed signal eliminates filter.
Specific embodiment
Specific embodiment 1: illustrating present embodiment below with reference to Fig. 1, single-phase power grid electricity is used for described in present embodiment
Press the enhanced phaselocked loop of synchronizing information detection, the phaselocked loop are as follows:
Single-phase mains voltage is input to the Second Order Generalized Integrator with DC offset estimator, obtains and does not include direct current
The filter value and orthogonal signalling of the input network voltage of offset；
The filter value of acquisition and orthogonal signalling are input to the enhanced phaselocked loop of two-phase, obtain the width of single-phase mains voltage
Value, the On-line Estimation value of frequency and phase angle；
The first cascade time delayed signal is separately added into the Frequency Estimation ring and Amplitude Estimation ring of the enhanced phaselocked loop of two-phase
It eliminates filter and the second cascade time delayed signal eliminates filter, to eliminate influence of the input harmonics to estimated result.
Specific embodiment 2: illustrating that present embodiment, present embodiment make into one embodiment one below with reference to Fig. 1
Step explanation obtains the detailed process of the filter value and orthogonal signalling that do not include the input network voltage of direct current offset are as follows:
Step 1, the starting in cycle estimator acquire single-phase mains voltage uin, subtract the filter value u of a cycle estimatorα
With the direct current offset estimated value u of a upper cycle estimatordcAfterwards, the filtering error u of this cycle estimator is obtainederr；
The filtering error u of this cycle estimatorerrThe first integrator being input in DC offset estimator, obtains this estimation
The direct current offset estimated value u in perioddc；
Step 2, the filtering error u by this cycle estimator obtained in step 1errMultiplied by COEFFICIENT K1, subtract an estimation week
The orthogonal signalling u of phaseβ, difference is input to second integral device, obtains the filter value u of this cycle estimator after being multiplied with angular frequencyα；
The filter value u of this cycle estimatorαIt is input to third integral device after being multiplied with angular frequency, obtains this cycle estimator
Orthogonal signalling uβ。
Specific embodiment 3: illustrating that present embodiment, present embodiment make into one embodiment two below with reference to Fig. 1
Step explanation, obtains the detailed process of the On-line Estimation value of the amplitude of single-phase mains voltage, frequency and phase angle are as follows:
The filter value u of step 3, this cycle estimator for obtaining step 2αWith the orthogonal signalling u of this cycle estimatorβSubtract respectively
Remove the instantaneous estimation value y of a cycle estimatorαAnd yβ, obtain the instantaneous value evaluated error e of this cycle estimatorαAnd eβ；
The instantaneous value evaluated error e of this cycle estimatorαAnd eβIt is input to the calculating enhanced lock of two-phase in the first point multiplication operation device
The frequency error e of the Frequency Estimation ring of phase ringω；
The frequency error e of Frequency Estimation ringωIt is input to the first cascade time delayed signal and eliminates filter, the first cascade is delayed
The output valve that signal eliminates filter is input to proportional integrator, the original frequency ω of the output and setting of proportional integrator0Phase
Add, obtains frequency estimationBy frequency estimationThe 4th integrator is inputted, phase angle estimated value is obtained
The instantaneous value evaluated error e of step 4, this cycle estimatorα、eβWith phase angle estimated valueIt is input to the second point multiplication operation
The amplitude error e of Amplitude Estimation ring is calculated in deviceA；
Amplitude error eAIt is input to the second cascade time delayed signal and eliminates filter, the second cascade time delayed signal is eliminated into filtering
The output valve of device is input to the 5th integrator, obtains Amplitude Estimation value
By the Amplitude Estimation value of acquisitionWith phase angle estimated valueIt is input in multiplier, obtains this cycle estimator uαAnd uβ's
Instantaneous estimation value yαAnd yβ。
Specific embodiment 4: illustrating that present embodiment, present embodiment make into one embodiment three below with reference to Fig. 1
Step illustrates, the frequency error e of the Frequency Estimation ring of the enhanced phaselocked loop of two-phase is calculated in the first point multiplication operation deviceωSpecific method
Are as follows:
Specific embodiment 5: illustrating that present embodiment, present embodiment make into one embodiment three below with reference to Fig. 1
Step illustrates, the amplitude error e of Amplitude Estimation ring is calculated in the second point multiplication operation deviceAMethod particularly includes:
Specific embodiment 6: illustrating that present embodiment, present embodiment make into one embodiment three below with reference to Fig. 1
Step explanation, multiplier obtain this cycle estimator uαAnd uβInstantaneous estimation value yαAnd yβMethod particularly includes:
The operation principle of the present invention is that: as shown in Figure 1, the present invention is to obtain single-phase power grid electricity using Second Order Generalized Integrator
The orthogonal signalling of pressure, while DC offset estimator being added in Second Order Generalized Integrator, the influence of input direct-current offset is eliminated,
Filtered network voltage and its orthogonal signalling are further input to the enhanced phaselocked loop of two-phase, and in the enhanced locking phase of two-phase
Cascade time delayed signal is added in the Frequency Estimation ring and Amplitude Estimation ring of ring and eliminates filter, eliminates the shadow of main input harmonics
It rings, and then obtains amplitude, the On-line Estimation information of frequency and phase angle of accurate network voltage.
U can get by the principle of Second Order Generalized Integratorα, uβAbout input single-phase network voltage uinTransmitting under the domain s
Function indicates are as follows:
From the above equation, we can see that when the frequency of input signal is ω, G1(s) gain is 1, phase shift zero, G2(s) phase shift
It is 1, phase shift is -90 °.Therefore ω is set to the rated frequency of power grid, to guarantee obtained filter value uαIt is same with network voltage
Amplitude, same-phase, and uβWith the same amplitude of network voltage, 90 ° of delayed phase.Input direct-current is deviated, it is assumed that uαIt follows completely
Upper network voltage, then filtering error uerrIn only include direct current offset, after the first integrator in DC offset estimator,
Integrated value can gradually increase, until integrated value is equal with actual direct current offset, filtering error uerrIn no longer comprising direct current it is inclined
It moves, to realize the closed loop estimation of input direct-current offset and filter out.
Further, to improve system dynamic response, the transient error of estimated information is especially reduced, setting two-phase is enhanced
Phaselocked loop is used to estimate the amplitude of network voltage, frequency and phase angle.Just by the above-mentioned two-phase obtained not comprising direct current offset
Hand over network voltage uα, uβThe u in a cycle estimator is individually subtractedα, uβInstantaneous estimation value yα,yβ, obtain instantaneous value estimation and miss
Poor eα,eβ, further according to the frequency of the Frequency Estimation ring of the calculation formula calculating enhanced phaselocked loop of two-phase of following point multiplication operation device
Rate error eω:
In above formulaFor the phase angle estimated value of the enhanced phaselocked loop of two-phase.
Input harmonics in network voltage can equally be input to above formula, thus in eωMiddle generation cyclic swing.It is defeated for n times
Enter harmonic wave, in the e after above formula operationωN+1 cyclic swing of middle generation.Theoretically, it needs to eliminate all numbers humorous
The influence of wave.In view of the harmonic amplitude in actual electric network can significantly reduce with the increase of frequency, only focus on eliminating 2 times, 3
Secondary, 5 times and 7 subharmonic influences, it is corresponding in eωThe number of the cyclic swing of middle generation is 3 times, 4 times, 6 times and 8 times.According to
Time delayed signal eliminates the working principle of filter, designs four time delayed signals elimination filters and is cascaded, respectively described in elimination
Four cyclic swings.The principle that first cascade time delayed signal obtained eliminates filter is as shown in Figure 2, wherein four are prolonged
When signal eliminate filter delay time be taken as respectively input network voltage cycle Tg1/6,1/8,1/12 and 1/16.First
The output that cascade time delayed signal eliminates filter is input to proportional integrator again, the output of proportional integrator and it is preset just
Beginning frequencies omega0It is added, obtains the estimated value of frequencyThe frequency estimationBy the 4th integrator, phase angular estimation is obtained
Value
It is briefly described as follows the estimation procedure of grid voltage amplitude: by the instantaneous value evaluated error e of acquisitionα、eβEstimate with phase angle
EvaluationIt is input to the amplitude error e of the Amplitude Estimation ring of the formula calculating enhanced phaselocked loop of two-phase of following point multiplication operation deviceA:
Due to input harmonics can be obtained after above formula operation with cyclic swing identical in Frequency Estimation ring, by institute
The e of acquisitionAIt is input to and eliminates filter with mutually isostructural second cascade time delayed signal elimination with the first cascade time delayed signal
Filter to filter out because of input harmonics caused by cyclic swing, the output that the second cascade time delayed signal eliminates filter is input to the
Five integrators obtain the estimated value of amplitudeIt is obtainedWith phase angle estimated valueIt is input to following formula and obtains this estimation week
The u of phaseα、uβInstantaneous estimation value yαAnd yβ:
The course of work of the phaselocked loop proposed in a cycle estimator is completed as a result,.
Claims (6)
1. the enhanced phaselocked loop for the detection of single-phase mains voltage synchronizing information, which is characterized in that the phaselocked loop are as follows:
Single-phase mains voltage is input to the Second Order Generalized Integrator with DC offset estimator, obtains and does not include direct current offset
Input network voltage filter value and orthogonal signalling；
The filter value of acquisition and orthogonal signalling are input to the enhanced phaselocked loop of two-phase, obtain amplitude, the frequency of single-phase mains voltage
The On-line Estimation value of rate and phase angle；
The elimination of the first cascade time delayed signal is separately added into the Frequency Estimation ring and Amplitude Estimation ring of the enhanced phaselocked loop of two-phase
Filter and the second cascade time delayed signal eliminate filter, to eliminate influence of the input harmonics to estimated result.
2. the enhanced phaselocked loop according to claim 1 for the detection of single-phase mains voltage synchronizing information, feature exist
In acquisition does not include the filter value of the input network voltage of direct current offset and the detailed process of orthogonal signalling are as follows:
Step 1, the starting in cycle estimator acquire single-phase mains voltage uin, subtract the filter value u of a cycle estimatorαWith it is upper
The direct current offset estimated value u of one cycle estimatordcAfterwards, the filtering error u of this cycle estimator is obtainederr；
The filtering error u of this cycle estimatorerrThe first integrator being input in DC offset estimator, obtains this cycle estimator
Direct current offset estimated value udc；
Step 2, the filtering error u by this cycle estimator obtained in step 1errMultiplied by COEFFICIENT K1, subtract a cycle estimator
Orthogonal signalling uβ, difference is input to second integral device, obtains the filter value u of this cycle estimator after being multiplied with angular frequencyα；
The filter value u of this cycle estimatorαIt is input to third integral device after being multiplied with angular frequency, obtains the orthogonal of this cycle estimator
Signal uβ。
3. the enhanced phaselocked loop according to claim 2 for the detection of single-phase mains voltage synchronizing information, feature exist
In obtaining the detailed process of the On-line Estimation value of the amplitude of single-phase mains voltage, frequency and phase angle are as follows:
The filter value u of step 3, this cycle estimator for obtaining step 2αWith the orthogonal signalling u of this cycle estimatorβIt is individually subtracted
The instantaneous estimation value y of one cycle estimatorαAnd yβ, obtain the instantaneous value evaluated error e of this cycle estimatorαAnd eβ；
The instantaneous value evaluated error e of this cycle estimatorαAnd eβIt is input to the calculating enhanced phaselocked loop of two-phase in the first point multiplication operation device
Frequency Estimation ring frequency error eω；
The frequency error e of Frequency Estimation ringωIt is input to the first cascade time delayed signal and eliminates filter, cascade time delayed signal for first
The output valve for eliminating filter is input to proportional integrator, the original frequency ω of the output and setting of proportional integrator0It is added, obtains
Obtain frequency estimationBy frequency estimationThe 4th integrator is inputted, phase angle estimated value is obtained
The instantaneous value evaluated error e of step 4, this cycle estimatorα、eβWith phase angle estimated valueThe second point multiplication operation device is input to fall into a trap
Calculate the amplitude error e of Amplitude Estimation ringA；
Amplitude error eAIt is input to the second cascade time delayed signal and eliminates filter, the second cascade time delayed signal is eliminated into filter
Output valve is input to the 5th integrator, obtains Amplitude Estimation value
By the Amplitude Estimation value of acquisitionWith phase angle estimated valueIt is input in multiplier, obtains this cycle estimator uαAnd uβIt is instantaneous
Estimated value yαAnd yβ。
4. the enhanced phaselocked loop according to claim 3 for the detection of single-phase mains voltage synchronizing information, feature exist
In the frequency error e of the Frequency Estimation ring of the calculating enhanced phaselocked loop of two-phase in the first point multiplication operation deviceωMethod particularly includes:
5. the enhanced phaselocked loop according to claim 3 for the detection of single-phase mains voltage synchronizing information, feature exist
In the amplitude error e of calculating Amplitude Estimation ring in the second point multiplication operation deviceAMethod particularly includes:
6. the enhanced phaselocked loop according to claim 3 for the detection of single-phase mains voltage synchronizing information, feature exist
In multiplier obtains this cycle estimator uαAnd uβInstantaneous estimation value yαAnd yβMethod particularly includes:
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110661263A (en) * | 2019-11-13 | 2020-01-07 | 东北电力大学 | Self-adaptive delay filter, frequency locking ring comprising filter and grid-connected inverter control method based on frequency locking ring |
| CN111983307A (en) * | 2019-05-21 | 2020-11-24 | 青岛鼎信通讯科技有限公司 | SOGI-based rapid and accurate frequency detection method |
| CN112152609A (en) * | 2020-08-21 | 2020-12-29 | 中车株洲电力机车研究所有限公司 | Phase-locked loop, method for controlling synchronization of grid voltage information and power electronic device |
| CN113113930A (en) * | 2020-09-27 | 2021-07-13 | 青岛鼎信通讯股份有限公司 | Single-phase-locked loop method applied to low-voltage treatment equipment |
| CN113541682A (en) * | 2021-06-15 | 2021-10-22 | 合肥工业大学 | Single-phase voltage soft phase-locked loop based on orthogonal signal generation |
| CN113567734A (en) * | 2020-04-29 | 2021-10-29 | 深圳市费思泰克科技有限公司 | Method for detecting power grid voltage signal parameters |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103558436A (en) * | 2013-10-31 | 2014-02-05 | 哈尔滨工业大学 | Method for network voltage amplitude, frequency and phase angle detection based on one-phase phase-locked loop algorithm |
-
2018
- 2018-11-09 CN CN201811333899.3A patent/CN109510619A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103558436A (en) * | 2013-10-31 | 2014-02-05 | 哈尔滨工业大学 | Method for network voltage amplitude, frequency and phase angle detection based on one-phase phase-locked loop algorithm |
Non-Patent Citations (4)
| Title |
|---|
| M. XIE: "DC Offset Rejection Improvement in Single-Phase SOGI-PLL Algorithms: Methods Review and Experimental Evaluation", 《IEEE ACCESS》 * |
| 刘建华: "一种改进型二阶广义积分锁相环研究", 《电力电子技术》 * |
| 吴晓波: "基于改进自适应陷波滤波器的锁相方法", 《电力系统自动化》 * |
| 李伟: "基于Goertzel滤波器的两相静止坐标系下的增强型锁相环", 《电力自动化设备》 * |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111983307A (en) * | 2019-05-21 | 2020-11-24 | 青岛鼎信通讯科技有限公司 | SOGI-based rapid and accurate frequency detection method |
| CN110661263A (en) * | 2019-11-13 | 2020-01-07 | 东北电力大学 | Self-adaptive delay filter, frequency locking ring comprising filter and grid-connected inverter control method based on frequency locking ring |
| CN110661263B (en) * | 2019-11-13 | 2020-11-03 | 东北电力大学 | Frequency locking ring with self-adaptive delay filter and grid-connected inverter control method based on frequency locking ring |
| CN113567734A (en) * | 2020-04-29 | 2021-10-29 | 深圳市费思泰克科技有限公司 | Method for detecting power grid voltage signal parameters |
| CN113567734B (en) * | 2020-04-29 | 2024-06-11 | 深圳市费思泰克科技有限公司 | Method for detecting power grid voltage signal parameters |
| CN112152609A (en) * | 2020-08-21 | 2020-12-29 | 中车株洲电力机车研究所有限公司 | Phase-locked loop, method for controlling synchronization of grid voltage information and power electronic device |
| CN112152609B (en) * | 2020-08-21 | 2024-05-28 | 中车株洲电力机车研究所有限公司 | Phase-locked loop, method for controlling synchronization of grid voltage information and power electronic device |
| CN113113930A (en) * | 2020-09-27 | 2021-07-13 | 青岛鼎信通讯股份有限公司 | Single-phase-locked loop method applied to low-voltage treatment equipment |
| CN113541682A (en) * | 2021-06-15 | 2021-10-22 | 合肥工业大学 | Single-phase voltage soft phase-locked loop based on orthogonal signal generation |
| CN113541682B (en) * | 2021-06-15 | 2024-02-02 | 合肥工业大学 | Single-phase voltage soft phase-locked loop based on orthogonal signal generation |
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Application publication date: 20190322 |