RU2581418C1 - Manufacturing method of semiconductor device - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: semiconductor device manufacturing method includes processes of doping, forming areas of source, drain and gate, at that the semiconductor device is formed by sequential application of a layer of p-type with thickness of 5 nm with doping concentration of 2·10¹¹ cm^-2, growth of silicone layer with thickness of 0.25 mcm and further cooling of antimony at temperature of 650°C and exposure during two minutes at temperature of 750°C in order to form a monolayer with concentration of antimony atoms of 2·10¹² cm^-2 and annealing at temperature of 750°C during 10 minutes.

EFFECT: semiconductor device manufacturing method by forming a doped layer of p-type serving as a barrier for electrons allows increase in production output of fit structures and improvement of their reliability.

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Description

The invention relates to the field of production technology of semiconductor devices, in particular to the manufacturing technology of a field effect transistor with reduced leakage currents.

A known method of manufacturing a semiconductor device [Application 2128473 Japan, MKI H01L 29/784] through the use of the design of a field effect transistor with reduced influence of a spurious bipolar source / substrate / drain transistor. The structure of the field effect transistor is separated from the pS _i substrate by a layer with an increased hole recombination rate obtained by proton implantation. The channel of the field-effect transistor is separated from the n ⁺ regions of the drain / source by buried n ⁺ pockets - channel limiters. In such devices, due to the formation of parasitic four-layer structures, the characteristics of the devices deteriorate.

A known method of manufacturing a semiconductor device [US Pat. 5144394 USA, MKI H01L 29/06] with improved electrical characteristics by forming contact areas of the sources and sinks of MOSFETs on the surface of S _i substrates using ion doping and diffusion processes; The pn junctions at the internal boundaries of these regions are the boundaries of the MOSFET channel. A layer of thick field oxide is used to isolate individual transistor structures. A thin oxide layer is formed over the contact regions; it is used to isolate those parts of the active structure whose position determines the width of the MOSFET channel.

The disadvantages of the method are:

- increased leakage currents;

- low manufacturability;

- high defectiveness.

The problem solved by the invention: reducing leakage currents, ensuring manufacturability, improving device parameters, improving quality and increasing yield.

The problem is solved by the formation of p-type doping atoms by the conductivity of barriers for electrons.

The technology of the method consists in the following: on silicon wafers successively grown: - an undoped layer of silicon, 0.3 microns thick; - p-type layer with a thickness of 5 nm with an impurity concentration of 2 · 10 ¹¹ cm ^-2 ; - undoped silicon layer with a thickness of 0.25 microns; Antimony is subsequently precipitated and a monolayer forms on the plate at a temperature of 650 ° C. Then the plates are incubated for 2 min at a temperature of 750 ° C. This contributes to the formation of a surface concentration of antimony atoms of 2 · 10 ¹² cm ^-2 . Then, solid-phase epitaxy of the amorphous silicon layer is carried out at a temperature of 550 ° C for 5 min. To improve the quality of the structures, the plates are annealed at a temperature of 750 ° C for 10 min. The low antimony coefficient at a temperature of 750 ° C allows one to obtain a sharp distribution profile of antimony atoms in silicon. All introduced antimony atoms become electrically active, i.e. the concentration of antimony atoms is equal to the concentration of electrons. Then, source and drain areas are formed by ion doping with phosphorus with an energy of E = 30 keV and a dose of 1 · 10 ¹⁵ cm ^-2 , followed by annealing at a temperature of 600 ° C for one hour. By the PFC method at a temperature of 400 ° C, a gate oxide 70 nm thick is grown. In such PTs, the leakage current is reduced. This is due to the fact that, in a PT, a doped P layer is a barrier for electrons. Then, contacts are formed to the areas of drain, source, and shutter of the device using standard technology.

According to the proposed method, semiconductor structures were manufactured and investigated. The results are presented in the table.

Experimental studies have shown that the yield of suitable devices on a batch of plates formed in the optimal mode increased by 15.2%.

Effect: reducing the value of leakage currents, ensuring manufacturability, improving parameters, improving quality and increasing the percentage of yield.

The stability of the parameters over the entire operating temperature range was normal and consistent with the requirements.

The proposed method for manufacturing a semiconductor device by forming a p-type doped layer, which is a barrier for electrons, allows to increase the yield of suitable structures and improve their reliability.

Claims (1)

A method of manufacturing a semiconductor device, including doping processes, the formation of source, drain and gate regions, characterized in that the semiconductor device is formed by sequentially applying a p-type layer with a thickness of 5 nm with an impurity concentration of 2 · 10 ¹¹ cm ^-2 , building a layer of silicon with a thickness of 0, 25 μm and the subsequent deposition of antimony at a temperature of 650 ° C with exposure for two minutes at a temperature of 750 ° C to form a monolayer with a concentration of antimony atoms of 2 · 10 ¹² cm ^-2 and annealing at a temperature of 750 ° C for 10 minutes.