RU2542666C1 - Device for determination of optimal period for control of product technical condition - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: device comprises five division units, four units of nonlinearity, nine multiplier units, two integrators, two subtractors, a timer (step voltage generator), five summators, multivibrator operating in standby mode, five delay units, OR gate, comparator, trigger, four memory elements, four couplers.

EFFECT: improved accuracy for determination of unknown values by implementation of mathematical model that allows considering dependence of failure function on time and on mode of the device usage.

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Description

The invention relates to computer technology, in particular to control devices, and can be used in experimental design work and the practice of operating products subject to aging, to determine the optimal timing of their maintenance.

Known devices [3, 4], allowing to determine the optimal values of the periods of maintenance of products. Their disadvantage is the limited scope, since they do not allow to take into account the aging factor of products. Devices [5, 6] make it possible to calculate the values of service periods, which ensure the obtaining of extreme values of the operational and technical characteristics of products taking into account the aging factor. However, these devices do not allow to take into account the difference in the rate of expenditure of the reliability potential when changing the mode of operation of the product, which reduces the accuracy of the results. Devices [7, 8] are designed to determine the optimal frequency of control and management of the technical condition of products, taking into account changes in the intensity of their failures depending on the mode of use. The disadvantage of devices [5, 6] is that the determination of the values of the output values is carried out without taking into account the aging factor of the product. The composition of the functional elements used in the claimed invention, the device [7, 8] are equivalent, and the composition of the output parameters is closer to the device [8].

In connection with the above, the prototype of the claimed invention adopted the device [8], containing a memory block, six valves, five adders, a multivibrator, two triggers, two accumulating adders, an OR circuit, four non-linearity blocks, a comparator, four multiplication blocks, two subtractors, four delay elements, four memory elements, two integrators and a divider.

The purpose of the proposed technical solution is to expand the scope of the device and improve the accuracy of determining the values of the desired values. The goal is achieved by implementing a mathematical model that allows you to take into account the dependence of the function of failures on time and on the mode of use of the product. The criterion for optimizing the product maintenance period is the maximum availability factor.

The process of applying a significant number of different types of products is cyclical. Each cycle includes the operation of the product in nominal mode and being in rest mode. Figure 1 presents a diagram of the operation of the product, including:

τ is the duration of the product application cycle (for example, one day);

t ₁ = τK _AND is the duration of use of the product in nominal mode, K _AND is the coefficient of use of the product for its intended purpose, 0 <K _AND <1. Moreover, the failure rate of the product has a value of λ ₁ ;

t ₂ = τ-t ₁ - the duration of rest after use (for example, technical equipment of enterprises working in one or two shifts, vehicles and much more). In this time interval, the failure rate is 0 <λ ₂ <λ ₁ [1].

To maintain the product in working condition, its maintenance is periodically carried out and the time τ _obs . At the same time, in-depth state monitoring is performed during the time τ _k1 , routine maintenance and restoration of the product’s performance in case of failure is detected, which takes time τ _c , and at the end of these works, a control check of the product’s condition is performed during the time τ _k2 . Note that the control of the technical condition is carried out in the conditions of the nominal operating mode of the product. Therefore, at time intervals τ _k1 and τ _k2 , the failure rate will be equal to λ ₁ . To carry out repair and restoration work, the product is put into rest mode, which corresponds to the failure rate λ ₂ . In connection with the foregoing, the total duration of maintenance is expressed as follows:

where P (T), P (τ _k1 + τ _k2 ), P (τ _in ) is the probability of failure-free operation of the product in the corresponding time interval.

циклов применения длительностью τ каждый, то естьThe duration of the service period T (Fig. 1) includes many $$i=\overline{\mathrm{one},n}$$

application cycles of duration τ each, i.e.

The duration T _c the product service cycle is

The probability of failure-free operation of the product on the time interval T is expressed as follows:

An important failure-free parameter is the failure rate. The theory and practice of operating a wide class of serviced products shows that aging of products is accompanied by an increase in this intensity. To determine the uptime of such products, the Rayleigh distribution law is applicable. Moreover, the failure rate λ (t) and the probability of failure-free operation of the product P (t) are determined as follows [2]:

where σ is the Rayleigh distribution parameter.

In this regard, the following occurs:

The working time of the product T _f on the time interval is determined by the formula

A comprehensive indicator of the quality of functioning is the availability coefficient, expressed by the following ratio:

Studies have shown that there is a service period in which K _G (T) has a global extremum. In this regard, the task of determining the optimal period for managing the technical condition of the product is expressed as follows:

The proposed mathematical model can be implemented in hardware using a device, a diagram of which is shown in Figure 2.

The device contains: first 1, second 3, third 20, fourth 22 and fifth 25 division blocks, first 2, second 4, third 21 and fourth 26 non-linearity blocks, first 5, second 6, third 7, fourth 9, fifth 19, sixth 24, seventh 29, eighth 30 and ninth 31 multiplication blocks, first 8 and second 11 integrators, first 10 and second 33 subtracters, time sensor (step voltage generator) 12, first 13, second 23, third 27, fourth 28 and fifth 32 adders, multivibrator 14, first 15, second 34, third 37, fourth 40 and fifth 45 delay elements, OR circuit 16, comparator 17, trigger 18, first 35, second 38, third 41 and fourth 43 memory elements, first 36, second 39, third 42 and fourth 44 gates.

The schemes of the used functional blocks of the representation device in [9], in particular, memory elements can be constructed according to the scheme 4-5-1, and non-linearity blocks according to the scheme 3-4-2.

The process of solving problem (13) has an iterative nature. In the first cycle of operation (i = 1), the devices T = τ, T ₁ = τ ₁ , T ₂ = τ-τ ₁ , and in each subsequent cycle the parameters T, T ₁ , T ₂ increase in accordance with (2) and (3 ) Accordingly, the values of the quantities P (T), T _f (T), K _G (T), τ _obs (T) change.

, $$2{\sigma }_2^2$$

, K_И, τ_в, τ_к1, τ_к2 подаются соответственно на 1, 2, 3, 5, 6, 7 его входы.Before starting the device, the source data: $$2{\sigma }_{\mathrm{one}}^2$$

, $$2{\sigma }_2^2$$

, K _И , τ _в , τ _к1 , τ _к2, respectively, are supplied to its inputs 1, 2, 3, 5, 6, 7.

из блока 5 передается на второй вход первого блока деления 1, на первый вход которого с первого входа устройства поступает сигнал $$2{\sigma }_1^2$$

. Этот сигнал поступает и на первый вход пятого блока деления 25. Выходной сигнал $$t_1^2/2{\sigma }_1^2$$

блока деления 1 передается на первый вход первого блока нелинейности 2, в котором формируется и передается на первые входы третьего блока умножения 7 и первого интегратора 8 значение величины P₁(t₁). Выходной сигнал t₂=τ-t₂ первого вычитателя 10 передается на первый вход второго интегратора 11, а также на оба входа второго блока умножения 6. Результат перемножения $$t_2^2$$

из блока умножения 6 передается на второй вход второго блока деления 3, на первый вход которого, как и на первый вход третьего блока деления 20, со второго входа устройства поступает значение сигнала $$2{\sigma }_2^2$$

. Выходной сигнал второго блока деления 3 передается на первый вход второго блока нелинейности 4, с выхода которого значение величины P₂(t₂) передается на вторые входы третьего блока умножения 7 и второго интегратора 11. В блоке умножения 7 формируется сигнал, соответствующий произведению Р₁(t₁)·Р₂(t₂), и передается на второй вход девятого блока умножения 31. Выходной сигнал второго интегратора 11 передается на второй вход, а выходной сигнал первого интегратора 8 - на первый вход первого сумматора 13. В сумматоре 13 реализуется соотношение (11) и его выходной сигнал передается через второй элемент задержки 34 в первый элемент памяти 35, а также в четвертый блок деления 22 через его первый вход.Work begins when the Start signal arrives at the fourth input of the device. This signal is fed to the first input of trigger 18, translating it into a zero state. At the same time, the “Start” signal, passing through the OR 16 circuit, initiates the generation by the waiting multivibrator 14 of the control action, according to which the first 2, second 4, third 21 and fourth 26 non-linearity blocks are reset (zeroed) during the time Δt as well as the first 8 and second 11 integrators. In addition, the “Start” signal, delayed by the first delay element 15 by the time Δt, starts the time sensor 12. This sensor sets the sequence of possible values τ _i of the product maintenance period τ _i = τ _i-1 + τ, in increments of τ, where i = 1, 2, 3 .... The initial signal T = τ from the output of the time sensor 12 is transmitted through the third delay element 37 to the second memory element 38, to the first inputs of the third adder 27 and the first subtractor 10, and also to the second input of the fourth multiplication block 9. From the third input of the device to the first input block 9 receives the value of the utilization of the product for the purpose of K _AND . The result of multiplication K _AND · τ = t ₁ from the output of block 9 is transmitted to the second inputs of the first integrator 8 and the first subtractor 10, as well as to both inputs of the first block of multiplication 5. The signal corresponding to $$t_{\mathrm{one}}^2$$

from block 5 is transmitted to the second input of the first block of division 1, the first input of which from the first input of the device receives a signal $$2{\sigma }_{\mathrm{one}}^2$$

. This signal is fed to the first input of the fifth division unit 25. The output signal $$t_{\mathrm{one}}^2/2{\sigma }_{\mathrm{one}}^2$$

unit 1 is transmitted to the first input of the first non-linearity unit 2, in which the value of P ₁ (t ₁ ) is generated and transmitted to the first inputs of the third multiplication unit 7 and the first integrator 8. The output signal t ₂ = τ-t _{2 of the} first subtractor 10 is transmitted to the first input of the second integrator 11, as well as to both inputs of the second block of multiplication 6. The result of multiplication $$t_2^2$$

from the multiplication unit 6 is transmitted to the second input of the second division unit 3, the first input of which, like the first input of the third division unit 20, the signal value is received from the second input of the device $$2{\sigma }_2^2$$

. The output signal of the second division unit 3 is transmitted to the first input of the second non-linearity unit 4, from the output of which the value of P ₂ (t ₂ ) is transmitted to the second inputs of the third multiplication unit 7 and the second integrator 11. In the multiplication unit 7, a signal is generated corresponding to the product P ₁ (t ₁ ) · Р ₂ (t ₂ ), and is transmitted to the second input of the ninth multiplication block 31. The output signal of the second integrator 11 is transmitted to the second input, and the output signal of the first integrator 8 is transmitted to the first input of the first adder 13. In the adder 13 is implemented relation (11) and its yhodnoy signal is transmitted through the second delay element 34 in the first memory element 35 and the fourth dividing unit 22 via its first input.

из блока умножения 19 передается в третий блок деления 20, где формируется и передается на второй вход третьего блока нелинейности 21 величина $$t_{в}^2/2{\sigma }_2^2$$

. Сигнал, соответствующий величине Р(τ_в), с выхода третьего блока нелинейности 21 передается на второй вход седьмого блока умножения 29. На первый вход второго сумматора 23 с шестого входа устройства поступает значение величины τ_k1. С седьмого входа устройства на вторые входы четвертого 28 и второго 23 сумматоров передается значение величины τ_k2. Суммарный сигнал τ_k1+τ_k2 с выхода сумматора 23 поступает на оба входа шестого блока умножения 24 и на второй вход пятого сумматора 32. Результат перемножения (τ_k1+τ_k2)² с выхода шестого блока умножения 24 передается на второй вход пятого блока деления 25. Выходной сигнал $${({\tau }_{k1}+{\tau }_{k2})}^2/2{\sigma }_1^2$$

с выхода блока деления 25 поступает на второй вход четвертого блока нелинейности 26, с выхода которого значение величины P(τ_k1+τ_k2) передается на второй вход восьмого блока умножения 30. Сигнал, соответствующий сумме τ_в+τ_k2, с выхода четвертого сумматора 28 поступает на первый вход седьмого блока умножения 29, выходной сигнал которого (τ_в+τ_k2)·Р(τ_в) передается на первый вход восьмого блока умножения 30. В блоке умножения 30 формируется сигнал, соответствующий величине (τ_в+τ_k2)·Р(τ_в)·Р(τ_в+τ_k2), который передается на первый вход девятого блока умножения 31. Выходной сигнал (τ_в+τ_k2)·Р(T)·Р(τ_в)·Р(τ_k1+τ_k2) блока умножения 31 поступает на второй вход второго вычитателя 33, на первый вход которого с выхода пятого сумматора 32 приходит сигнал, соответствующий сумме τ_k1+τ_в+τ_k2. В результате во втором вычитателе 33 формируется согласно (1) значение величины τ_обс, которое передается непосредственно на второй вход третьего сумматора 27 и через пятый элемент задержки 45 на информационный вход четвертого элемента памяти 43. В третьем сумматоре 27 осуществляется вычисление согласно (4) значения времени T_Ц, которое передается на второй вход четвертого блока деления 22. В блоке 22 осуществляется вычисление текущего значения K_Г(T) согласно (12), оно передается непосредственно на первый вход компаратора 17, а через четвертый элемент задержки 40 на информационный вход третьего элемента памяти 41 и на второй вход компаратора 17. В компараторе 17 происходит сравнение значений K_Г(T_i) и K_Г(T_i-1). В первом цикле работы устройства выполнится условие K_Г(T_i)>K_Г(T_i-1). Поэтому управляющий сигнал компаратора 17 появится на его первом выходе и через схему ИЛИ 16 поступит непосредственно на вход мультивибратора 14, а через первый элемент задержки 15 - на вход датчика времени 12. При этом на выходе датчика времени 12 будет действовать сигнал, соответствующий величине T=2τ, и процесс вычисления значений искомых величин, т.е. работы устройства, повторится. Так будет продолжаться пока K_Г(T_i) будет больше либо равным K_Г(T_i-1).At the same time, from the fifth input of the device to the first inputs of the fourth 28 and fifth 32 adders, as well as to the first and second inputs of the fifth block of multiplication 19, a value of τ _{in is} received. Multiplication result $${\tau }_{\mathrm{at}}^2$$

from the multiplication unit 19 is transferred to the third division unit 20, where the value is formed and transmitted to the second input of the third non-linearity unit 21 $$t_{\mathrm{at}}^2/2{\sigma }_2^2$$

. The signal corresponding to the value of P (τ _in ) from the output of the third block of nonlinearity 21 is transmitted to the second input of the seventh multiplication unit 29. The value of τ _{k1 is} supplied to the first input of the second adder 23 from the sixth input of the device. From the seventh input of the device to the second inputs of the fourth 28 and second 23 adders is transmitted the value of τ _k2 . The total signal τ _k1 + τ _k2 from the output of the adder 23 is fed to both inputs of the sixth multiplication block 24 and to the second input of the fifth adder 32. The result of multiplication (τ _k1 + τ _k2 ) ² from the output of the sixth multiplication block 24 is transmitted to the second input of the fifth division block 25. The output signal $${({\tau }_{k\mathrm{one}}+{\tau }_{k2})}^2/2{\sigma }_{\mathrm{one}}^2$$

from the output of the division unit 25 it enters the second input of the fourth block of nonlinearity 26, from the output of which the value of the quantity P (τ _k1 + τ _k2 ) is transmitted to the second input of the eighth multiplication unit 30. The signal corresponding to the sum of τ _in + τ _k2 from the output of the fourth adder 28 is supplied to the first input of the seventh multiplication block 29, the output signal of which (τ _in + τ _k2 ) · P (τ _in ) is transmitted to the first input of the eighth multiplication block 30. In the multiplication block 30, a signal is generated corresponding to the value (τ _in + τ _k2 ) · P (τ _in ) · P (τ _in + τ _k2 ), which is transmitted to the first input of the ninth block of the mind knives 31. The output signal (τ _in + τ _k2 ) · P (T) · P (τ _in ) · P (τ _k1 + τ _k2 ) of the multiplication unit 31 is fed to the second input of the second subtractor 33, the first input of which is from the output of the fifth adder 32 receives a signal corresponding to the sum of τ _k1 + τ _in + τ _k2 . As a result, in the second subtractor 33, according to (1), a value of τ _obs is generated, which is transmitted directly to the second input of the third adder 27 and through the fifth delay element 45 to the information input of the fourth memory element 43. In the third adder 27, the value is calculated according to (4) time T _C , which is transmitted to the second input of the fourth division unit 22. In block 22, the current value K _G (T) is calculated according to (12), it is transmitted directly to the first input of the comparator 17, and through the fourth element nt delay 40 to the information input of the third memory element 41 and to the second input of the comparator 17. In the comparator 17, the values of K _G (T _i ) and K _G (T _i-1 ) are compared. In the first cycle of the device, the condition K _G (T _i )> K _G (T _i-1 ) is satisfied. Therefore, the control signal of the comparator 17 will appear at its first output and through the OR circuit 16 will go directly to the input of the multivibrator 14, and through the first delay element 15 to the input of the time sensor 12. At the same time, the signal corresponding to the value T = 2τ, and the process of calculating the values of the sought quantities, i.e. device operation will be repeated. This will continue until K _G (T _i ) is greater than or equal to K _G (T _i-1 ).

As soon as at a certain value T = nτ, n = 2,3, ... as a result of the comparison in comparator 17, it turns out that K _Г (T _i ) <K _Г (T _i-1 ) the control signal appears at the second output of comparator 17. This the signal will translate the trigger 18 into a single state. Its output signal will ensure the reading of the contents of the first 35, second 38, third 41 and fourth 43 memory elements, will open the valves 36, 39, 42 and 44, as well as transfer the time sensor 12 to its original (zero) state. As a result of this, the calculated values of the values of T _f , τ, K _G , T _obs arrive respectively at the first, second, third and fourth outputs of the device. This completes the operation of the device.

An increase in the failure rate of the product entails a shift in the optimal period for controlling the technical condition of the product to lower values. Therefore, each subsequent optimal value of the period must be found taking into account changes in the failure rate.

The positive effect that the proposed technical solution provides is that the device allows you to determine the values of the periods of control of the technical condition of the product, ensuring the maximum possible readiness of the product for use, taking into account the increase in the failure rate of the product during its operation, as well as the difference in the values of this intensity at finding the product in the operating mode and in the rest mode after application.

Information sources

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3. Grishin V.D., Zinoviev S.V., Sokolov B.V., Maydanovich O.V. Patent RU No. 2452027. IPC G07C 3/08, 2012.

4. Sokolov B.V., Starodubov V.A., Grishin V.D., Tsivirko E.G. Patent RU No. 2476935, IPC G07C 3/08, 2013.

5. Grishin V.D., Pavlov A.N., Mikhailov E.P. Patent RU No. 2343544, IPC G07C 3/08, 2009.

6. Grishin V.D., Kudryashov A.N., Timoshenko D.V. Patent RU No. 2347272, IPC G07C 3/08, 2009.

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Claims (1)

A device for determining the optimal period of control of the technical condition of the product, containing the first nonlinearity block, the output of which is connected to the first inputs of the first integrator and the third multiplication block, the second input of which is connected to the output of the second nonlinearity block and to the second input of the second integrator, and the output is connected to the second input of the ninth multiplication block, the first input of the second integrator is connected to the output of the first subtracter, and the output is to the second input of the first adder, the first input of which is connected to the output m of the first integrator, and the output directly with the first input of the fourth division block and through the second delay element with the information input of the first memory element, the output of which is connected to the information input of the first valve, the output of which is the first output of the device, the second output of which is the output of the second valve , the information input of which is connected to the output of the second memory element, the information input of which is connected to the output of the third delay element, the third output of the device is the output a gate whose information input is connected to the output of the third memory element, the information input of which through the fourth delay element is connected to the output of the fourth division unit and to the first input of the comparator, the first output of which is connected to the second input of the OR circuit, the output of which is connected to the input of the multivibrator, and the first input, which is the fourth input of the device, is connected to the first input of the trigger, the second input of which is connected to the second output of the comparator, and the output is connected to the control inputs of the first, second, the third and fourth memory elements, the first, second, third and fourth gates, the fourth output of the device is the output of the fourth gate, the input of which is connected to the output of the fourth memory element, the information input of which is connected to the output of the fifth delay element, the input of which is connected to the second through the third adder the input of the fourth division block, and directly with the output of the second subtractor, the first input of which is connected to the output of the fifth adder, the second input of which is connected to the output of the second sum RA, the second input of which is connected to the second input of the fourth adder, the output of which is connected to the first input of the seventh multiplication block, the second input of which is connected to the output of the third nonlinearity block, the fourth nonlinearity block, the eighth multiplication block, the output of which is connected to the first input of the ninth multiplication block, characterized in that a time sensor, a first delay element, four division blocks and five multiplication blocks are introduced into it, the first input of the device being connected to the first inputs of the fifth division block and the first block division, the second input of which is connected to the output of the first block of multiplication, and the output to the first input of the first block of nonlinearity, the second input of which is connected to the output of the multivibrator, with the first inputs of the third and fourth blocks of nonlinearity, with the third inputs of the first and second integrators, as well as the second input of the second nonlinearity block, the first input of which is connected to the output of the second division block, the first input of which is connected to the first input of the third division block and is the second input of the device, and the second input is connected to the output of the second multiplication block, both inputs of which are connected to the output of the first subtractor, the second input of which is connected to the second input of the first integrator, to the first and second inputs of the first multiplication block and to the output of the fourth multiplication block, the first input of which is the third input of the device, and the second input connected to the first input of the first subtractor, with the input of the third delay element, with the first input of the third adder and with the output of the time sensor, the second input of which is connected to the trigger output, and the first input through the first e delay element - to the output of the OR circuit, the fifth input of the device is connected to the first inputs of the fourth and fifth adders and to both inputs of the fifth multiplication block, the output of which is connected to the second input of the third division block, the output of which is connected to the second input of the third nonlinearity block, the first and second the inputs of the second multiplication block are respectively the sixth and seventh inputs of the device, and the output is connected to both inputs of the sixth multiplication block, the output of which is connected to the second input of the fifth division block, the output of which is under is connected to the second input of the fourth non-linearity block, the output of which is connected to the first input of the eighth multiplication block, the first input of which is connected to the output of the seventh multiplication block, the output of the ninth multiplication block is connected to the second input of the second subtracter, the second input of the comparator is connected to the output of the fourth delay element.

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