RU2519035C1 - Controlled selective amplifier - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: controlled selective amplifier comprises an input signal source, two input transistors, two current-stabilising two-terminal elements, a power supply, a current mirror, two balancing capacitors, a resistor and a buffer amplifier. The input transistors used are field-effect transistors, whose sources correspond to the emitter, the drain to the collector and the gate to the base of a bipolar transistor.

EFFECT: lower overall power consumption owing to higher attenuation of the input signal in the low frequency range with high stability of the Q factor of the amplitude-frequency characteristic of the selective amplifier and voltage gain at quasi-resonance frequency f₀.

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Description

The present invention relates to the field of radio engineering and communications and can be used in devices for filtering radio signals, television, radar, etc.

Integrated operational amplifiers with special RC correction elements that form the amplitude-frequency characteristic of the resonant type are widely used today in the tasks of extracting high-frequency signals [1, 2]. However, the classical construction of such selective amplifiers (DUTs) is accompanied by significant energy losses, which are mainly used to ensure the static mode of a sufficiently large number of secondary transistors forming an operational amplifier [1, 2]. In this regard, it is very urgent to build selective amplifiers on two or three transistors, providing a narrow spectrum of signals with a sufficiently high quality factor (Q) of the resonance characteristic (Q = 2 ÷ 40) with low power consumption.

Known schemes are DUTs integrated into the architecture of RC filters based on bipolar transistors, which provide the formation of the amplitude-frequency characteristics of the voltage gain in a given frequency range Δf = f _in -f _n [3-10]. Moreover, their upper f _in and lower f _n boundary frequencies are formed by special corrective capacitors.

The closest prototype of the claimed device is a selective amplifier, presented in patent US 4843343, figure 1. It contains an input signal source 1 connected to the base of the first 2 input transistor, the second 3 input transistor, the base of which is connected to the output 4 of the device, and the emitter is connected to the emitter of the first 2 input transistor and through the first 5 current-stabilizing two-terminal device is connected to the first 6 bus of the power source , current mirror 7, coordinated with the second 8 bus power supply, the output of which 9 through the second 10 current-stabilizing two-terminal connected to the first 6 bus power source, the first 11 correction capacitor is included first AC coupling between the output of the current mirror 7, 9 and power supply common bus 12, a second adjustment capacitor 13.

Significant disadvantages of the Yiwu prototype of figure 1 are as follows:

- to ensure large attenuation of the output signal in the low frequency range (<< f ₀ ) in the structure of the DUT of Fig. 1, it is necessary to use the connection of the signal source 1 to the base of the first 2 input transistor through a special isolation capacitor, the capacitance of which should be significantly larger than the capacities of the frequency setting circuit (first 11 and second 13 correction capacitors). In addition, in this case, an additional mode-setting resistor is required in the base circuit of the input transistor 2;

- for cascading (serial connection) of such DUT schemes into bandpass filters, it is necessary to use additional buffer amplifiers;

- in its structure, obtaining high quality factors is problematic. When implementing high Q factors (Q = 3 ... 10), it is necessary to use a large value of the resistance of the current-stabilizing two-terminal 10, which increases the proportional effect on the operation of the parasitic capacitance of the collector junction of transistor 3 and the output capacitance of the current mirror. Ultimately, this limits the operating frequency range of the DUT prototype.

The main objective of the invention is to increase the attenuation of the output signal in the low frequency range with an increased and sufficiently stable quality factor Q of the amplitude-frequency characteristic (AFC) of the DUT and a large voltage gain (K ₀ ) at the quasi-resonance frequency f ₀ .

The problem is solved in that in the selective amplifier of figure 1, containing an input signal source 1 connected to the base of the first 2 input transistor, the second 3 input transistor, the base of which is connected to the output 4 of the device, and the emitter is connected to the emitter of the first 2 input transistor and through the first 5, the current-stabilizing two-terminal is connected to the first 6 bus of the power supply, a current mirror 7, coordinated with the second 8 bus of the power supply, the output of which 9 through the second 10 current-stabilizing two-terminal is connected to the first 6 another power source, the first 11 correction capacitor connected by alternating current between the output 9 of the current mirror 7 and the common bus of the power supplies 12, the second 13 correction capacitor, new elements and connections are provided - field-effect transistors are used as the first 2 and second 3 input transistors, the source of which corresponds to the emitter, the drain to the collector, and the gate to the base of the bipolar transistor, and the drain of the second 3 input transistor is connected to the input 14 of the current mirror 7, the output 9 of the current mirror 7 is connected to the input the house of the additional buffer amplifier 15, the output of which is connected to the output of the device 4 through the second 13 correction capacitor, the drain of the first 2 input transistor is connected to the second 8 bus of the power supply, and the output of the device 4 is shunted by alternating current with an additional resistor 16.

The amplifier circuit of the prototype is shown in figure 1. Figure 2 presents a diagram of the claimed IU in accordance with the claims.

Figure 3 presents a diagram of the DUT of figure 2 with a specific implementation of the current mirror 7 and the buffer amplifier 15.

Figure 4 shows a diagram of the DUT of figure 3 in a Cadence computer simulation environment on SiGe integrated transistor models.

Figure 5 shows the logarithmic amplitude-frequency characteristic of the DUT of figure 4 in the frequency range 0.2-5 GHz at different values of the current I _{0 of the} current-stabilizing two-terminal network 5.

Figure 6 shows the logarithmic phase-frequency characteristic of the DUT of figure 4 in the frequency range 0.2-5 GHz at different current values of 1 ₀ two-terminal 5.

Figures 7 and 8 show the amplitude-frequency (Fig. 7) and phase-frequency (Fig. 8) characteristics of the DUT of Fig. 4 in the frequency range 0.5-2 GHz at different current values of the two-terminal network 20 (I ₂₀ = I _k ).

The controlled selective amplifier contains an input signal source 1 connected to the base of the first 2 input transistor, a second 3 input transistor, the base of which is connected to the output 4 of the device, and the emitter is connected to the emitter of the first 2 input transistor and connected through the first 5 current-stabilizing two-terminal to the first 6 bus power supply, current mirror 7, coordinated with the second 8 bus power supply, the output of which 9 through the second 10 current-stabilizing two-terminal connected to the first 6 bus power supply, the first 11 a correction capacitor connected by alternating current between the output 9 of the current mirror 7 and the common bus of the power supplies 12, the second 13 is a correction capacitor. As the first 2 and second 3 input transistors, field effect transistors are used, the source of which corresponds to the emitter, the drain to the collector, and the gate to the base of the bipolar transistor, and the drain of the second 3 input transistor is connected to the input 14 of the current mirror 7, the output 9 of the current mirror 7 is connected to the input of the additional buffer amplifier 15, the output of which is connected to the output of the device 4 through the second 13 correction capacitor, the drain of the first 2 input transistor is connected to the second 8 bus of the power source, and the output of the device 4 shun It is ac coupled with an additional resistor 16.

In figure 3, the current mirror 7 is implemented on transistors 17 and 18, and the additional buffer amplifier 15 contains a transistor 19 and a current source 20. A transistor 21 is included in the drain circuit of transistor 2, which increases the symmetry of the circuit.

Consider the work of the proposed IU on the example of the analysis of a particular version of its construction (figure 3).

Source input signal _Rin u (1) changes the current sources (drains) of MOS transistors 2 and 3. The drain current of transistor 3 changes the base current and emitter of transistor 17. A similar change in the collector current of transistor 17 because of the nature of its collector load leads to increased low frequency signals and attenuation of high-frequency signals in the base circuit of transistor 19. Converting the voltage drop across the two-terminal 10 and capacitor 11 to the voltage of the emitter circuit of transistor 19 provides (due to the differentiating properties of the circuit formed by the by connecting the capacitor 13 and the resistor 16) the dependence of the output voltage of the DUT (node 4), corresponding to the characteristic of the selective amplifier. Thus, the regenerative properties of the feedback loop of the DUT of Fig. 3 form its maximum depth at only one frequency, which coincides with the frequency of the quasi-resonance of the selective amplifier (f ₀ ). The specified property of the DUT provides an increase in the realized quality factor (Q) and gain (K ₀ ) without changing f ₀ .

Integrated transmission ratio DUT as the ratio of output voltage u = u _{vyh.4 O} (output apparatus 4) to the input voltage u _Rin of the amplifier 2 is determined by a formula which can be obtained by electronic circuits assays

$$K{\left(jf\right)}_{12}=\frac{u_{\mathrm{at}sx\mathrm{.four}}}{u_{\mathrm{at}x}}=K_0\frac{jf\frac{f_0}{\mathrm{<figure-callout\; id="0"\; label="Q\; f"\; filenames="00000024.png,00000027.png"\; state="\{\{state\}\}">Q\; </figure-callout>}}}{f_{}^{}},\left(\mathrm{one}\right)$$

where f is the frequency of the input signal;

f ₀ is the frequency of the quasi-resonance of the DUT;

Q is the quality factor of the frequency response of the selective amplifier;

To ₀ is the gain of the DUT by voltage at the frequency of quasi-resonance f ₀ . Moreover

$${\mathrm{<figure-callout\; id="0"\; label="f"\; filenames="00000024.png,00000027.png"\; state="\{\{state\}\}">f</figure-callout>}}_0=\frac{\mathrm{one}}{2\pi \sqrt{C_{13}{C}_{\mathrm{eleven}}{R}_{10}\left(R_{\mathrm{at}sx\mathrm{fifteen}}+R_{16}\right)}},\left(2\right)$$

$$Q^{-\mathrm{one}}=d_p=\sqrt{\frac{C_{\mathrm{eleven}}{R}_{10}}{C_{13}\left({\mathrm{<figure-callout\; id="16"\; label="R"\; filenames="00000022.png,00000023.png"\; state="\{\{state\}\}">R</figure-callout>}}_{16}+R_{\mathrm{at}sx\mathrm{fifteen}}\right)}}+\sqrt{\frac{C_{13}\left({\mathrm{<figure-callout\; id="16"\; label="R"\; filenames="00000022.png,00000023.png"\; state="\{\{state\}\}">R</figure-callout>}}_{16}+R_{\mathrm{at}sx\mathrm{fifteen}}\right)}{C_{\mathrm{eleven}}{R}_{10}}}\left(\mathrm{one}-S\frac{R_{16}{R}_{10}}{{\mathrm{<figure-callout\; id="16"\; label="R"\; filenames="00000022.png,00000023.png"\; state="\{\{state\}\}">R</figure-callout>}}_{16}+R_{\mathrm{at}sx\mathrm{fifteen}}}\right),\left(3\right)$$

$${\mathrm{<figure-callout\; id="0"\; label="K"\; filenames="00000024.png,00000027.png"\; state="\{\{state\}\}">K</figure-callout>}}_0=Q\cdot S\sqrt{R_{16}{R}_{10}}\sqrt{\frac{C_{13}}{C_{\mathrm{eleven}}}}\frac{\mathrm{one}}{\sqrt{\mathrm{one}+\raisebox{1ex}{$R_{\mathrm{at}sx\mathrm{fifteen}}$}\!\left/ \!\raisebox{-1ex}{${\mathrm{<figure-callout\; id="16"\; label="R"\; filenames="00000022.png,00000023.png"\; state="\{\{state\}\}">R</figure-callout>}}_{16}$}\right.}},\left(\mathrm{four}\right)$$

where R _o15 , S is the output impedance of the buffer amplifier 15 and the slope of the current mirror 7.

The structure feature of the DUT of FIG. 2 allows you to select the optimal values of the parameters of the circuit elements

$$m=\sqrt{\frac{C_{\mathrm{eleven}}{R}_{10}}{C_{13}\left(R_{16}+R_{\mathrm{at}sx\mathrm{fifteen}}\right)}},\left(5\right)$$

R ₁₆ = kR _out15 ,

$$m_{opt}=\frac{\mathrm{one}}{2}{d}_p;k_{opt}=\frac{\mathrm{one}}{\mathrm{four}}{\mathrm{<figure-callout\; id="2"\; label="d\; p"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">d\; </figure-callout>}}_p^{}.\left(6\right)$$

Then for the circuit of FIG. 3

$${\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\approx 2\frac{h_{11.17}}{{\mathrm{<figure-callout\; id="17"\; label="\alpha "\; filenames="00000023.png"\; state="\{\{state\}\}">\alpha </figure-callout>}}_{17}}\frac{\mathrm{one}+k}{k},\left(7\right)$$

Therefore, the choice of m = m _{opt is} carried out through the ratio of capacitances of capacitors C ₁₃ and C ₁₁

$$\raisebox{1ex}{$C_{\mathrm{eleven}}$}\!\left/ \!\raisebox{-1ex}{${\mathrm{<figure-callout\; id="13"\; label="C"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">C</figure-callout>}}_{13}$}\right.=n,\left(8\right)$$

можно найтиat $$\raisebox{1ex}{$C_{10}$}\!\left/ \!\raisebox{-1ex}{${\mathrm{<figure-callout\; id="16"\; label="C"\; filenames="00000022.png,00000023.png"\; state="\{\{state\}\}">C</figure-callout>}}_{16}$}\right.=l$$

can find

$$n=\frac{\mathrm{one}}{l}\left(\mathrm{one}+\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$k$}\right.\right)\frac{{\mathrm{<figure-callout\; id="2"\; label="d\; p"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">d\; </figure-callout>}}_p^{}}{\mathrm{four}}.\left(9\right)$$

легко реализуемые параметрические условия.For example, when choosing k≈3, we get l≈3 / k and $$n=\frac{{\mathrm{<figure-callout\; id="2"\; label="d\; p"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">d\; </figure-callout>}}_p^{}}{3}$$

easily implemented parametric conditions.

The combination of structural and parametric features of the circuit of the claimed device allows you to configure its frequency quasi-resonance f ₀ . So, to control the frequency of quasi-resonance f ₀ through a change in the output resistance of the buffer amplifier 15, it is necessary to ensure the dependence of R _o15 = φ _T / I _k (Fig. 3). Given that R ₁₆ = kR _out15 , the implementation of constraints (6) leads to the following additional parametric condition:

$${\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">R</figure-callout>}}_2=2h_{11.17}\cdot \frac{\mathrm{one}+k}{{\alpha }_{17}k}\left(\mathrm{one}-\frac{\mathrm{one}}{\mathrm{four}}{d}_p^2\right)=\frac{\mathrm{one}}{2}{h}_{11.17}\left(\mathrm{four}-d_p^2\right)\frac{\mathrm{one}+k}{{\alpha }_{17}k}\approx \frac{2h_{11.17}}{{\mathrm{<figure-callout\; id="17"\; label="\alpha "\; filenames="00000023.png"\; state="\{\{state\}\}">\alpha </figure-callout>}}_{17}}\cdot \frac{\mathrm{one}+k}{k},\left(10\right)$$

where α ₁₇ , h _11.17 - low-signal parameters of the transistor 17.

For example, to change f ₀ by ± 10% it is advisable to have

$$k\approx 3{\mathrm{<figure-callout\; id="2"\; label="R"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">R</figure-callout>}}_2\approx \frac{8}{3}{h}_{11.17}\approx 3h_{11.17}.\left(\mathrm{eleven}\right)$$

(при $$\frac{R_{10}}{R_{16}}=1$$

) задаются «перекосом» емкостей С_п/С₁₃=n при сохранении соотношенийThen the parameters d _p and $$m_{opt}=\frac{\mathrm{one}}{2}{d}_p$$

(at $$\frac{R_{10}}{{\mathrm{<figure-callout\; id="16"\; label="R"\; filenames="00000022.png,00000023.png"\; state="\{\{state\}\}">R</figure-callout>}}_{16}}=\mathrm{one}$$

) are set by the “skew” of the capacitance C _p / C ₁₃ = n while maintaining the ratios

$$\frac{n{R}_{10}}{{\mathrm{<figure-callout\; id="16"\; label="R"\; filenames="00000022.png,00000023.png"\; state="\{\{state\}\}">R</figure-callout>}}_{16}+R_{\mathrm{at}sx\mathrm{fifteen}}}=nl\cdot \frac{\mathrm{one}}{\mathrm{one}+\mathrm{one}/k}=nl\frac{k}{\mathrm{one}+k}=\frac{\mathrm{one}}{\mathrm{four}}{\mathrm{<figure-callout\; id="2"\; label="d\; p"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">d\; </figure-callout>}}_p^{},\left(12\right)$$

. $$n=\frac{\mathrm{one}}{l}\left(\mathrm{one}+\raisebox{1ex}{$\mathrm{one}$}\!\left/ \!\raisebox{-1ex}{$k$}\right.\right)\frac{{\mathrm{<figure-callout\; id="2"\; label="d\; p"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">d\; </figure-callout>}}_p^{}}{\mathrm{four}}$$

.

и $$l\approx \frac{3h_{11.17}}{k{R}_{вых15}}\approx \frac{3}{k}$$

For the case when $$k\approx 3$$

and $$l\approx \frac{3h_{11.17}}{k{R}_{\mathrm{at}sx\mathrm{fifteen}}}\approx \frac{3}{k}$$

we get that

$$n=\frac{\mathrm{one}}{3}\left(k+\mathrm{one}\right)\frac{{\mathrm{<figure-callout\; id="2"\; label="d\; p"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">d\; </figure-callout>}}_p^{}}{\mathrm{four}}\approx \frac{\mathrm{four}}{3}\frac{{\mathrm{<figure-callout\; id="2"\; label="d\; p"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">d\; </figure-callout>}}_p^{}}{\mathrm{four}}=\frac{{\mathrm{<figure-callout\; id="2"\; label="d\; p"\; filenames="00000021.png,00000022.png"\; state="\{\{state\}\}">d\; </figure-callout>}}_p^{}}{3}.\left(13\right)$$

The circuit is tuned to the required quality factor Q in accordance with relation (3) by changing the slope S through a constant current source I ₅ . For the circuit of Fig. 3, the parameter S = α ₁₇ / h _11.17 ≈φ _T / I ₀ and, as can be seen from relation (2), the mode dependence of the slope S does not change the value of f ₀ .

Thus, the proposed circuitry solution provides a non-iterative procedure for tuning the DUT while maintaining high asymptotic attenuation in the low-frequency region (f << f ₀ ) and zero operating (constant) input and output voltages of the circuit. Additionally, we note that the selection (implementation) of the above parameters does not require significant voltage of the power source.

Presented in figure 5-8, the simulation results of the proposed IU confirm these properties.

Thus, the claimed circuit design solution of the DUT is characterized by higher values of the gain K ₀ at the frequency of the quasi-resonance f ₀ , increased values of the Q factor Q, characterizing its selective properties, as well as a higher attenuation of the output signal in the low frequency range.

BIBLIOGRAPHIC LIST

1. Design of Bipolar Differential OpAmps with Unity Gain Bandwidth up to 23 GHz \ N.Prokopenko, A. Budyakov, K.Schmalz, C.Scheytt, P. Ostrovskyy \\ Proceeding of the 4-th European Conference on Circuits and Systems for Communications - ECCSC'08 / - Politehnica University, Bucharest, Romania: July 10-11, 2008. - pp. 50-53.

2. Microwave SF blocks of communication systems based on fully differential operational amplifiers. / Prokopenko NN, Budyakov AS, K. Schmalz, C. Scheytt. // Problems of the development of promising micro- and nanoelectronic systems - 2010. Proceedings / under the general. ed. Academician of the Russian Academy of Sciences A.L. Stempkovsky. - M .: IPPM RAS, 2010. - P.583-586.

3. Patent US 4843343.

4. Patent US 4,590,435, fig. 5.

5. Patent US 4999585, fig. 2.

6. Patent US 6307438, fig. 2.

7. Patent US 4267518, fig. 4.

8. Patent WO 03052925.

9. Patent application US 2008/0246538, fig. 3.

10. Patent application US 2010/0201437.

Claims (1)

A controlled selective amplifier containing an input signal source 1 connected to the base of the first 2 input transistor, the second 3 input transistor, the base of which is connected to the output 4 of the device, and the emitter is connected to the emitter of the first 2 input transistor and connected through the first 5 current-stabilizing two-terminal to the first 6 bus power supply, current mirror 7, consistent with the second 8 bus power supply, the output of which 9 through the second 10 current-stabilizing two-terminal connected to the first 6 bus power source, the first 11 a correction capacitor connected by alternating current between the output 9 of the current mirror 7 and the common bus of the power sources 12, the second 13 is a correction capacitor, characterized in that as the first 2 and second 3 input transistors, field effect transistors are used, the source of which corresponds to the emitter, the drain to the collector, and the gate to the base of the bipolar transistor, and the drain of the second 3 input transistor is connected to the input 14 of the current mirror 7, the output 9 of the current mirror 7 is connected to the input of the additional buffer amplifier 15, the output of which is connected to the output of the device 4 through the second 13 correction capacitor, the drain of the first 2 input transistor is connected to the second 8 bus of the power source, and the output of the device 4 is shunted ac alternating resistor 16.

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