RU2511007C2 - Method of increasing yield ratio when manufacturing high-density electronic modules - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to microelectronics and can be used to increase yield ratio when manufacturing high-density electronic modules. When manufacturing high-density electronic modules by forming built-in passive elements, directly assembling active elements (chips) and layered formation of interconnections before manufacturing and assembling the electronic elements, a modification of the circuit is produced, which is intended only for testing thereof, and multifunctional probing of operating capacity of each element is carried out using processing procedures after forming passive elements and assembling active elements and before forming interconnections.

EFFECT: wider range of methods of lowering the cost of manufacturing high-density electronic modules, high yield ratio.

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Description

Technical field

The invention relates to electronics, and more specifically to microelectronics.

What is the yield in this case?

Suitable yield is a characteristic of the “quality of the technological process, showing the share of suitable (non-defective) products in the manufactured batch (or by group procurement).

Yield, as a rule, is defined as the ratio of the number of suitable products to the total batch volume (the number of products on a group procurement) and expressed as a percentage. Usually, the so-called suitable products from the first pass, i.e. not subjected to repair and restoration, however, in some cases, the yield from the first pass is distinguished as a separate characteristic ”(http: /www.elinform.ru/dictionary_262.htm).

In fact, an increase in yield means a reduction in the cost of electronic modules.

The technical result of the invention is to expand the arsenal of methods to reduce the cost of manufacturing high-density electronic modules.

State of the art

Let's turn to analogues.

One of the ways to reduce the manufacturing cost of electronic modules is proposed in Russian patent 2133522 "Method for the manufacture and control of electronic components."

“A method of manufacturing and control of electronic components is that many crystals are placed in the mold, focusing on the contact pads of the crystals and the basic elements of the mold, isolate all unprotected surfaces of the crystals, except for the contact pads. The specificity of the method lies in the fact that, when placed in a mold, the crystals are fixed with each other with the formation of a group carrier, ensuring that the front surfaces of the crystals are in the same plane with one of the surfaces of the group carrier, while all the conductors necessary for electrotraining are applied to this plane simultaneously and control, as well as an external media connector. Simultaneously with the crystals, a group metal frame is placed in the mold; the frame is fixed simultaneously with the crystals. The group medium may also be formed by a flexible printed circuit board connected to a rigid base. The technical result of the invention is to reduce the cost of electrothermal training and finishing control, reducing the duration of the assembly process and control of the electronic component. "

Another way is to increase the yield due to the high reliability of the interconnects (Russian patent 2193259).

Design of testability of circuits during their development is also proposed.

“Designing testability of circuits during their development (Design-For-Testability, DFT) is a key and integral component of modern design of electronic circuits and printed circuit boards. The expected level of test suitability (as a percentage of coverage of certain defects previously planned for testing) is usually laid down in the technical requirements of new developments and is confirmed by computer simulation of test suitability even before of how the manufacture and installation of printed circuit boards, components and systems. The rules of test-fit design <...> involve modifying the topology and / or connections between circuit elements or even adding additional elements (in-circuit or external), which may not be connected with the functioning of the circuit and are intended only to ensure its testability ”(http: // www.jtag-test.ru/Solutions/DFT.php).

This method is selected for the prototype.

Disclosure of invention

Output suitable for the manufacture of electronic modules is the most important characteristic of production. In the manufacture of high-density, functionally and physically saturated electronic modules (VPEM), their performance depends on a large number of reasons. The most significant effect on the increase in yield is exerted by the efficiency of passive elements after their formation and active elements after their installation. Traditionally, the input control of operability of active elements in limited operating conditions, the intermediate technological control of passive elements and the output control of the functioning of the finished module along with tests in the operating temperature range and other specified conditions are used. As a result, at the stage of the output control, the VPEM inoperability is only recorded due to the impossibility of the previous full-fledged control of elements in the range of operating temperatures and other conditions. There is no possibility in advance, at the initial stages of production of VPEM, to significantly affect the yield due to this problem.

To solve the problem, it is proposed to change the composition and sequence of operations for the production of VPEM so that the operability of active and passive elements in the operating range of conditions can be controlled at the initial stage of manufacture. Then, the implementation of the remaining less critical operations for the manufacture of VPEM will not significantly affect the yield. As a result, the yield of suitable VPEM will mainly be determined by control at the initial stage of manufacture.

To achieve the goal, it is proposed that after the formation of passive elements and direct installation of active elements, it is proposed to seal them with an insulating compound, which allows them to be protected from external influences in the range of operating conditions. Then, to form contact conclusions by known methods (photolithography, laser processing, metallization, planarization, etc.) and, before the subsequent layer-by-layer formation of interconnects, carry out, by known methods, full-function probe monitoring of the operability of each element in the operating temperature range and other external conditions.

To make this possible, the following technological operations are carried out sequentially, illustrated in figures 1-7:

1. Minor transactions.

2. Preparation of the surface of the substrate.

3. The formation of embedded thin-film elements R, C, L, microstrip elements, etc. Figure 1 shows, by way of example, resistance 1 and capacitor 2 with dielectric 3 on substrate 4.

4. Performing direct mounting of crystals of integrated circuits (chips) of various types (microwave monolithic integrated circuits, VLSI, microelectromechanical systems, systems on a chip, power assemblies, single semiconductor elements, photodetectors, passive elements in a "chip" version, etc.). In Fig. 2, the chip 5 is added to that shown in Fig. 1.

5. Filling the set of elements formed on the substrate with an insulating polymer layer above the level of the highest element by the amount of technological stock, for example, the well-known SU-8 photopolymer, 5-50 microns higher than the surface of the crystals (polymer 6 in FIG. 3).

6. Opening the contact areas to the filled elements, for example, by photolithography (contact area 7 in figure 4).

7. Filling with metallization of opened windows in the polymer layer, for example, by vacuum deposition and galvanic growth of the copper layer to the entire depth of the opened windows (metallization 8 in FIG. 5).

8. Planarization (for example, flat grinding and chemical-mechanical polishing) of the surface of the formed layer to the complete separation of all contacts (Fig.6).

9. Cleaning the surface of the contacts to ensure their minimum ohmic resistance and electrical probes in subsequent operations (Fig.6).

10. Performing full-function control of all elements by placing the substrate on a specialized heat-setting holder, sequentially connecting the measuring probes to the contacts of the elements and performing the set of required measurements (Fig. 7 shows a resistance meter 9, a capacitance meter 10, and a functional tester 11).

11. The direction of technological modules that have successfully passed control to subsequent technological operations and removal from the route of failed control.

12. Minor transactions.

Brief Description of the Drawings

Figure 1 illustrates the formation of embedded thin film elements.

Figure 2 illustrates the implementation of direct mounting crystals of integrated circuits (chips) of various types.

Figure 3 illustrates the filling formed on the substrate of a set of elements with a layer of insulating polymer.

Figure 4 illustrates the opening of the contact areas to the flooded elements.

Figure 5 illustrates the metallization filling of open windows in the polymer layer.

Fig.6 illustrates the planarization of the surface of the formed layer to the complete separation of all contacts and cleaning the surface of the contacts.

7 illustrates the implementation of full-function control of all elements.

The implementation of the invention

For 2 years, the company conducts probe control of test samples in accordance with the described method at the Sammit 12000 installation of Agilent Technologies (USA). This made it possible to increase the number of suitable products after the formation of multi-layer switching wiring by an average of 27% due to the timely rejection of semi-finished products at the initial stage of manufacture.

Claims (1)

A way to increase the yield of high-density electronic modules suitable for manufacturing based on the formation of built-in passive elements, direct mounting of active elements (chips) and layer-by-layer formation of interconnects, which consists in the fact that even before the manufacture and installation of electronic modules, a modification of the circuit is developed, which is intended only for its testability , characterized in that it allows due to technological operations after the formation of passive and installation of active elements and before the formation of the interconnect The intention is to carry out multifunctional probe monitoring of the health of each element.

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