RU2506598C1 - Peak detector - Google Patents

Abstract

FIELD: measurement equipment.

SUBSTANCE: invention relates to a pulsed technique and can be used in automation and power equipment for detecting and for determining the channel with the extreme voltage and its polarity. The technical result is achieved due to the fact that the peak detector comprises a power line, two input buses, two voltage comparing units and current comparing units, an analog switch, an n-p-n transistor, a capacitor, a resistor, a voltage follower, the first output line, the second resistor, the first diode, a control input, four second diodes, four pulse delay circuits, the second output line, the third resistor, an OR gate, a short pulse generator, four RS- triggers, a converter of code into voltage.

EFFECT: enhanced functionality by changing structure of the scheme and introduction of additional elements results not only in the maximum peak value of k input channels, but also the polarity and channel with maximum amplitude.

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Description

The invention relates to a pulse technique and can be used in automation devices and power equipment for detection, as well as to determine the channel with extreme voltage and its polarity.

A device for determining the channel with extreme voltage (G06G 7/02, SU No. 1385130 A1, BI No. 12, 1988, authors Voronova V.G., Gunbina M.V.), containing n comparators, the first inputs of which are inputs of the device the second inputs are connected to the output of the integrating filter, and the outputs are connected to the inputs of the OR element, the reference voltage source, the positive and negative voltage outputs of which are connected through the switch to the input of the integrating filter, a memory register and a pulse shaper, the input of which is connected to the output the positive voltage source of the reference voltage source, and the output is with the register zeroing input, the output of the OR element is connected to the control input of the switch and the control input of the memory register, and the outputs of n comparators are each connected to the input of the corresponding discharge of the memory register, the code output of which is the output of the device.

The disadvantages of the known device are limited functionality due to:

- the impossibility of determining the polarity of the extreme voltage, because its comparators work with a positive signal;

- lack of peak detector function, as its integrating filter does not provide the function of an analog memory element;

- the impossibility of compressing information due to the lack of a channel number pointer with extreme voltage, because memory register code outputs provide a multi-digit digital code.

The closest in technical essence to the claimed invention is a peak detector (RF patent No. 2409818 priority from 06.22.2009 authors Gutnikova A.I., Davletchina D.Z., Pikaeva L.A., IPC G01R 19/04 published on 01.20.2011) containing the power bus, k input buses, where k = 1, 2, ..., and k voltage comparison and current comparison blocks (BSNiST), including voltage comparators, analog switch, npn transistor, voltage follower, first diode, capacitor and resistor, second diodes, second, third and fourth resistors, threshold element, third diode, trigger ep Schmitt delay circuit comprising integrating circuit.

Each input bus is connected to the first input of the corresponding unit for comparing voltages and comparing currents. The first output of the analog switch is connected to a common bus, and the second output is connected to the emitter of an npn transistor, through a series-connected first capacitor and resistor with a common bus and to the input of a voltage follower, the output of which is connected to the output bus, with the second inputs of the BSNiST, the input of the threshold element and through a second resistor with an npn transistor base and an anode of the first diode. The cathode of the first diode is connected to the control input of the analog switch and the output of the Schmitt trigger, the input of which is connected through the second capacitor to the common bus and through the third resistor to the anode of the third diode and the first terminal of the fourth resistor, the second terminal of which is connected to the cathode of the third diode and the output of the threshold element. Each output of each BSNiST is connected to the anode of the corresponding second diode and the input of the corresponding pulse delay circuit. The power bus is connected to the collector of an n-p-n-transistor, the base of which is connected to the combined cathodes of the second diodes.

The disadvantages of the peak detector are:

- the inability to determine the polarity of the extreme voltage due to the structure of the circuit;

- the inability to determine the channel number with extreme voltage due to the structure of the circuit;

- the presence of a false pulse at the output of the peak detector due to the arbitrary state of the analog switch when the power is turned on.

The technical result, the invention is aimed at, is to expand the functionality.

This technical result is achieved by the fact that in the peak detector containing the power bus, k input buses, each of which is connected to the first input of the corresponding BSNiST, where k = 1, 2, ..., an analog switch, the first output of which is connected to a common bus, and the second output is connected to the emitter of the npn transistor, through a series-connected capacitor and a first resistor with a common bus and with the input of a voltage follower, the output of which is connected to the first output bus, with the second inputs of the BSNiST and through the second resistor with the base of the npn transistor the node of the first diode, the cathode of which is connected to the control input of the analog switch, the outputs of each BSNiST are connected to the anode of the corresponding second diode and the input of the corresponding pulse delay circuit, the power bus is connected to the collector of the npn transistor, it is new that the second output bus is added, the third resistor, OR gate, short-pulse generator (FKI), 2k RS-flip-flops, code-to-voltage converter (PCN), the output of each pulse delay circuit is connected to the corresponding S-input, respectively of the existing RS-flip-flop, the outputs of each BSNiST are connected to the corresponding input of the OR logic element, the output of which is connected via the shaper of short pulses to the combined R-inputs of the RS-flip-flops, the outputs of which are connected via the PCB to the second output bus, the base of the npn transistor is connected via a third resistor with combined cathodes of the second diodes.

Advanced functionality is provided by:

- the ability to determine the polarity of the extreme voltage and the channel number with the extreme voltage due to a change in the structure of the circuit in which the newly introduced third resistor and comparators from the BSNiST provided normalized logic levels to the newly introduced OR gate and S-inputs of 2k RS triggers. It is noted that when highlighting the extreme value at the outputs of the BSNiST comparators, a unitary code is formed that allows you to select both the input number with the extreme voltage and its polarity, due to the common voltage follower in the feedback circuit of all the BSNiST comparators of the peak detector. Due to the introduced periodic reset of the peak detector capacitor to zero, together with the above characteristics, a tracking mode of the extreme input voltage in the section arises after the next reset to zero of the capacitor, and any BSNiST comparators are triggered in each switching cycle, which resets all RS triggers through the logic element OR and FCI. The delayed installation of one of the RS triggers to the unit at the S-input corresponds to the number of the input bus with the maximum amplitude and with the specified polarity and is carried out from one of the BSNiST comparators with the maximum amplitude at the input. In this case, the other compilers BSNiST with a lower amplitude at the input are reset to zero through the feedback circuit. Stable operation of RS-triggers is provided by a delay circuit, while first they are set to zero, and then set to one with a delay. The presence of a unit in a unitary code at one of the inputs of the code-to-voltage converter (at the remaining inputs is zeros) from one of the many outputs of 2k RS-flip-flops provides analog voltage across one second bus, which provides information compression;

- the absence of a false pulse at the output of the peak detector due to the zero state of the analog key when the power is turned on with a single pulse on the zero bus or on the control input of the analog key.

Figure 1 presents an example implementation of a functional diagram of a peak detector at k = 2. Figure 2 shows the timing diagrams of the peak detector.

The peak detector (Fig. 1) contains a power bus 1, two input buses 2 and 3, two BSNiST 4, 5 (with two outputs each), an analog switch 6, an npn transistor 7, a capacitor 8, a first resistor 9, a voltage follower 10 , the first output bus 11, the second resistor 12, the first diode 13, the control input 14 of the analog switch 6, the second diodes 15, 16, 17, 18, the pulse delay circuit 19, 20, 21, 22, the second output bus 23, the third resistor 24 , logic element OR 25, FKI 26, four independent RS-flip-flops 27, PKN 28. Input buses 2 and 3 are connected to the first inputs of BSNiST 4, 5, respectively. The first output of the analog switch 6 is connected to a common bus, and the second output is connected to an emitter of an n-pn transistor 7 and to the input of a voltage follower 10, and through a series-connected capacitor 8 and a first resistor 9 with a common bus. The output of the voltage follower 10 is connected to the first output bus 11, to the second inputs of the BSNiST 4, 5 and through the second resistor 12 with the base of the npn transistor 7 and the anode of the first diode 13. The cathode of the diode 13 is connected to the control input 14 of the analog switch 6, the outputs of each BSNiST 4, 5 are connected to the anodes of the second diodes 15, 16 and 17, 18, respectively, and the input of the corresponding pulse delay circuit 19, 20, 21, 22. The power bus 1 is connected to the collector of the npn transistor 7. The output of each pulse delay circuit 19, 20, 21, 22 connected to the corresponding S-input of the RS-flip-flops 27. The outputs of each The first BSNiST 4, 5 is connected to the corresponding inputs of the OR gate 25, the output of which through the FCI 26 is connected to the combined R-inputs of the RS flip-flops 27, the outputs of which are connected through the PKN 28 to the second output bus 23. The base of the npn transistor 7 through the third resistor 24 is connected to the combined cathodes of the second diodes 15, 16, 17, 18.

PKN 28 is made on a standard digital-to-analog converter. FCI is made on a differentiating RC circuit.

The analog switch 6 is made on a series-connected logic element NOT 29, the input of which is a non-inverting control input 14 of the analog switch 6, and a bit key with a common emitter on the n-p-n-transistor 30.

The pulse delay circuit 19, 20, 21, 22 is of the same type, each is made on an integrating RC circuit, the input of which is an input, the output of which is the output of the pulse delay circuit 19, 20, 21, 22. Active pulse delay circuits made in series are also applicable. connected logic gates or special microcircuits.

BSNiST 4, 5 are of the same type, each is made on two differential voltage comparators (DCI) 31, 32. The non-inverting input of the comparator 31 is connected to a common bus, the inverting input of the comparator 31 is connected to the combining point of the resistors 33, 34. The second output of the resistor 33 is the first input of the BSNiST 4, 5 and is connected through a resistor 35 to the non-inverting input of the comparator 32. The second output of the resistor 34 is the second input of the BSNiST 4, 5 and is connected to the inverting input of the comparator 31.

The positive power terminals BSNiST 4, 5 and voltage follower 10 are connected to a common power bus 1, and their negative power leads are connected to a common bus (not shown in Fig.).

The figure 2 presents the timing diagrams of the peak detector (figure 2), where:

U ₂ , U ₃ - bipolar voltage pulses of a wide range of amplitudes and duration on input buses 2 and 3, starting from time t1 to time t9;

U ₁₄ - periodic pulses of a Reset duration at the control input 14 for resetting to 0 a capacitor 8 of a peak detector after reading information into a storage device (not shown in FIG. 1);

U ₁₁ - output pulses on the bus 11, equal to the maximum amplitudes of the pulses from the input buses 2 and 3, extended in duration to the specified recording time of the storage device (not shown in Fig. 1) t _xpah ;

U ₂₃ - output pulses on the bus 23, reflecting the polarity of the maximum pulses and the number of the input bus 2, 3, containing the maximum amplitude pulse at moments t1, t4, t5, t6, t7, t8, t9.

The peak detector operates as follows.

In the initial static state, until time t0 in FIG. 2, the voltage on the input buses 2, 3 is zero, and power is supplied to the bus 1. The zero level on the control bus 14 of the analog switch 6, the capacitor 8 is discharged almost to zero (several millivolts) voltage. DKN 31, 32 are in a state of logical zero at the output due to a small (several millivolts) bias voltage at their inverting inputs, formed by the input leaky bias current of the voltage follower 10, flowing through its large input resistance. At the outputs of the comparators BSNiST 4, 5 and the output of the logical element OR 25 logical zero. At the output of the FCI 26 and at the combined R-inputs of the RS-flip-flops 27 is a logical zero. A single pulse of positive polarity on the zero-setting bus R (not shown in FIG. 1) RS-flip-flops 27 are set to zero by direct Q-outputs, which ensures zero voltage at the output of the control panel 28 and the output bus 23.

The combined cathodes of the diodes 15, 16 and 17, 18, the base of the npn transistor 7 also have a “zero” (several millivolts) voltage from the output of the voltage follower 10 through the resistor 12.

With a negative polarity of the input signal on the input buses 2, 3, to limit the signals on the comparators 32 of the BSNiST 4, 5, resistors 35 are installed. The pulse delay circuits 19, 20, 21, 22 provide a delay for the pulses received after the moment t1 from the output of the comparators 31, 32 to S-inputs of RS-flip-flops 27, an amount greater than the pulse width of the PCF. Comparators 32 perform a voltage comparison function for a positive input voltage, and comparators 31 with resistors 33, 34 perform a current comparison function for a negative input voltage.

At time t0, the voltage of the logical unit with which the diode 13 is locked is set at the control input 14, and the n-p-n-transistor 30 of the analog switch 6 is locked with a logic zero through a logic element NOT 29.

Upon receipt of negative pulses on the input buses 2, 3 and inverting inputs of the comparators 31 (see t1 on U ₂ , U ₃ in FIG. 2), the comparators 31 switch to the state of the logic unit by the output and through the open diodes 15, 17 and the npn transistor 7, a capacitor is charged 8. Through a voltage follower 10, this voltage in the form of an output signal U ₁₁ (negative feedback signal) is supplied through resistors 34 to the inverting inputs of the comparators 31, returning them sequentially as the output signal U ₁₁ grows to a logical zero state (at equalizing the amplitudes of the current pulses at the inverting inputs in the resistors 33, 34).

The pulse delay circuits 19, 21 provide a delay of the front and fall of the pulses of the comparators 31 arriving at the corresponding S-inputs of the RS-flip-flops 27 at times t1, t5, t8, to exceed the pulse duration at the decay of the pulses at the combined R-inputs of the RS-flip-flops 27 when returning comparators 31 from the state of the logical unit to the state of logical zero and the allocation of the maximum value with the installation of a single RS-trigger in unit.

During the negative input pulses arriving at the non-inverting inputs of the comparators 32 BSNiST 4, 5, which are in a state of logical zero, the diodes 16, 18 are closed and do not participate in the work.

The voltage across the capacitor 8 exists during the storage time t _XPAH ; the duration of which is determined by the period of the reset pulses of the Reset at the control input 14. The reset pulse (logical zero) from the control input 14 (see U ₁₄ in figure 2) through the element 29 opens the bit key on the npn transistor 30, discharging the capacitor 8 in a short time t ₂ -t ₃ . In this case, the diode 13 is open, which means that the voltage at the base of the npn transistor 7 is 0.3 V, which is not enough to unlock it and, therefore, the npn transistor 7 is protected against current overload even in the case of long input negative pulses on the input buses 2 3 (not shown in FIG. 2).

Upon receipt at the input buses 2, 3 and non-inverting inputs of the comparators 32 BSNiST 4, 5 positive pulses (see t4 on U ₂ , U ₃ in figure 2), the comparators 32 are switched to the state of the logical unit by the output and through the diodes 16, 18 and the npn transistor 7 charges the capacitor 8. Through a voltage follower 10, this voltage in the form of an output signal U ₁₁ (negative feedback signal) is supplied to the inverting inputs of the comparators 32, returning them sequentially as the output signal U ₁₁ grows to a logical zero state (when equalizing straining eny input to the comparator 32).

Pulse delay circuits 20, 22 provide a delay of the front and fall of the pulses of the comparators 32 arriving at the corresponding S-inputs of the RS-flip-flops 27 at the times t4, t6, t7, t9 to exceed the pulse duration of the FCI 26 at the decay exceeding the combined R-inputs of the RS-flip-flops 27 when returning the comparators 32 from the state of the logical unit to the state of logical zero and highlighting the maximum value with the installation of a single RS-trigger in one.

During the positive input pulses entering through the resistors 33 to the inverting inputs of the comparators 31 BSNiST 4, 5, which are in a state of logical zero, the diodes 15, 17 are closed and do not participate in the work.

The value of t _{XPAH is} an order of magnitude smaller than the discharge time constant of the storage capacitor 8 at the high input resistance of the voltage follower 10, which ensures the stability of the stored amplitude. The pulses at the control input 14 of the analog switch 6 are periodic (see U14 in figure 2). The pulse duration t _XPAH (reset delay time) should be sufficient to transfer the maximum amplitude of the next stored pulses to the external memory.

The polarity of the extreme voltage and the channel number with the extreme voltage are determined by changing the structure of the circuit in which the newly introduced third resistor 24 and comparators 31, 32 from the BSNiST 4, 5 provide normalized logic levels to the newly introduced logic element OR 25 and S-inputs of four RS flip-flops 27 (by increasing the input resistance of the npn transistor 7). When highlighting the extreme value at the outputs of the four compilers BSNiST 4, 5 and RS-flip-flops 27, a unitary code is formed, which allows you to select both the input number with the extreme voltage and its polarity, due to the common voltage follower 10 in the feedback circuit of all BSNiST 4 comparators, 5 peak detector. Due to the introduced periodic zeroing of the peak detector capacitor 8 in conjunction with the above features, a tracking mode of the extreme input voltage in the section arises after the next resetting of the capacitor 8 to zero, and in every switching cycle any BSNiST 4, 5 comparators are activated, which resets all RS -triggers 27 through the logical element OR 25 and FKI 26. Subsequent delayed installation of one of the RS-triggers 27 into the unit at the S-input corresponds to the input bus number 2 or 3 with the maximum amplitude given polarity and carried out with one of the four comparators BSNiST 4, 5 having the maximum amplitude of the input. In this case, the remaining three comparators BSNiST 4, 5 with a lower input amplitude are reset to zero through the feedback circuit. Stable operation of the RS-flip-flops 27 is provided by pulse delay circuits 19, 20, 21, 22, while first they are set to zero, and then set to one with a delay. The presence of units in the unitary code at one of the inputs of the control panel 28 (at the remaining inputs are zeros) from one of the four outputs of four RS-flip-flops 27 provides the corresponding step voltage on the second bus 23, which provides information compression.

The absence of a false pulse (when the power is turned on) at the output of the peak detector 11 is ensured by zeroing the voltage across the capacitor 8 with an analog switch 6 for a single pulse on the zero bus (not shown in Fig. 1) or at the control input 14 of the analog switch 6.

Tests of the peak detector layout confirmed its operability and claimed advantages in the range of operating temperatures from -40 ° to + 50 ° C.

Claims (1)

A peak detector containing a power bus, k input buses, each of which is connected to the first input of the corresponding unit for comparing voltages and currents, where k = 1, 2, ..., an analog switch, the first output of which is connected to a common bus, and the second output is connected to an emitter of an npn transistor, through a series-connected capacitor and a first resistor, with a common bus and a voltage follower input, the output of which is connected to the first output bus, with the second inputs of the voltage and current comparison unit and through the second resistor with the npn transistor base ra and the anode of the first diode, the cathode of which is connected to the control input of the analog switch, each output of each voltage and current comparison unit is connected to the anode of the corresponding second diode and the input of the corresponding pulse delay circuit, the power bus is connected to the collector of the npn transistor, characterized in that introduced a second output bus, a third resistor, an OR gate, a short-pulse shaper, 2k RS-flip-flops, a code-to-voltage converter, the output of each pulse delay circuit is connected to corresponding S-input of the corresponding RS-flip-flop, the outputs of each block comparing voltages and currents are connected to the corresponding input of the OR logic element, the output of which is connected via the shaper of short pulses to the combined R-inputs of the RS-flip-flops, the outputs of which are connected to the second through the code-to-voltage converter output bus, the base of the npn transistor is connected through a third resistor to the combined cathodes of the second diodes.

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