CN205912037U - Metastable state cancelling circuit and equipment thereof - Google Patents
Metastable state cancelling circuit and equipment thereof Download PDFInfo
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- CN205912037U CN205912037U CN201620428588.5U CN201620428588U CN205912037U CN 205912037 U CN205912037 U CN 205912037U CN 201620428588 U CN201620428588 U CN 201620428588U CN 205912037 U CN205912037 U CN 205912037U
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Abstract
The utility model relates to a metastable state cancelling circuit and equipment thereof. The metastable state cancelling circuit includes: developments latch the comparator, comparator output judges circuit, asynchronous clock generation circuit, metastable state judgement circuit and dynamic charge injector circuit, and the metastable state judges that the circuit detects the comparative result that the comparator output who receives judges circuit signal in the setting -up time to only demonstrate signal that comparator output judges the circuit and do not having and allowwing the dynamic charge injector circuit to pour into the metastable state of corresponding electric charge with the cancelling circuit in to the circuit into under the condition of difference. The utility model discloses an allow the dynamic charge injector circuit in to the circuit injection charge in order to eliminate the metastable state for the circuit is more stable, and this circuit has the advantage of low -power consumption moreover.
Description
Technical field
This utility model is related to microelectric technique design field, and specifically, this utility model is related to metastable state eliminates electricity
Road and its equipment.
Background technology
Existing analog-to-digital conversion device is the important interface between analogue signal and digital signal.Sending out with modern network
Exhibition, have low-power consumption, small size, intermediate resolution and in high sample rate analog-to-digital conversion device demand increasing.
Because gradual approaching A/D converter is in the excellent expression power of the aspects such as power consumption, area, precision, speed, cost
Can, and be widely used.
The bottleneck of existing gradual approaching A/D converter development is mainly manifested in: in gradual approaching A/D converter
Metastable state phenomenon.For high-resolution gradual approaching A/D converter, when the input voltage signal of comparator is excessively micro-
Weak, now the input voltage signal of comparator closely, leads to comparator can not quickly judge its input voltage signal
Size, thus be easier occur metastable state phenomenon.
Utility model content
This utility model embodiment is to provide a kind of metastable state and eliminate circuit and its equipment, and this metastable state and eliminate circuit is led to
Cross the comparative result of metastable state decision circuitry detection signal in setting time, and only show corresponding signal not significantly
Allow in the case of difference to inject corresponding electric charge in circuit to eliminate the metastable state of circuit, so that circuit is more stable.
In a first aspect, this utility model provides a kind of metastable state and eliminate circuit, described circuit includes:
Dynamic latch comparator, comparator output decision circuitry, asynchronous clock produce circuit, metastable state decision circuitry and
Dynamic charge injection circuit,
Asynchronous clock produces the asynchronous clock control signal that circuit produces dynamic latch comparator；
Metastable state decision circuitry detects that in setting time received comparator exports the comparison of the signal of decision circuitry
As a result, and only in the case that the signal showing comparator output decision circuitry is not significantly different from allow dynamic charge injection
Circuit injects corresponding electric charge to eliminate the metastable state of circuit in circuit.
Preferably, dynamic charge injection circuit includes:
Switch and current source, one end of switch is connected with current source, the other end of switch and dynamic latch comparator
Input is connected, and the other end of current source is connected with the power end of circuit.
Preferably, when metastable state decision circuitry is triggered, the connection controlling dynamic charge injection circuit is so that dynamic charge
Injection circuit discharges to the latch stage of dynamic latch comparator, so that comparator output decision circuitry produces corresponding pulse letter
Number；Or,
When metastable state decision circuitry no exports, dynamic charge injection circuit cuts out so that extraneous power supply is noted to dynamic charge
Enter circuit to be charged, to prepare the discharge process of dynamic charge injection circuit next time.
Preferably, dynamic latch comparator includes dynamic pre-amplification stage and latch stage；
Dynamic pre-amplification stage is realized the input voltage signal of circuit being carried out with the process of pre-amplification process, to generate amplification
Voltage signal simultaneously exports；
Latch stage carries out, to the voltage signal amplifying, the process that voltage signal compares process, to generate corresponding useful signal
And export, wherein, the outfan of dynamic pre-amplification stage is connected with the input of latch stage.
Preferably, metastable state decision circuitry sets the required trigger pulse of the dynamic charge injection corresponding with setting time
Threshold value.
Preferably, metastable state decision circuitry sets the current source corresponding with dynamic charge injection circuit.
Preferably, described circuit also includes Approach by inchmeal logic, and Approach by inchmeal logic sets and the conversion of switching capacity digital-to-analogue
The corresponding control logic of device.
Preferably, produce comparator in the form of NAND gate to export the comparative result of decision circuitry signal and export.
Second aspect, this utility model embodiment provides the equipment of metastable state and eliminate circuit, including such as first aspect institute
The either circuit stated.
This utility model embodiment provides metastable state and eliminate circuit and its equipment, and this metastable state and eliminate circuit is passed through metastable
The comparative result of state decision circuitry detection signal in setting time, and only showing what corresponding signal was not significantly different from
In the case of allow to inject corresponding electric charge in circuit to eliminate the metastable state of circuit, so that circuit is more stable.
Brief description
Fig. 1 is the general principles frame of the metastable state and eliminate circuit based on the injection of feedback control loop dynamic charge of the present utility model
Figure；
Fig. 2 is another optimization knot of the metastable state and eliminate circuit based on the injection of feedback control loop dynamic charge of the present utility model
Structure block diagram；
Fig. 3 is the another optimization knot of the metastable state and eliminate circuit based on the injection of feedback control loop dynamic charge of the present utility model
Structure block diagram；
Fig. 4 is the sequential chart of the metastable state and eliminate circuit that this utility model embodiment provides.
Specific embodiment
Below by drawings and Examples, the technical solution of the utility model is described in further detail.
As shown in figure 1, it is total for the metastable state and eliminate circuit based on the injection of feedback control loop dynamic charge of the present utility model
Body theory diagram.It is illustrated as in Fig. 1: 101, switching capacity digital to analog converter, 102, dynamic latch comparator, wherein, 102a is
The dynamic pre-amplification stage of dynamic latch comparator, 102b be dynamic latch comparator latch stage, 103, comparator output judge
Circuit, 104, asynchronous clock produce circuit, 105, metastable state decision circuitry, 106, Approach by inchmeal logic, 107, dynamic charge note
Enter circuit.
Switched capacitor digital to analog converter 101 input receives differential input signal, completes the sampling to input signal, and
Generation output signal is controlled by Approach by inchmeal logic 106, and produced output signal is connected to dynamic latch comparator
102.Dynamic latch comparator 102 includes: dynamic pre-amplification stage 102a and latch stage 102b, wherein dynamic pre-amplification stage 102a
Two outfans connect two inputs of latch stage 102b respectively, and dynamic pre-amplification stage 102a is used for realizing input voltage is believed
Number pre-amplification, then corresponding output result is produced by positive feedback processing procedure by latch stage 102b, output result is anti-
Mirror the comparison procedure of corresponding input voltage signal.Comparator output decision circuitry 103 includes: two input connects respectively
Two outfans of dynamic latch comparator 102, and output result q according to dynamic latch comparator 102 and qbProduce valid
Signal, wherein, valid signal is used for reflecting the comparative result that comparator exports decision circuitry signal.Numerical value when valid signal
During for 1, represent corresponding signal (output result q and qb) there were significant differences, conversely, when the numerical value of valid signal is 0, table
Show corresponding signal (output result q and qb) be not significantly different from.The input termination comparator output of Approach by inchmeal logic 106 is sentenced
The outfan of deenergizing 103, thus receiving corresponding valid signal, and then produces controlling switch capacitor D/A converter 1
Control logic.Asynchronous clock produces the input of circuit 104 and comparator exports outfan and the Approach by inchmeal of decision circuitry 103
The outfan of logic 106 connects, for producing asynchronous clock control signal latch of dynamic latch comparator 102.Metastable state is sentenced
The input of deenergizing 105 terminates the outfan that comparator exports decision circuitry 103, thus receiving corresponding valid, for producing
Lively state charge injection trigger pulse.Dynamic charge injection circuit 107 includes: switch s1With current source i1, a termination electric current of s1
Source i1, an another input op terminating to dynamic latch comparator 102, dynamic electric is controlled by metastable state decision circuitry 105
The state of lotus injection circuit 107, another termination of current source i1 is connected with power supply vdd.
Need it is further noted that in the metastable state and eliminate circuit that this utility model embodiment is provided, by adopting
Produce comparator with the form of NAND gate to export the comparative result of decision circuitry signal and export.That is, valid signal be equal to q with
qbWith non-, specifically, comparator reset during, q be " 1 ", qbFor " 1 ", then accordingly, through NAND gate, " 1 " and " 1 " with
The numerical value of the non-valid signal for " 0 ", producing through NAND gate is 0；During comparator compares, q is " 1 ", qbFor " 0 ", or
Person, q is " 0 ", qbFor " 1 "；Then corresponding, through NAND gate, " 1 " and " 0 ", are produced through NAND gate for " 1 " with non-
The numerical value of valid signal is 1.So, when the numerical value of valid signal is 1, represent that there were significant differences for corresponding signal, i.e. defeated
Go out result q and output result qbThere were significant differences, conversely, when the numerical value of valid signal is 0, representing that corresponding signal does not have
Significant difference, i.e. output result q and output result qbIt is not significantly different from.In this manner it is possible to judge electricity by analyzing metastable state
The comparative result of road detection signal in setting time, and only show what corresponding signal was not significantly different from comparative result
In the case of allow to inject corresponding electric charge in circuit to eliminate the metastable state of circuit, so that circuit is more stable.
By the general principles block diagram of metastable state and eliminate circuit as shown in Figure 1 it will thus be seen that being sentenced by analyzing metastable state
The comparative result of deenergizing detection signal in setting time, and only show that corresponding signal does not have significance difference in comparative result
Allow in the case of different to inject corresponding electric charge in circuit to eliminate the metastable state of circuit, so that circuit is more stable.
Further, metastable state and eliminate circuit of the present utility model be based on feedback control loop dynamic charge injection asynchronous by
Secondary approach analog-digital converter metastable elimination circuit.Wherein, dynamic latch comparator 102, comparator output decision circuitry
103rd, asynchronous clock produces circuit 104, metastable state decision circuitry 105 and one feedback of dynamic charge injection circuit 107 composition
Network.Metastable state decision circuitry 105 is passed through to detect that valid signal judges whether dynamic latch comparator 102 enters metastable state
State.Specifically, change as being not detected by valid signal within the time (such as δ t) of regulation, then metastable state judges
Circuit 105 produces a short pulse signal, and metastable state decision circuitry 105 is passed through to control dynamic charge injection unit 107 triggering to open
Close s1With current source i1Inject electric charge in circuit, break the metastable equilibrium state of dynamic latch comparator 102, promote dynamic latch
Comparator 102 enters new positive exponent and sets up process, quick lock in a new comparative result, when comparative result shows:
Signal has significant difference, thus proving that circuit is in stable state it is achieved that eliminating original unstable metastable of circuit
The purpose of state.
Further, dynamic charge injection circuit 107 and dynamic latch comparator 102 can have multiple connected modes.As
Shown in Fig. 1, the connected mode being adopted between dynamic charge injection circuit 107 and dynamic latch comparator 102 is current source i1、
Switch s1It is connected in parallel to the input op of dynamic latch comparator 102 respectively.Additionally, in actual applications, dynamic charge is noted
Entering the connected mode being adopted between circuit 107 and dynamic latch comparator 102 can also be particularly as follows: current source i1, switch s1Point
It is not connected in parallel to the input on of dynamic latch comparator 102.
In the metastable state and eliminate circuit that this utility model embodiment provides, dynamic latch comparator, comparator output are sentenced
Deenergizing, asynchronous clock produce circuit, metastable state decision circuitry and dynamic charge injection circuit and constitute a feedback network.
Asynchronous clock produces the asynchronous clock control signal that circuit produces dynamic latch comparator；
Metastable state decision circuitry detects that in setting time received comparator exports the comparison knot of decision circuitry signal
Really, and only in the case that the signal showing comparator output decision circuitry is not significantly different from allow dynamic charge injection electricity
Corresponding electric charge is injected to eliminate the metastable state of circuit in road direction circuit.
The metastable state and eliminate circuit of this utility model embodiment, is examined in setting time by analyzing metastable state decision circuitry
Survey the comparative result of signal, and only show in comparative result and allow to circuit in the case that corresponding signal is not significantly different from
Middle injection corresponding electric charge to eliminate the metastable state of circuit so that circuit is more stable.
As embodiment of the present utility model, dynamic charge injection circuit includes: switch and current source, one end of switch with
Current source is connected, and the other end of switch is connected with the input of dynamic latch comparator, the other end of current source and circuit
Power end be connected.
As embodiment of the present utility model, when metastable state decision circuitry is triggered, control dynamic charge injection circuit
Connect so that dynamic charge injection circuit discharges to the latch stage of dynamic latch comparator, so that comparator output decision circuitry
Produce corresponding pulse signal；Or, when metastable state decision circuitry no exports, dynamic charge injection circuit cuts out so that extraneous
Power supply is charged to dynamic charge injection circuit, to prepare the discharge process of dynamic charge injection circuit next time.
As embodiment of the present utility model, dynamic latch comparator includes dynamic pre-amplification stage and latch stage；Dynamically pre-
Amplifier stage realizes the input voltage signal of circuit is carried out with the process of pre-amplification process, to generate the voltage signal of amplification defeated
Go out；Latch stage carries out, to the voltage signal amplifying, the process that voltage signal compares process, to generate corresponding useful signal defeated
Go out, wherein, the outfan of dynamic pre-amplification stage is connected with the input of latch stage.It should be noted that metastable state judges electricity
Road detects that within the time (δ t) of regulation the time (δ t) of valid signal can be by programming the different detection time of setting
The interval of (δ t), to meet the different demands of user.
As embodiment of the present utility model, metastable state decision circuitry sets the dynamic charge corresponding with setting time
The required trigger pulse threshold value of injection.It should be noted that the triggering arteries and veins of dynamic charge that dynamic charge injection circuit is injected
Punching can be by programming the different trigger pulse of setting generation width, to meet the different demands of user.
As embodiment of the present utility model, metastable state decision circuitry sets the electricity corresponding with dynamic charge injection circuit
Stream source.It should be noted that the current source for producing dynamic charge to can be by programming different with intensity to produce size
Electric current, to meet the different demands of user.
As embodiment of the present utility model, described circuit also includes Approach by inchmeal logic, Approach by inchmeal logic set with
The corresponding control logic of switching capacity digital to analog converter.
As embodiment of the present utility model, produce the ratio that comparator exports decision circuitry signal in the form of NAND gate
Relatively result simultaneously exports.It should be noted that in addition to the form of NAND gate, comparator output decision circuitry can have multiple shapes
Formula, to produce corresponding valid signal, will not be described here.
The metastable state and eliminate circuit of this utility model embodiment, is detected in setting time by analyzing metastable state decision circuitry
The comparative result of interior signal, and only show in comparative result and allow to circuit in the case that corresponding signal is not significantly different from
Middle injection corresponding electric charge to eliminate the metastable state of circuit so that circuit is more stable.
Fig. 2 is another optimization knot of the metastable state and eliminate circuit based on the injection of feedback control loop dynamic charge of the present utility model
Structure block diagram.Fig. 2 is contrasted with Fig. 1, Fig. 2 is the ways of realization different from Fig. 1, and specific implementation is: by metastable state
Decision circuitry directly produces a control signal, connects and exports decision circuitry to comparator, for controlling the product of valid signal
Raw.
Fig. 3 is the another optimization knot of the metastable state and eliminate circuit based on the injection of feedback control loop dynamic charge of the present utility model
Structure block diagram.
Fig. 3 is contrasted with Fig. 1, Fig. 3 is the ways of realization different from Fig. 1, and specific implementation is: Fig. 3 also may be used
Meet same op end identical feedback unit (current source i in the other end on of latch2With switch s2) as standby dynamic charge note
Enter circuit, wherein s2Connecing fixed level, to ensure that switch is off state, making circuit have symmetry, thus reaching into one
Step ground optimizes the purpose of circuit.
Fig. 4 is the sequential chart of the metastable state and eliminate circuit that this utility model embodiment provides.As shown in figure 4, combined circuit
Sequential chart, describes asynchronous gradual approaching A/D converter metastable elimination process.
In embodiment of the present utility model, normal mode of operation is: input voltage signal first passes through dynamic latch and compares
The dynamic pre-amplification stage of device is transmitted to the latch stage of dynamic latch comparator after amplifying, and the signal after amplification has voltage difference.Cause
The difference of this velocity of discharge, tells result q and q through the positive feedback effect of the latch stage of dynamic latch comparatorb, then q
And qbValid signal is produced by NAND gate.When latch signal is " 0 ", dynamic latch comparator is in reset state, right
Q and q answeringbIt is " 1 ", the valid signal producing through NAND gate is " 0 ", now produces what circuit produced by asynchronous clock
Latch signal is changed into " 1 "；When latch signal be " 1 " when, dynamic latch comparator enter normally compare state, tell q and
qb, q is " 1 ", qbFor " 0 ", or, q is " 0 ", qbFor " 1 "；The valid signal producing through NAND gate is " 1 ", now by different
The latch signal that step clock generation circuit produces is changed into " 0 ", is circulated down with this, until completing the conversion of successive approximation modulus
The transformation process of device.
Need it is further noted that in the metastable state and eliminate circuit that this utility model embodiment is provided, latch believes
Number with q and qbRelation to be realized by dynamic latch comparator.The corresponding relation of valid signal and latch signal is logical
Cross asynchronous clock and produce circuit to realize, particularly latch is realized by gate and be equal to the non-of valid, here not
Repeat again.
And when dynamic latch comparator input voltage signal closely when, that is, be less than 1lsb (least
Significant bit, least significant bit) (even 1/2lsb, 1/4lsb), and when latch signal is " 1 ", dynamic latch ratio
Fail to tell q and q in the time δ t of regulation compared with the latch stage of deviceb, corresponding valid signal is " 0 " always, then phase
The latch signal answered is continued for as " 1 ", dynamic latch comparator entrance metastable state state.
The metastable elimination process of asynchronous gradual approaching A/D converter is described in detail below accordingly:
A) fail to detect that valid signal is changed into " 1 " in the time δ t of regulation from metastable state decision circuitry, thus judging
Go out dynamic latched comparator and enter metastable state state.B) produce a short pulse signal to touch by metastable state decision circuitry itself
Send out switch s1Closure；Work as s1After closure, current source i1Inject corresponding electric charge to the latch stage of dynamic latch comparator, thus broken
The metastable state state of bad latch is so that the voltage of circuit reaches stable state.
The process of implementing is: makes q be " 1 ", qbFor " 0 ", or, q is " 0 ", qbFor " 1 "；Valid signal is accordingly
" 1 ", latch signal is changed into " 0 ", promotes dynamic latch comparator to enter new positive exponent and sets up process, quick lock in
New stable comparative result effectively, thus reached the metastable purpose of elimination.It should be noted that dynamic charge injection electricity
The quantity of electric charge of the electric charge that road is injected refers to equation below:Wherein, q is particularly as follows: dynamic charge injection circuit
The quantity of electric charge of the electric charge being injected, vmeta is particularly as follows: enable latch to depart from metastable minimum in given time just
Beginning of-state voltage, cp is particularly as follows: the parasitic capacitance of input node locked by latch.
The metastable state and eliminate circuit of this utility model embodiment, is examined in setting time by analyzing metastable state decision circuitry
Survey the comparative result of signal, and only show in comparative result and allow to circuit in the case that corresponding signal is not significantly different from
Middle injection corresponding electric charge to eliminate the metastable state of circuit so that circuit is more stable.
Additionally, as shown in above-mentioned formula, it should be noted that the dynamic charge that injected of dynamic charge injection circuit
The quantity of electric charge can be by what above-mentioned formula accurately calculated, the different demands to meet user.With respect to existing technology, this reality
The metastable state and eliminate circuit being provided with new embodiment, more accurately can inject corresponding electric charge to eliminate electricity in circuit
The metastable state on road, so that circuit is more stable.
In actual applications, above-mentioned metastable state and eliminate circuit can be also used for preparing and includes above-mentioned metastable state and eliminate circuit
Equipment, detail, with reference to the corresponding details of metastable state and eliminate circuit, will not be described here.
Above-described specific embodiment, is entered to the purpose of this utility model, technical scheme and beneficial effect
One step describes in detail, be should be understood that and the foregoing is only specific embodiment of the present utility model, is not used to limit
Fixed protection domain of the present utility model, all any modifications within spirit of the present utility model and principle, made, equivalent replaces
Change, improve, should be included within protection domain of the present utility model.
Claims (9)
1. a kind of metastable state and eliminate circuit is it is characterised in that include: dynamic latch comparator, comparator output decision circuitry, different
Step clock generation circuit, metastable state decision circuitry and dynamic charge injection circuit,
Described asynchronous clock produces the asynchronous clock control signal that circuit produces described dynamic latch comparator；
Described metastable state decision circuitry detects that in setting time the described comparator being received exports the signal of decision circuitry
Comparative result, and only allow described in the case that the signal showing described comparator output decision circuitry is not significantly different from
Dynamic charge injection circuit injects corresponding electric charge to eliminate the metastable state of described circuit in described circuit.
2. metastable state and eliminate circuit according to claim 1 is it is characterised in that described dynamic charge injection circuit includes:
Switch and current source, one end of described switch is connected with described current source, and the other end of described switch is dynamic with described
The input of latched comparator is connected, and the other end of described current source is connected with the power end of described circuit.
3. metastable state and eliminate circuit according to claim 1 and 2 it is characterised in that
When described metastable state decision circuitry is triggered, the connection controlling described dynamic charge injection circuit is so that described dynamic electric
Lotus injection circuit discharges to the latch stage of described dynamic latch comparator, so that described comparator output decision circuitry produces accordingly
Pulse signal；Or,
When described metastable state decision circuitry no exports, described dynamic charge injection circuit cuts out so that extraneous power supply is to described dynamic
State charge injection circuit is charged, to prepare the discharge process of described dynamic charge injection circuit next time.
4. metastable state and eliminate circuit according to claim 3 is it is characterised in that described dynamic latch comparator includes dynamically
Pre-amplification stage and latch stage；
Described dynamic pre-amplification stage realizes the input voltage signal of described circuit is carried out with the process of pre-amplification process, is put with generating
Big voltage signal simultaneously exports；
Described latch stage carries out, to the voltage signal of described amplification, the process that voltage signal compares process, effective accordingly to generate
Signal simultaneously exports, and wherein, the outfan of described dynamic pre-amplification stage is connected with the input of described latch stage.
5. metastable state and eliminate circuit according to claim 1 is it is characterised in that described metastable state decision circuitry sets and institute
State the required trigger pulse threshold value of the corresponding dynamic charge injection of setting time.
6. metastable state and eliminate circuit according to claim 5 is it is characterised in that described metastable state decision circuitry sets and institute
State the corresponding current source of dynamic charge injection circuit.
7. metastable state and eliminate circuit according to claim 1 is it is characterised in that described circuit also includes Approach by inchmeal patrols
Volume, described Approach by inchmeal logic sets the control logic corresponding with switching capacity digital to analog converter.
8. metastable state and eliminate circuit according to claim 1 is it is characterised in that produce described ratio in the form of NAND gate
Export the comparative result of decision circuitry signal compared with device and export.
9. a kind of equipment of metastable state and eliminate circuit is it is characterised in that include claim 1-8 either circuit.
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| CN201620428588.5U CN205912037U (en) | 2016-05-12 | 2016-05-12 | Metastable state cancelling circuit and equipment thereof |
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| CN201620428588.5U CN205912037U (en) | 2016-05-12 | 2016-05-12 | Metastable state cancelling circuit and equipment thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105897268A (en) * | 2016-05-12 | 2016-08-24 | 英特格灵芯片(天津)有限公司 | Metastable state eliminating circuit and equipment |
| CN111262561A (en) * | 2020-02-05 | 2020-06-09 | 电子科技大学 | Metastable state detection circuit of comparator |
| CN111740744A (en) * | 2020-07-28 | 2020-10-02 | 灵矽微电子(深圳)有限责任公司 | Metastable state detection correction circuit of SAR analog-to-digital converter and asynchronous SAR analog-to-digital converter |
-
2016
- 2016-05-12 CN CN201620428588.5U patent/CN205912037U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105897268A (en) * | 2016-05-12 | 2016-08-24 | 英特格灵芯片(天津)有限公司 | Metastable state eliminating circuit and equipment |
| CN105897268B (en) * | 2016-05-12 | 2023-04-28 | 豪威模拟集成电路(北京)有限公司 | Metastable state elimination circuit and device thereof |
| CN111262561A (en) * | 2020-02-05 | 2020-06-09 | 电子科技大学 | Metastable state detection circuit of comparator |
| CN111262561B (en) * | 2020-02-05 | 2023-03-31 | 电子科技大学 | Metastable state detection circuit of comparator |
| CN111740744A (en) * | 2020-07-28 | 2020-10-02 | 灵矽微电子(深圳)有限责任公司 | Metastable state detection correction circuit of SAR analog-to-digital converter and asynchronous SAR analog-to-digital converter |
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Effective date of registration: 20210120 Address after: 100094 Room 601, unit 3, 6 / F, building 2, yard 9, FengHao East Road, Haidian District, Beijing Patentee after: Beijing Weihao integrated circuit design Co.,Ltd. Address before: Room 2701-1, building 2, TEDA service outsourcing park, 19 Xinhuan West Road, Tianjin Development Zone, Binhai New Area, Tianjin, 300457 Patentee before: INTERNATIONAL GREEN CHIP (TIANJIN) Co.,Ltd. |
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Address after: 100094 Room 601, unit 3, 6 / F, building 2, yard 9, FengHao East Road, Haidian District, Beijing Patentee after: Howell analog integrated circuit (Beijing) Co.,Ltd. Address before: 100094 Room 601, unit 3, 6 / F, building 2, yard 9, FengHao East Road, Haidian District, Beijing Patentee before: Beijing Weihao integrated circuit design Co.,Ltd. |