RU2487467C1 - Apparatus for compensating for static and dynamic input currents of differential stages on bipolar transistors - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: apparatus for compensating for static and dynamic input currents of differential stages on bipolar transistors has first and second compensating transistors, emitters of which are connected to each other and to a current source, a differential stage on bipolar transistors with first and second inputs connected to collectors of corresponding first and second compensating transistors, first and second closed insulating p-n junctions on the substrate of the first and second compensating transistors, first leads of which are connected to collectors of the corresponding first and second compensating transistors, wherein the base of the first compensating transistor is connected to the collector of the second compensating transistor, the base of the second compensating transistor is connected to the collector of the first compensating transistor, second leads of the first and second closed insulating p-n junctions on the substrate of the first and second compensating transistors are connected to combined emitters of the first and second compensating transistors.

EFFECT: high stability of output current of the compensation device.

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Description

The invention relates to the field of radio engineering and communication and can be used as a device for amplifying analog signals of sensors with high internal resistance, in the structure of analog microcircuits for various functional purposes (for example, operational amplifiers (op amps), broadband and selective amplifiers, filters, etc. )

Known devices for compensating static and dynamic input currents of differential stages on bipolar transistors [1-7], which are used to reduce the static and dynamic errors of differential stages caused by β-transistors.

The closest prototype of the claimed device is a circuit presented in patent RU No. 2346386. It contains the first 1 and second 2 compensating transistors, the emitters of which are connected to each other and connected to a current source 3, a differential stage 4 on bipolar transistors with the first 5 and second 6 inputs connected to the collectors of the corresponding first 1 and second 2 compensating transistors, the first 7 and second 8 closed isolating pn junctions on the substrate of the first 1 and second 2 compensating transistors, the first conclusions of which are connected to the collectors of the corresponding first 1 and second 2 compensating transistors, and the base the first 1 compensating transistor is connected to the collector of the second 2 compensating transistor, and the base of the second 2 compensating transistor is connected to the collector of the first 1 compensating transistor.

This structure of the remote control is also present in patents RU No. 2346386, RU No. 2346385, RU No. 2393628, RU No. 2394361, RU No. 2394360, RU No. 2396699, RU No. 2396698.

A significant drawback of the known device is that when it is implemented on pnp transistors having traditional isolation of pn junctions on a substrate, it does not provide full compensation of the input currents of differential stages in a wide temperature range, as well as when exposed to radiation, which requires the introduction of special compensating pn transitions [1-7].

The main objective of the invention is to increase the stability of the output currents of the compensation device, and, as a result, increase the efficiency of its use when working with classical differential cascades on bipolar transistors.

The problem is achieved in that in the device for compensating the static and dynamic input currents of differential stages on bipolar transistors of Fig. 1, containing the first 1 and second 2 compensating transistors, the emitters of which are connected to each other and connected to the current source 3, the differential stage 4 on bipolar transistors with the first 5 and second 6 inputs connected to the collectors of the corresponding first 1 and second 2 compensating transistors, the first 7 and second 8 closed isolation pn junctions on the substrate per 1 and second 2 compensating transistors, the first terminals of which are connected to the collectors of the corresponding first 1 and second 2 compensating transistors, the base of the first 1 compensating transistor connected to the collector of the second 2 compensating transistor, and the base of the second 2 compensating transistor connected to the collector of the first 1 compensating transistor new connections are provided - the second conclusions of the first 7 and second 8 closed insulating pn junctions on the substrate of the first 1 and second 2 compensating soy transistors ineny emitters combined with the first one 2 and the second compensating transistors.

The drawing of figure 1 presents a diagram of a known device for compensating the input currents of a differential stage 4.

The drawing of figure 2 presents a diagram of the inventive device in accordance with the claims.

The diagram of figure 3 shows the scheme of the compensation device with three options for the inclusion of insulating p-n junctions on the substrate:

- figa - p-n transitions to the substrate are included in the traditional way, which corresponds to the prototype of figure 1;

- figb - pn transitions to the substrate are included in accordance with the claims;

- figv - p-n transitions to the substrate are absent (ideal case).

The drawing of figure 4 shows the temperature dependence of the output (compensating) current I _com.1 = I _R1 in the prototype device for different values of current I ₁ (40 μA, 100 μA, 200 μA), which is associated with the numerical values of β transistors of the differential stage one.

The drawing of figure 5 shows the temperature dependence of the output (compensating) current I _com.1 = I _R1 in the inventive device at different current values I ₁ (40 μA, 100 μA, 200 μA).

The drawing of Fig. 6 shows the temperature dependence of the output (compensating) current I _com.1 = I _R1 in the considered devices of Fig.3c for different values of the current I ₁ (40 μA, 100 μA, 200 μA) and the absence of isolating pn junctions on the substrate ( ideal version of the circuit).

The device for compensating the static and dynamic input currents of differential stages on bipolar transistors of figure 2 contains the first 1 and second 2 compensating transistors, the emitters of which are connected to each other and connected to a current source 3, a differential stage 4 on bipolar transistors with the first 5 and second 6 the inputs associated with the collectors of the corresponding first 1 and second 2 compensating transistors, the first 7 and second 8 closed insulating pn junctions on the substrate of the first 1 and second 2 compensating transistors the first conclusions of which are connected to the collectors of the corresponding first 1 and second 2 compensating transistors, the base of the first 1 compensating transistor connected to the collector of the second 2 compensating transistor, and the base of the second 2 compensating transistor connected to the collector of the first 1 compensating transistor. The second terminals of the first 7 and second 8 closed insulating pn junctions on the substrate of the first 1 and second 2 compensating transistors are connected to the combined emitters of the first 1 and second 2 compensating transistors.

Consider the operation of the remote control of figure 2.

и $$I_{вх.4}^{(-)}$$

, которые компенсируются выходными токами I_com.1 и I_com.2 предлагаемого устройства компенсацииDifferential stage 4 is characterized by input currents $$I_{\mathrm{at}x\mathrm{.four}}^{(+)}$$

and $$I_{\mathrm{at}x\mathrm{.four}}^{(-)}$$

which are compensated by the output currents I _com.1 and I _{com.2 of the} proposed compensation device

$$I_{com\mathrm{.one}}={\mathrm{<figure-callout\; id="0"\; label="I"\; filenames="00000014.png,00000016.png"\; state="\{\{state\}\}">I</figure-callout>}}_0+\left(\mathrm{one}-{\alpha }_{\mathrm{one}}\right){\mathrm{<figure-callout\; id="7"\; label="I"\; filenames="00000014.png"\; state="\{\{state\}\}">I</figure-callout>}}_7^0,\text{(one)}$$

$$I_{com.2}=I_0+\left(\mathrm{one}-{\alpha }_2\right)I_8^0,\text{(2)}$$

where I ₃ = 2I ₀ is the total current of the emitters of transistors 1, 2;

α _i ≈1 is the current gain of the emitter of transistors 1, 2, associated with β transistors of the differential stage 4.

As a result, the equivalent input currents for nodes 5 and 6 are reduced.

$$I_{\mathrm{at}x.\sum \mathrm{one}}^{(-)}=I_{\mathrm{at}x\mathrm{.four}}^{(-)}-I_0-\left(\mathrm{one}-{\alpha }_{\mathrm{one}}\right){\mathrm{<figure-callout\; id="7"\; label="I"\; filenames="00000014.png"\; state="\{\{state\}\}">I</figure-callout>}}_7^0\approx I_{\mathrm{at}x\mathrm{.four}}^{(-)}-I_0,\text{(3)}$$

$$I_{\mathrm{at}x.\sum 2}^{(+)}=I_{\mathrm{at}x\mathrm{.four}}^{(+)}-I_0-\left(\mathrm{one}-{\alpha }_2\right){\mathrm{<figure-callout\; id="8"\; label="I"\; filenames="00000014.png"\; state="\{\{state\}\}">I</figure-callout>}}_8^0\approx I_{\mathrm{at}x\mathrm{.four}}^{(+)}-I_0.\text{(four)}$$

, $$I_0\approx I_{вх.4}^{(-)}$$

), a также обеспечение α₂≈1 в схеме фиг.2 устраняется влияние температурно-зависимых токов через p-n переходы на подложку $$I_7^0$$

, $$I_8^0$$

на суммарные входные токи $$I_{вх.\sum 1}^{(-)}$$

, $$I_{вх.\sum 2}^{(+)}$$

устройства.Due to the appropriate choice of current I ₀ ( $${\mathrm{<figure-callout\; id="0"\; label="I"\; filenames="00000014.png,00000016.png"\; state="\{\{state\}\}">I</figure-callout>}}_0\approx I_{\mathrm{at}x\mathrm{.four}}^{(+)}$$

, $${\mathrm{<figure-callout\; id="0"\; label="I"\; filenames="00000014.png,00000016.png"\; state="\{\{state\}\}">I</figure-callout>}}_0\approx I_{\mathrm{at}x\mathrm{.four}}^{(-)}$$

), as well as providing α ₂ ≈1 in the circuit of Fig. 2, the influence of temperature-dependent currents through pn junctions on the substrate is eliminated $${\mathrm{<figure-callout\; id="7"\; label="I"\; filenames="00000014.png"\; state="\{\{state\}\}">I</figure-callout>}}_7^0$$

, $$I_8^0$$

total input currents $$I_{\mathrm{at}x.\sum \mathrm{one}}^{(-)}$$

, $$I_{\mathrm{at}x.\sum 2}^{(+)}$$

devices.

Computer simulation (figure 5, figure 6) shows that the compensating currents in the proposed circuit I _R1 = I _com.1 , I _R2 = I _com.2 do not change in the temperature range. For the prototype circuit, these effects are not characteristic (figure 4).

Thus, the proposed device provides a more efficient compensation of the input currents of the differential cascade 4 on bipolar transistors.

BIBLIOGRAPHIC LIST

1. Patent RU No. 2346386

2. Patent RU No. 2346385

3. Patent RU No. 2393628

4. Patent RU No. 2394361

5. Patent RU No. 2394360

6. Patent RU No. 2396699

7. Patent RU No. 2396698

Claims (1)

A device for compensating static and dynamic input currents of differential stages on bipolar transistors, containing the first (1) and second (2) compensating transistors, the emitters of which are connected to each other and connected to a current source (3), a differential stage (4) on bipolar transistors with the first (5) and second (6) inputs connected to the collectors of the corresponding first (1) and second (2) compensating transistors, the first (7) and second (8) closed pn isolating junctions on the substrate of the first (1) and second ( 2) compensating tr ansistors, the first conclusions of which are connected to the collectors of the corresponding first (1) and second (2) compensating transistors, the base of the first (1) compensating transistor connected to the collector of the second (2) compensating transistor, and the base of the second (2) compensating transistor connected to the collector the first (1) compensating transistor, characterized in that the second terminals of the first (7) and second (8) closed isolating pn junctions on the substrate of the first (1) and second (2) compensating transistors are connected to the combined emit s first (1) and second (2) compensating transistors.

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