RU2481653C2 - Memory cell for fast erasable programmable read-only memory and method of its programming - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: memory cell comprises an n(p)-MOS-transistor, a capacitor, an address discharge bus, differing by the fact that it additionally comprises the first and second diodes and a numerical bus, at the same time the cathode (anode) of the first diode is connected with the numerical bus by a source of the n(p)-MOS-transistor, its anode is connected to the anode of the second diode, with the gate area of the n(p)-MOS-transistor and the first output of the capacitor, the second output of which is connected to the gate of the n(p)-MOS-transistor and to the address bus, and the cathode of the second diode is connected with the area of the drain of the n(p)-MOS-transistor and the discharge bus.

EFFECT: increased efficiency, reliability and integration of nonvolatile electrically programmable read-only memories.

4 cl, 5 dwg

Description

The invention relates to nanoelectronics, and more particularly to non-volatile electrically programmable read-only memory devices (EEPROM).

Known single-transistor memory cells for storage devices (memory). For example: a Dennard cell [1] for dynamic random access memory (DOS), a FAMOS [2] floating-memory cell for EEPROM, a memory cell based on a silicon-nitride-polysilicon transistor structure ( MNOP, KONOP, SONOS) [3]. In these cells, the gate region (substrate) of the MOS transistor is connected to the common bus (ground), the gate to the address bus, the drain to the discharge bus, and the source to the numerical bus.

In such a cell [1] it is difficult to ensure the non-volatility of the memory and it is relatively large due to the need to have a large area of information capacity. Cells [2, 3] do not provide fast EEPROM programming due to the time-consistent method of programming them.

Closest to the technical nature of the invention is the memory cell "Dennard" [1]. On figa and 1b respectively shows the electrical circuit and the design of the memory cell. It contains an n (p) MOS transistor whose drain is connected to the discharge bus, a gate with an address bus, a gate region with a common bus, and a source with a first capacitor terminal, the second terminal of which is connected to a common bus.

The memory cell design is a functionally integrated structure, in which the information capacity is formed by the source region of the n (p) type, the space charge region of the pn junction source-substrate, and the substrate itself of the n (p) type MOS transistor, the gate region forms address bus, and on the drain area of the n (p) -type is the electrode (contact) of the discharge bus.

Such a memory cell does not have extremely small sizes due to the need to place information capacity, which is desirable to have a larger size. The second disadvantage is the complexity of the technological implementation of the non-volatile element based on it / it requires the manufacture and placement of an additional capacitor from ferroelectric /.

The aim of the invention is to increase the speed, reliability and integration of EEPROM.

This goal is achieved in that the electrical circuit of the memory cell additionally contains the first and second diodes and a numerical bus, while the cathode (anode) of the first diode is connected to the numerical bus and the source of the n (p) MOS transistor, its anode is connected to the anode of the second diode , with the gate region of the n (p) -MOS transistor and the first output of the capacitor, the second terminal of which is connected to the gate of the n (p) -MOS transistor and the address bus, and the cathode of the second diode is connected to the drain region of the n (p) -MOS transistor and bit bus.

In order to simplify the electrical circuit, the gate of the n (p) MOS transistor is connected to the cathode (anode) of the first diode.

The design of the memory cell (like the prototype) is a single functionally integrated structure that contains an n (p) -MOS transistor with a "floating" gate region, while its n (p) -region of the source is simultaneously the region n (p) - the cathode (anode) type of the first diode, and the p (n) gate region is the region of the p (n) -type of the anode (cathode) of the first diode; the n (p) -region of the drain is the region n (p) of the cathode (anode) of the second diode, and the p (n) gate region forms the region of the p (n) -type of the anode (cathode) of the second diode; the capacitor is respectively formed by a gate, a dielectric, and a gate region of a MOS transistor.

Programming a memory cell occurs in two stages

- at the first stage, operational information is recorded (ie, the logical unit “log 1”) by supplying a high (low) zero potential to the address bus, and a capacitor is charged to the low (high) potential discharge bus (+ V ') through the second diode, while the "floating" gate region of the MOS transistor (which is the first capacitor plate) acquires a negative charge and potential with respect to the gate, which is the second capacitor plate.

The recorded operational information in the form of a charge in the capacitor can be stored (similarly to the prototype memory cell) for a sufficiently long time and its storage time is determined by the leakage currents of the pn junctions of the drain-source of the MOS transistor, while the potential difference in the capacitor is formed by a gate gate by the dielectric and the gate region Vc does not exceed the potential value (Vnp) in the gate system of the MOS transistor necessary for programming the memory cell, i.e. Vnp <Vnp.

At the second stage, an additional (high) potential (Vd) is supplied to the gate of the MOS transistor, such that the sum of the potentials Vc and Vd exceeds the programming voltage of the memory cell, i.e.

Vc + Vd> Vnp,

at the same time, permanent (non-volatile) information is recorded in the memory cell.

In the case of “recording” logical zero “log 0”, the capacitor is not charged with negative potential, and information is not written to the memory cell when additional Vd voltage is applied.

The advantage of the claimed memory cell in comparison with analogues and prototype is obvious from the designs of the EEPROM matrices, which are presented in FIGS. 2 and 3, while the integration of the EEPROM memory, as can be seen from the drawings, reaches the theoretical limit.

The performance of a traditional EEPROM compared to DOSE is rather slow and is determined by the duration of the process of sequentially programming EEPROM memory cells.

The proposed memory cell solves this problem due to the fact that at the first stage, operational information is recorded in the memory cell in the form of charges in the gate capacitances of the corresponding MOS transistors, as in DOS, relatively quickly.

At the second stage, an additional voltage is applied for a short time (1-2 milliseconds) (or irradiation with ionizing radiation is carried out), as a result of which all EEPROM memory cells are programmed simultaneously. Thus, the EEPROM programming time is reduced from tens of minutes to several milliseconds.

The electrical circuit of the memory cell (see figa)

It contains an n (p) MOS transistor T1, the source of which is connected to the cathode (anode) of the first diode D1, a digital bus Z, the anode (cathode) of the first diode is connected to the anode (cathode) of the second diode D2 by the gate region of the MOS transistor T1 and the first terminal of the capacitor C, the second terminal of which is connected to the gate of the n (p) MOS transistor T1 and address bus X, the cathode (anode) of the second diode D2 is connected to the drain of the n (p) MOS transistor and the discharge bus Y.

In order to simplify the electrical circuit, the gate of the MOS transistor is connected to the drain area (see Fig. 2b).

Design and topology of the memory cell (see Fig. 3a, b)

It consists of a substrate - 1, on the surface of which there is a dielectric layer - 2, on the surface of which there is a drain region - 3, forming a numerical bus, a source region - 4, forming a discharge bus, a gate region - 5, on the surface of which a gate dielectric is located - 6, on the surface of which a gate - 7 is located, which forms an address bus, an insulating dielectric - 8 is located on the surface of the drain, source, and gate regions, and a discharge bus electrode - 9 is located on the source region - 4.

In order to simplify the design of the memory cell, the gate 7 of the MOS transistor forms an electrical contact with the drain area - 3 (see figa, 4b).

The memory cell works as follows.

In the lattice of recording operational information “log 1”, when a positive potential arrives at the address bus x, and zero — on the discharge bus y, the information capacitor C is discharged through the diode D2, and a negative potential (charge) is formed on the “floating” gate region of the MOS transistor in relation to the shutter, which can be stored long enough in the mode of storing operational information, i.e. at zero potential at the gate (address bus X) and positive potential at the discharge of the discharge bus Y. The storage time of the charge information in the capacitor is determined by the leakage currents of the diodes, i.e. the drain-source p-n junctions of the MOS transistor, and usually amounts to hundreds of milliseconds (as in a conventional DOS based on a Dennard memory cell taken as a prototype).

The state “log 0” corresponds to the absence of an information charge in the capacitor in the memory cell, as in a conventional DOSE.

Thus, operational information in the form of “log 1” and “log 0” is recorded in all EEPROM cells. In this case, the recording time of the RAM also corresponds to the time of its recording in the usual DOS, i.e. ~ 10 ^-9 s per cell. After recording operational information in a memory cell, it is actually transferred to constant by simultaneously programming all MOS transistors, for example, by supplying additional voltage to all transistor gates.

It is important that the physical programming principle of the MOS transistor of the EEPROM memory cell is not significant. In the memory cell, in particular, an MNOS transistor, a FAMOS transistor with a “floating” gate, a MOS transistor programmed with hydrogen ions [4], etc. can be used.

Implementation examples

A high-speed EEPROM based on the proposed memory cell can be implemented, for example, on the basis of traditional K-MOS technology, silicon on an insulator (SIC), see Figs. 3, 4 or on monosilicon, see Fig. 5.

Information sources

1. Matsue S, Vamamoto H, Kobayski K, et al / A 256 Kbit dynamia RAM IEEE, J. 1980. V sc-. 15. No. 5, p. 872-874.

2. Al Fazio, Mark Bauer "Intel Strata Flesh tm Memory Tecnology Dievopment end Impmentation /" Intel Tecnology Gournal Q 4, 1997 1-13.

3. M.L. French end M.H. White "Scaling of miltidielectric nonvolatile Sonos Memory Structurec" Solid-State Elec., Vol, 37, p. 1913, 1995.

4. K. Vanheusden, WL: Warren, RAB Devine, DMFleetwood, JRSchwank et.al. Non-volatile memory device based on mobile protons in SiO ₂ thin films Nature | Vol 386 | April 10, 1997.

Claims (4)

1. A memory cell containing an n (p) MOS transistor, capacitor, address bit line, characterized in that it additionally contains the first and second diodes and a number line, while the cathode (anode) of the first diode is connected to the number line by a source n ( p) MOS transistor, its anode is connected to the anode of the second diode, with the gate region of the n (p) MOS transistor and the first output of the capacitor, the second output of which is connected to the gate of the n (p) MOS transistor and to the address bus, and the cathode of the second diode is connected to the drain region of the n (p) MOS transistor and the discharge bus. 2. The memory cell according to claim 1, the gate of the n (p) MOS transistor is connected to the cathode (anode) of the first diode. 3. The memory cell according to claim 3, containing on the substrate an address and discharge bus, an n (p) MOS transistor consisting of a drain, a source, a gate, a dielectric and a gate region, which forms the first terminal (capacitor plate), characterized in that the memory cell design (like the prototype) is a single functionally integrated structure that contains an n (p) -MOS transistor with a “floating” gate region, while its n (p) -region of the source is simultaneously the region of n (p ) -type of the cathode (anode) of the first diode, and p (n) the gate region is the region of the p (n) -type of the anode (cathode) of the first diode; the n (p) region of the drain is the region n (p) of the cathode (anode) of the second diode, and the p (n) gate region forms the region of the p (n) type of the anode (cathode) of the second diode; the capacitor is respectively formed by a gate, a dielectric, and a gate region of a MOS transistor. 4. A method of programming an EEPROM memory cell by supplying electrical signals to the gate and drain-source regions of the MOS transistor, characterized in that the programming of the memory cell occurs in two stages:
at the first stage, the operational information of the logical unit is log “1” by feeding a high (low) zero potential to the address bus, and a low (high) potential Vc to the discharge bus and charging the capacitor through the second diode, while the “floating” gate area The MOS transistor (which is the first capacitor plate) acquires a negative (positive) charge (potential) with respect to the gate, while the potential difference of the gate-substrate Vc does not exceed the value of the potential difference by the gate system of the transistor Vpp necessary for programming a memory cell, i.e. Vc <Vpp;
at the second stage, operational information is logged “1” into a non-volatile constant, for which a high (low) potential Vd is applied to the gate of the MOS transistor, and such that the sum of the potential difference Vc and Vd corresponds to the programming voltage of the memory MOS transistor, t .e. Vc + Vd = Vpp,
in the case of recording (storage) of logical zero, the log "0" in the memory cell is supplied with electrical signals in such a way that the capacitor is not charging.

Images