RU2468503C1 - Cascode amplifier - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: cascode amplifier is characterised by that the emitter of the first (3) output transistor is connected to the base of the second (10) output transistor, whose collector is connected to the first (7) power supply bus, the emitter is connected to the second (11) power supply bus through a first (12) current stabilising source and to the emitter of the third (13) output transistor; the collector of the third (13) output transistor is connected to the collector of the first (3) output transistor, the base is connected to the emitter of the fourth (14) output transistor and through a second (15) current stabilising source to the second (11) power supply bus, wherein the base of the fourth (14) output transistor is connected to the base of the first (3) output transistor, and its collector is connected to the collector of the second (10) output transistor.

EFFECT: eliminating an additional amplifier stage and reducing total power consumption by raising voltage gain.

4 cl, 11 dwg

Description

The invention relates to the field of radio engineering and communications and can be used as a device for amplifying analog signals in the structure of analog microcircuits for various functional purposes (for example, broadband and selective amplifiers of the high and microwave ranges).

In modern microelectronics, classical cascode amplifiers (KUs) with a resistive load included in the collector circuit of an input transistor - cascade with a common emitter are widely used [1-19].

The closest in technical essence to the claimed device is KU figure 1 according to patent RU 2421878.

A significant drawback of the well-known KU, the architecture of which is also present in many other cascode amplifiers [1-19], is that under restrictions on the supply voltage (E _p ) characteristic of SiGe technological processes (E _p ≤2.0 ÷ 2, 5 V), its voltage gain (K ₀ ) turns out to be relatively small (K _0max = 40 ÷ 50 dB). This is primarily due to incomplete self-compensation of the resistance of the collector load resistors, which, due to low E _p, cannot be selected as high-resistance.

The main objective of the invention is to increase the voltage gain by 20 ÷ 30 dB (up to the level of 70-80 dB). This allows in some cases to exclude additional amplification stages, to reduce the overall power consumption in comparison with multi-stage amplifiers.

The problem is solved in that in the cascode amplifier of figure 1, containing the first 1 input voltage-current converter, the current output 2 of which is connected to the emitter of the first 3 output transistor, the circuit for establishing a static mode 4 connected to the base of the first 3 output transistor, the first 5 collector load two-terminal, the first terminal of which is connected to the collector of the first 3 output transistor and device output 6, the first 7 power supply bus connected to the first terminal of the second 8 two-terminal collector load The second output of the second 8 two-terminal collector load and the second terminal of the first 5 two-terminal collector load are connected to each other and connected to the emitter of the first 3 output transistor via a non-inverting matching circuit 9 with current transfer coefficients less than unity, new elements and connections are provided - the emitter of the first 3 output transistors connected to the base of the second 10 output transistor, the collector of which is connected to the first 7 bus power supply, the emitter is connected to the second 11 bus power supply through the first current-stabilizing source 12 and is connected to the emitter of the third 13 output transistor, the collector of the third 13 output transistor is connected to the collector of the first 3 output transistor, the base is connected to the emitter of the fourth 14 output transistor and through the second current-stabilizing source 15 is connected to the second 11 bus of the power source, and the base the fourth 14 output transistor is connected to the base of the first 3 output transistor, and its collector is connected to the collector of the second 10 output transistor.

The amplifier circuit of the prototype is shown in FIG. 1 for the case when a passive bipolar isolating capacitor is used as a non-inverting matching circuit 9 with a current transfer coefficient less than unity. The drawing of figure 2 presents a diagram of the inventive device in accordance with claim 1 and claim 2 of the claims.

The drawing of figure 3 shows a diagram of the inventive device in accordance with claim 3 of the claims.

The drawings of figure 4 and figure 5 shows a diagram of the inventive device in accordance with paragraph 4 of the claims.

The drawing of Fig.6 shows a diagram of the control unit of Fig.3 in a computer simulation environment PSpice on models of integrated transistors of FSUE NPP Pulsar.

The drawing of Fig.7 shows the amplitude-frequency characteristic of the voltage gain KU of Fig.6 when the current of the first current-stabilizing two-terminal I ₁ (I ₁₂ , Fig.3) changes within I ₁ = 0 ... 530 μA with a step of 106 μA.

The drawing of Fig. 8 shows a diagram of the KU of Fig. 5, in which the output cascode is implemented on p-n-p transistors.

The drawing of Fig.9 shows a diagram of the KU of Fig.8 in the PSpice environment on models of integrated transistors of the Federal State Unitary Enterprise NPP Pulsar (npn TN15S, pnp TP15S).

In the drawing of Fig. 10, the amplitude-frequency characteristic of the KU of Fig. 9 is shown, and in the Fig. 11 is the dependence of the voltage gain of the KU of Fig. 9 on the current of the two-terminal I ₁ corresponding in the drawing of Fig. 2 - Fig. 3 to the current of the first current-stabilizing bipolar 12 (I ₁ = I ₁₂ ).

The cascode amplifier of FIG. 2 contains a first 1 voltage-current input converter, the current output 2 of which is connected to the emitter of the first 3 output transistor, a static mode 4 circuit connected to the base of the first 3 output transistor, the first 5 collector two-terminal, the first output of which is connected with the collector of the first 3 output transistor and the output of device 6, the first 7 power supply bus connected to the first output of the second 8 two-terminal collector load, the second output of the second 8 two-terminal to the collector load and the second output of the first 5 two-terminal collector load are connected to each other and connected to the emitter of the first 3 output transistor through a non-inverting matching circuit 9 with current transfer coefficients less than unity. The emitter of the first 3 output transistor is connected to the base of the second 10 output transistor, the collector of which is connected to the first 7 bus of the power supply, the emitter is connected to the second 11 bus of the power supply through the first current-stabilizing source 12 and connected to the emitter of the third 13 output transistor, the collector of the third 13 output transistor connected to the collector of the first 3 output transistor, the base is connected to the emitter of the fourth 14 output transistor and through the second current-stabilizing source 15 is connected to the second 11 bus power supply, and the base of the fourth 14 output transistor is connected to the base of the first 3 output transistor, and its collector is connected to the collector of the second 10 output transistor.

In addition, in the drawing of figure 2, in accordance with claim 2 of the claims, an isolation capacitor is used as a non-inverting matching circuit 9 with current transfer coefficients less than unity.

In the drawing of figure 3, in accordance with claim 3 of the claims, the current output of the second 16 voltage-current input converter is used as the second current-stabilizing source 15.

In the particular case, the static mode of the input converters 1 and 16 can be set by the reference current source 17. To balance the collector-base voltages of the transistors 3 and 14, in the particular case, resistors 18 and 19 can be used.

In the drawing of FIG. 4, in accordance with claim 4, as the first 1 and second 16 input voltage-current converters, a differential stage 20 with antiphase current outputs is used, implemented on transistors 21 and 22 and a current source 23.

The drawing of Fig. 5 shows a diagram of Fig. 4 for the case when a capacitor 24 is inserted into it, which allows providing a symmetric (paraphase) output of the cascode amplifier.

Consider the work of KU figure 2.

The limiting voltage gain KU of Fig. 1 at zero capacitance of the isolation capacitor 9 (C ₉ = 0) is determined by the resistance R _{5 of the} first 5 two-terminal collector load:

where R ₅ >> R ₈ ;

S ₁ ≈ (r _e1 ) ^-1 is the gain slope of the input voltage-current converter in the output short circuit, which in a particular case depends on the resistance of the emitter junction (r _evh ) of the input transistor of this converter.

Let us show analytically that higher values of K ₀ in the mid-frequency range are realized in the circuit of FIG. 2 at a current of I ₁₂ = 0 and C ₉ ≠ 0, which corresponds to the prototype of FIG. 1, and the claimed circuit of FIG. 2 has an even higher K ₀ at a current of the first 12 current-stabilizing two-terminal network, which lies within I ₁₂ = 100 ÷ 150 μA.

Indeed, in the General case, the complex transmission coefficient of voltage KU figure 2 when I ₁₂ = 0 and C ₉ ≠ 0 is determined by the formula:

- комплекс эквивалентного выходного импеданса узла А.Where

- complex equivalent output impedance of node A.

If the capacitance of the capacitor 9 is zero, then for KU of figure 2, provided that R ₅ >> R ₈ we obtain the formula (1):

where R ₅ >> R ₈ are the resistances of the first 5 and second 8 two-terminal collector loads.

That is, (3) is the formula for K _{0 of} the prototype amplifier, provided that C ₉ = 0.

The equivalent load complex in the node A of KU of figure 2 at C ₉ ≠ O and current I ₁₂ = 0, that is, when the transistors 10, 13 are de-energized and do not affect the operation of the circuit, can be found by the formula:

Where

- комплекс сопротивления конденсатора 9 на частоте ω;

- complex resistance of the capacitor 9 at a frequency ω;

,

- токи через двухполюсник коллекторной нагрузки 5 и через конденсатор 9;

,

- currents through the bipolar collector load 5 and through the capacitor 9;

- комплекс коллекторного тока транзистора 3;

- complex collector current of the transistor 3;

- комплексный коэффициент усиления по току эмиттера транзистора 3.

- complex current gain of the emitter of the transistor 3.

After transformations of the last formula, we find that

Therefore, the voltage gain KU of figure 2 at a current of I ₁₂ = 0 and C ₉ ≠ 0

:At

:

In the field of operating frequencies, when 1 / ωC ₉ << r _e3 , the coefficient K _{0.n is} not better than

.

.

The gain in K ₀ , which gives the scheme KU of figure 2 at a current of I ₁₂ = 0 in comparison with the case when in the scheme of figure 2 I ₁₂ = 0, C ₉ = 0, can be estimated using a special complex coefficient

, т.е. на постоянном токе выигрыш по коэффициенту усиления K₀ отсутствует. При α₃=0,98-0,99, r_э3/R₈<<1 в области средних частот, когда можно пренебрегать влиянием реактивного сопротивления конденсатора 9 (ωC₉=∞), реализуется значительный выигрыш по коэффициенту усиления:If ω = 0, then

, i.e. on direct current, gain in gain K _{0 is} absent. When α ₃ = 0.98-0.99, r _e3 / R ₈ << 1 in the middle frequency region, when the influence of the reactance of capacitor 9 (ωC ₉ = ∞) can be neglected, a significant gain in gain is realized:

In the best case, when R ₈ >> r _e3

However, taking into account the real values of the parameters of the elements, the denominator of formula (9) is quite significantly different from zero, which does not allow the KU prototype to implement the limiting values of N _y and, as a result, the voltage gain.

In the KU circuit of FIG. 2, which is a development of the circuit of FIG. 1, additional elements 10, 12, 13, 14, 15 are influenced by the transfer of current i ₉ to node A.

It can be shown that the effective voltage gain (K _0.n ) of the cascode amplifier of Fig. 2 in the middle frequency region, when the influence of resistance 1 / С ₉ ω can be neglected, and the current I ₁₂ ≠ 0, is determined by the formula

;Where

;

I ₀ is the static current of the emitter of transistors 3 and 14;

- коэффициент деления тока через резистор 5 между двухполюсником 8 и эмиттером транзистора 3.

- the division ratio of the current through the resistor 5 between the two-terminal 8 and the emitter of the transistor 3.

Thus, in the claimed circuit, the current gain of the first 12 current-stabilizing two-terminal I ₁₂ has an effect on the voltage gain:

By choosing the current I ₁₂ in the circuit of figure 2, you can provide almost any value of K _0.n , which is unattainable in the KU prototype.

So, for example, to obtain N _max -fold gain in K _y, it is necessary to ensure the ratio of currents

As the graphs of Fig. 11 show, at N _max = 10 the numerical values of the current I ₁₂ ≈600 μA.

These theoretical conclusions confirm the results of computer simulation of Fig.7, Fig.10, Fig.11.

Thus, the claimed circuit solution is characterized by higher values of the voltage gain.

BIBLIOGRAPHIC LIST

1. US patent No. 6825723 fig.3.

2. US patent No. 4151483 fig.2.

3. US patent No. 4151484.

4. US patent No. 3882410 fig. 3.

5. Patent application WO 2004/030207.

6. US patent No. 4021749 fig.2.

7. US Patent No. 3693108 fig. 9.

8. US patent No. 7113043 fig.2.

9. US Patent Application 2006/003 35 62.

10. US Patent Application 2006/0132242.

11. US patent application 2006/0119435.

12. US Patent Application 2005/0248408.

13. US patent No. 6204728.

14. US patent No. 6278329.

15. US patent application 2005/0225397.

16. US Patent No. 5451906.

17. US Patent No. 7098743 fig. 1.

18. British Patent GB No. 1431481 fig. 2.

19. US patent No. 6515547 fig.2.

Claims (4)

1. Cascode amplifier containing the first (1) input voltage-current converter, the current output (2) of which is connected to the emitter of the first (3) output transistor, the circuit for establishing a static mode (4) connected to the base of the first (3) output transistor, the first (5) collector load two-pole, the first output of which is connected to the collector of the first (3) output transistor and the output of the device (6), the first (7) power supply bus connected to the first output of the second (8) two-collector load, the second output of the second (8) engine the collector load port and the second terminal of the first (5) collector load two-port are connected to each other and connected to the emitter of the first (3) output transistor through a non-inverting matching circuit (9) with current transfer coefficients less than unity, characterized in that the emitter of the first (3 ) the output transistor is connected to the base of the second (10) output transistor, the collector of which is connected to the first (7) bus of the power supply, the emitter is connected to the second (11) bus of the power supply through the first (12) current-stabilizing source and connected to the emitter of the third (13) output transistor, the collector of the third (13) output transistor is connected to the collector of the first (3) output transistor, the base is connected to the emitter of the fourth (14) output transistor, and through the second (15) current-stabilizing source is connected to the second ( 11) the power supply bus, and the base of the fourth (14) output transistor is connected to the base of the first (3) output transistor, and its collector is connected to the collector of the second (10) output transistor. 2. The cascode amplifier according to claim 1, characterized in that an isolation capacitor is used as a non-inverting matching circuit (9) with current transfer coefficients less than unity. 3. The cascode amplifier according to claim 1, characterized in that the current output of the second (16) voltage-current input converter is used as the second (15) current-stabilizing source. 4. The cascode amplifier according to claim 1 or 3, characterized in that as the first (1) and second (16) input voltage-current converters, a differential stage (20) with antiphase current outputs is used.

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