RU2437180C2 - Manufacturing method of nanowires, matrix of nanowires from nitrides of group iii of periodic table (versions), and substrate (versions) - Google Patents

Abstract

FIELD: power industry.

SUBSTANCE: manufacturing method of nanowires, which involves the formation stage on the substrate of mask for selective growth, which contains a group of holes located in certain order and opening a group of substrate sections; stage of selective non-pulse growth, in which in each of the above sections there grown through the above holes are cores of nanowires by using the growth mode including simultaneous supply of initial gaseous substances forming cores of nanowires, to crystal growth reactor (non-pulse mode), switching stage in which after formation of nanowire cores with the specified characteristics there switched is growth mode from non-pulse mode to the mode at which there performed is alternate supply of initial gaseous substances forming threadlike part of nanowires, to crystal growth reactor (pulse mode), and stage of pulse growth, at which there continued is growth of threadlike parts of nanowires in pulse mode with formation of multiple semiconductor nanowires.

EFFECT: obtaining high-quality nanowires and instruments on their base.

25 cl, 21 dwg

Description

FIELD OF THE INVENTION

The present invention generally relates to semiconductor materials, devices and methods for their manufacture, and more particularly, to nanowires and active devices with semiconductor nanowires.

State of the art

Nanowires consisting of alloys of group III-N (nitrides of elements of group III of the Periodic table, for example, gallium nitride (GaN)), can serve as the basis for a new type of semiconductor devices, for example, nanoscale optoelectronic devices. For example, GaN nanowires can have a large band gap, a high melting point, and chemical resistance necessary for operation in aggressive environments or at high temperatures. The wider band gap of GaN and related alloys also contributes to the creation of visible light sources that can be used in displays and for lighting. In addition, the unique geometry of each nanowire opens up prospects for the study of new principles for the construction of devices for photoelectronics and transport. To realize this potential, a scalable process of manufacturing high-quality nanowires and / or nanowire matrices from nitrides of group III elements is required in full, provided that the geometry, position and crystalline properties of each nanowire are precisely and uniformly controlled.

The usual process for manufacturing nanowires is based on a vapor-liquid-crystal growth mechanism (VLS - from Vapor-Liquid-Solid) using catalysts, for example, Au, Ni, Fe or In. However, difficulties arise, since it is impossible to control the position and uniformity of the resulting nanowires in these catalytic processes. Another disadvantage of conventional catalytic processes is that the catalyst inevitably enters the nanowires. This affects the quality of crystalline nanostructures, which limits the scope of their application.

Thus, at present, there is a need to overcome these and other disadvantages of known technologies and create high-quality nanowires and / or matrices of nanowires, and scalable processes for their manufacture. The task is also to create photoelectronic devices based on nanowires, and their manufacture using high-quality nanowires and matrices of nanowires.

Disclosure of invention

In accordance with various embodiments, the present invention includes a method for manufacturing nanowires. In this method, a mask for selective growth can be created on top of the substrate. The selective growth mask may include a plurality of holes arranged in a particular order, leaving many areas of the substrate exposed. Then, on each of these sections of the substrate, open through holes in a specific order, semiconductor material can be grown using a selective non-pulse growth mode. The growing mode can be transferred from a non-pulse growing mode to a pulsed growing mode. Continuing the growth in a pulsed mode, you can get a lot of semiconductor nanowires.

In accordance with various options for implementation, the present invention also includes a matrix of nanowires from nitrides of elements of group III, which may include a mask for selective growth, located on top of the substrate. The selective growth mask may include a plurality of holes arranged in a particular order that leave a plurality of portions of the substrate open. Nanowires made of nitrides of group III elements can be connected to open areas of the substrate and depart from them, passing through a mask for selective growth. Nanowires of nitrides of group III elements can be oriented along a single direction and can preserve the geometry of the cross section of one of the many selected surface regions.

In accordance with various embodiments, the present invention also includes a GaN substrate. The structure of the GaN substrate may be a GaN film formed by splicing a plurality of GaN nanowires in which there are no defects. A GaN film may have a defect density of about 10 ⁷ / cm ^-2 or less.

Other objects and advantages of the invention may be set forth in part in the description which follows, and will also become apparent from the description, or will be understood in the course of carrying out the invention. The objectives and advantages of the invention will be achieved by means of the elements and combinations specifically described in the attached claims.

It should be understood that both the foregoing general description and the following detailed description are provided only to explain the invention in the claimed form and do not limit its scope.

Brief Description of the Drawings

The attached drawings, which are included in the description and constitute a part thereof, illustrate several embodiments of the invention and, together with the description, serve to explain the principles of the invention.

Figure 1-3 presents views of the cross section used as an example of a device with semiconductor nanowires at various stages of manufacture, in accordance with the present invention.

Figure 4 presents a second example of a device with semiconductor nanowires, illustrating the present invention.

Figure 5 presents an example of the process of forming a plurality of nanowires and / or matrices of nanowires using the two-phase growth mode proposed in the present invention.

6-8 depict a third semiconductor nanowire device illustrating the present invention.

9 is a fourth semiconductor nanowire device illustrating the present invention.

10 (A-D) presents the results of an experiment for growing a plurality of ordered matrices of GaN nanowires using the two-stage catalyst-free growth process of the present invention.

Figure 11-14 presents four options for semiconductor devices, including the structure of the GaN substrate, formed from a variety of nanowires and / or matrices of nanowires shown in Fig.1-10, in accordance with the present invention.

On Fig presents an example of a device with an active structure based on a nanowire "core-shell" / MQW (structure on quantum wells, from the English. Multiple Quantum Well) proposed in the present invention.

On Fig presents another example of a device with an active structure based on a nanowire "core-sheath" / MQW proposed in the present invention.

17-19 show an example of a nanowire LED using an active core-sheath / MQW nanowire structure in accordance with the present invention.

FIG. 20 is an example of a nanowire laser device using an active core-sheath / MQW nanowire structure depicted in FIGS. 15-16 in accordance with the present invention.

FIG. 21 shows another example of a nanowire laser device using an active core-sheath / MQW nanowire structure depicted in FIGS. 15-16, in accordance with the present invention.

The implementation of the invention

The following is a detailed description of embodiments illustrating the present invention, examples of which are presented in the attached drawings. In cases where this is possible, the same or similar parts in the drawings have the same designations. In the following description, reference is made to the corresponding drawings, which form part of this description and illustrate specific embodiments of the invention. These embodiments of the invention are described in sufficient detail for those skilled in the art to implement the present invention. It should be understood that other embodiments may be used, and various changes may be made within the scope of the invention. Thus, the description below is for illustrative purposes only.

Although the invention is illustrated in one or more examples of its implementation, in the above examples of embodiments, changes and / or modifications can be made that do not go beyond the essence of the invention and the scope of the claims defined by the attached claims. In addition, although a specific feature of the invention may be disclosed in relation to one or more embodiments, this feature, if desired or in an effort to improve any function, may be combined with one or more features of other embodiments. Below in the present description and formula, it is assumed that the terms “including”, “includes”, “having”, “has”, “with (together with something)”, or their variants, have the meaning “including”, by analogy with the term "comprising." The term “at least one of” indicates that one or more objects from the listed objects may be selected.

Despite the fact that the numerical ranges and parameters representing a wide range of claims of the invention are approximate, the numerical values in specific embodiments are given with the greatest possible accuracy. Any numerical value, however, inevitably includes certain errors due to the measurement error in the corresponding tests. In addition, it is understood that all of the ranges indicated herein cover any and all sub-ranges included in the corresponding category. For example, an interval of "less than 10" may include any and all sub-intervals between (and including) a minimum value of zero and a maximum value of 10, that is, any and all sub-intervals having a minimum value equal to or greater than zero and a maximum value equal to or greater 10, for example, from 1 to 5.

In exemplary embodiments, semiconductor devices are provided that include high-quality (i.e., free from defects) nanowires from group III nitrides and homogeneous matrices of group III-N nanowires, as well as scalable processes for their manufacture in which it is possible with high accuracy control the position, orientation, cross-sectional properties, length or features of the crystal structure of each nanowire. In particular, a plurality of nanowires and / or matrices of nanowires can be formed using a selective growing mode, followed by switching the growing mode from the selective growing mode to the pulsed growing mode. Cross-sectional properties, for example, cross-sectional dimensions (eg, diameter or width) and cross-sectional shape, of each nanowire obtained in the selective growth mode, can be maintained during continued growth using a pulsed growth mode. In this case, it is possible to form nanowires with a high elongation parameter. In an exemplary embodiment, the length of each nanowire may be from about 10 nm to 1000 μm, for example, from about 10 nm to 100 μm.

In addition, high-quality films of nitrides of group III elements can be formed, for example, high-quality GaN films by stopping the growth and splicing of many nanowires and / or matrices of nanowires. Such GaN films can be used as GaN substrate structures used in the manufacture of GaN-based devices, for example, visible-light emitting diodes and lasers for developing technologies of solid-state lighting devices and sensitive UV sensors.

Moreover, since each of the nanowires and / or the matrix of nanowires grown in a pulsed mode can have nonpolar side walls, the growth of core-shell structures can be successfully used to create active shell structures on quantum wells on the side walls of each nanowire. Such active MQW structures of the core-shell nanowires can be used in nanoscale photoelectronic devices with high efficiency, for example, nanodiode-based LEDs and / or nanowire-based lasers.

In the present description, the term "nanowire" generally refers to any elongated conductive or semiconducting material having at least one smaller size, for example, one of the cross-sectional dimensions, for example, a width or diameter of less than or equal to about 1000 nm. In various embodiments, the smaller size may be less than about 100 nm. In various other embodiments, the smaller size may be less than about 10 nm. Nanowires can have a size ratio (for example, a ratio of length to width and / or larger to smaller), approximately 100 or more. In various embodiments, the size ratio may be about 200 or more. In other various embodiments, the size ratio may be about 2000 or more. In the exemplary embodiment, the cross section of the nanowire can be very asymmetric, with the size of the cross section in one direction being much less than 1000 nm, and in the orthogonal direction, the size can be significantly larger than 1000 nm.

In addition, it is intended that the term “nanowires” also encompass other elongated structures of similar dimensions, including nanoscale pins, nanoscale columns, nanoscale needles, nanorods and nanotubes (eg, single-walled nanotubes, or multilayer nanotubes), and various functional fibrous derivatives thereof forms, for example, nanofibres in the form of threads, yarn, fabric, etc.

Nanowires can have a cross section of various shapes, for example, rectangular, polygonal, square, oval or round. Accordingly, nanowires can have a cylindrical and / or conical bulk (3-D) configuration. In various embodiments, the implementation of many nanowires can be substantially parallel to each other, located at an angle, along a sinusoid, etc.

Nanowires can be formed on / from the carrier substrate, which may include selected surface areas to which nanowires can be connected (e.g., grown) or from which they can extend. The carrier base of the nanowires may also include a substrate formed from various materials, including Si, SiC, sapphire, ceramic, or glass. The carrier base of the nanowires may also include a selective growth mask formed on the substrate. In various embodiments, the carrier base of the nanowires may further include an intermediate layer located between the selective growth mask and the substrate.

In various embodiments, using nanowires or matrices of nanowires, active devices with nanowires, for example, nanowire LEDs or nanowire lasers, can be manufactured. In various embodiments, the implementation of nanowires and / or matrices of nanowires and active devices based on nanowires can be manufactured using a system of semiconductor materials of compounds of III-V groups, for example, a system of materials of compounds of group III-N. Examples of elements of group III are Ga, In or Al, which can be obtained from precursors of elements of group III, for example, trimethylgallium (TMGa), triethyl gallium (TEGa), trimethylindium (TMIn) or trimethylaluminum (TMAl). An example of a nitrogen precursor is, for example, ammonia (NH ₃ ). Other elements of group V can be used, for example, P or As, with such precursors for elements of group V, such as tertiary butylfosine (TBP), or arsine (AsH ₃ ).

In the description below, Group III-N semiconductor alloys can be represented by a combination of Group III-N elements, for example, GaN, AlN, InN, InGaN, AlGaN or AlnGaN. In general, the elements in the compound may be in various mole fractions. For example, an InGaN semiconductor alloy can be described by the expression In _x Ga _1-x N, where the mole fraction × can be any number less than 1.00. In addition, depending on the size of the mole fraction, various active devices can be made from materials with a similar composition. For example, the compound In _0.3 Ga _0.7 N (where x is approximately 0.3) can be used in the active MQW region of the blue light emitting diode, while the compound ln _0.43 Ga _0.57 N (where x is approximately 0.43) can be used in the active MQW region of the green LED.

In various embodiments of the present invention, the nanowires of the matrix of nanowires and / or active nanowire devices may include dopants selected from the group consisting of p-type impurities from group II of the Periodic Table, for example Mg, Zn, Cd and Hg; p-type impurities from group IV of the Periodic table, for example, C; or n-type impurities from the group consisting of Si, Ge, S, Se and Te.

In various embodiments, the implementation of nanowires and / or matrices of nanowires, as well as active devices based on nanowires, can have a high-quality heterogeneous structure and can be formed by various crystal growing technologies, including chemical vapor deposition of metal-organic compounds (MOCVD). metal-organic chemical vapor deposition), also known as gas-phase epitaxy of metal-organic compounds (OMVPE - from English organometallic vapor phase epitaxy), molecular beam epitaxy (MBE - from English molecular beam epitaxy), molecular beam epitaxy from a gas source (GSMBE-engl. gas source molecular beam epitaxy), molecular beam epitaxy of metal-organic compounds (MOMBE - from English metal-organic MBE), atomic layer epitaxy (ALE - from the English atomic layer epitaxy), or hydride epitaxy from the gas phase (HVPE - from the English hydride vapor phase epitaxy), and other processes.

In various embodiments, a multi-stage growth mode, for example, a two-stage growth mode, can be used to grow high-quality nanowire crystals and / or nanowire matrices, as well as active nanowire devices. The first stage of the growth mode, for example, the selective growth mode, can be used to create conditions for the selectivity of growth for the nuclei of nanowires and / or matrices of nanowires. In the selective growth mode, conventional crystal growing methods, for example, conventional MOCVD, for nanowire cores with a desired thickness, for example, about 10 nm or more, can be used.

At the second stage of the growing regime, conditions can be created for continuing the growth of each nanowire with preserving the cross-section properties remaining from the first growing regime, while obtaining an arbitrary length. The second stage of the growing mode begins after switching the growing mode, which completes the first stage of the growing mode. In the second stage of the growing regime, a pulsed growing regime can be used, for example, pulsed MOCVD growing.

As used herein, the term “pulsed growth mode” refers to a process in which the gaseous starting materials of group III and group V are introduced in turn into a crystal growth reactor in a predetermined sequence. For example, TMGa and NH ₃ can be used as starting materials for an example process of forming GaN nanowires and / or matrices of nanowires and / or active devices based on GaN nanowires. In the pulsed growing mode, TMGa and NH ₃ can be introduced in turn in the sequence when TMGa is introduced at a given flow rate (for example, about 10 standard cm ³ / min) for a certain period of time (for example, about 20 s), after which NН is introduced ₃ at a predetermined flow rate (for example, about 1500 standard cm ³ / min) for a predetermined period of time (for example, about 30 s). In various embodiments, one or more cycles of sequences may be conducted (e.g., repeated) to obtain a predetermined length of each nanowire. In various embodiments, the growth rate of each nanowire may depend on the direction.

In various embodiments, dielectric materials can be used in the manufacture of the described nanowires, matrices of nanowires and / or active devices based on nanowires. For example, a mask for selective growth during the formation of multiple nanowires and / or matrices of nanowires can be made of dielectric materials. In another example, dielectric materials can be used for electrical insulation in active devices, for example, nanowire LEDs or nanowire lasers. Dielectric materials in the present description may include silicon dioxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), fluorinated silicon dioxide (SiOF), silicon oxycarbide (SiOC), hafnium oxide (HfO ₂ ), silicate hafnium (HfSiO), hafnium nitride silicate (HfSiON), zirconium oxide (ZrO ₂ ), alumina (Al ₂ O ₃ ), barium and strontium titanate (BST), lead zirconate titanate (PZT), zirconium silicate (ZrSiO ₂ ), tantalum oxide (TaO ₂ ) or other insulating materials. In accordance with various other embodiments, a mask for growing from a conductive metal, such as tungsten, can be used to selectively grow the nanowires disclosed herein.

Used as an example, embodiments for semiconductor devices based on nanowires and / or matrices of nanowires, and scalable processes for their manufacture are presented in FIGS. 1-3, FIGS. 4-5, FIGS. 6-8, FIG. 9 and FIG. 10 (AD).

Figure 1-3 presents views of the cross section of a semiconductor device 100 based on a nanowire at different stages of manufacture, in accordance with the present invention. It will be apparent to those skilled in the art that the nanowire-based semiconductor device 100 shown in FIGS. 1-3 is a generalized schematic illustration, and that other layers / nanowires can be added, or existing layers / nanowires can be removed or modified.

As shown in FIG. 1, a nanowire device 100 may include a substrate 110, a selective growth mask 135, and a plurality of holes 138 arranged in a specific order. A selective growth mask 135 and a plurality of holes 138 arranged in a specific order can be placed on top of the substrate 110, while a plurality of through holes 138 arranged in a specific order can be scattered through a selective growth mask 135.

Substrate 110 may be any substrate on which Group III-N material can be grown. In various embodiments, the implementation of the substrate 110 may include sapphire, silicon carbide, silicon, silicon on the insulator (SOI from the English. Silicon-on-insulator), semiconductor compounds of III-V groups, for example, GaN or GaAs, metals, ceramics or glass, as well as other materials.

To make a mask 135 for selective growth, a pattern can be applied to a dielectric layer (not shown) formed on the substrate 110, followed by etching. In various embodiments, the dielectric layer may be made of any dielectric material and formed by any technology known to those skilled in the art. Then the layer is marked by applying a pattern using one or more methods, including interferometric lithography (IL - from English interferometric lithography), which includes immersion interferometric lithography and nonlinear interferometric lithography, nanoimprint lithography (NL - from English nanoimprint lithography) and electronically -radiation lithography, which can be used to produce nanostructures or a regular set of nanostructures on large, macroscopic sites. After drawing the pattern, etching, for example, reactive ion etching, can be carried out to form a plurality of holes 138 arranged in a specific order. The etching process can be stopped on the surface of the underlying layer, that is, the substrate 110, and a plurality of sections 139 of the substrate 110 are exposed. In various embodiments, the mask for selective growth 135 may be a mask for growing from a conductive metal made, for example, of tungsten necessary for the selective growth of nanowires in a pulsed mode.

The plurality of holes 138 arranged in a specific order may have the same depth as the thickness of the mask 135 for selective growth, for example, about 30 nm or less, and the size of the cross section, for example, a diameter of about 10 nm to 1000 nm. As a further example, a diameter of from about 10 nm to about 100 nm may be indicated. In the embodiment used for the example, the plurality of holes 138 arranged in a specific order have a hexagonal arrangement with a pitch (i.e., the center-to-center spacing of two adjacent holes) of approximately 50 nm to 10 μm. In various embodiments, matrices of a plurality of holes 138 arranged in a specific order may be formed. Then, the nanoscale properties of the plurality of holes 138 arranged in a specific order will be transferred to subsequent processes of forming nanowires and / or matrices of nanowires.

In various embodiments, before starting the process of growing nanowires and / or matrices of nanowires, a cleaning procedure of the device 100 shown in FIG. 1 can be performed. For example, the cleaning process may include cleaning outside the process plant (i.e., cleaning is carried out outside the reactor where the growing takes place). After that, cleaning is carried out inside the process unit (i.e., cleaning is carried out inside the reactor). Depending on the materials used for the mask 135 for selective growth, various cleaning methods can be used. In the embodiment used as an example, the mask for selective growth from silicon nitride can be subjected to standard cleaning outside the reactor, after which it is cleaned in the reactor by placing the device 100 in the MOCVD reactor used as an example and heating the device 100 to a temperature of approximately 950 ° C for about 3 minutes in a stream of hydrogen. In a reducing atmosphere of hydrogen, unwanted intrinsic oxides can be removed from the surface of the device 100. Depending on the combination of the materials of the substrate 110 and the mask 135 for selective growth, one skilled in the art will be able to choose alternative procedures that can be used.

Figure 2 shows how the selective growth of the cores of nanowires 140 from the plurality of exposed portions 139 of the surface of the substrate 110 can occur, which fill each of the plurality of holes 138 arranged in a specific order and defined by a mask 135 for selective growth. A mask 135 for selective growth can serve as a form for selective growth, repeating in the form of a negative on a plurality of cores 140 of the nanostructure a nanoscale pattern of a plurality of holes 138 arranged in a specific order. In this way, the location and cross-sectional parameters of each of the many cores of the nanowires 140, for example, shape and size, can be set by the corresponding parameters of each hole from the set of holes 138 arranged in a specific order. For example, a plurality of holes 138 arranged in a specific order may include a hexagonal matrix of about 250 nm in size. The hexagonal matrix can then be transferred to the growth of multiple nuclei of 140 nanostructures with the same or smaller size, approximately 250 nm. In another example, if one or more holes of the plurality of holes 138 arranged in a particular order has an approximately circular shape with a diameter of about 100 nm, at least one core of the plurality of cores 140 of the nanostructure can be grown in circular holes and will have a diameter about 100 nm or less. Thus, the plurality of nuclei 140 of the nanostructure can be located in a strictly defined area and shaped in accordance with the plurality of holes 138 arranged in a specific order defined by the mask 135 for selective growth. In various embodiments, a plurality of nanostructure cores 140 may be formed by a standard MOCVD process.

Thus, the device 100 shown in FIG. 2 can be used as a carrier substrate for nanowires and / or matrices of nanowires, which may include a plurality of selected surface portions (i.e., a surface for each of the plurality of nanostructure cores 140). Then, a plurality of nanowires and / or matrices of nanowires can be grown on a plurality of isolated surface areas. In various embodiments, the selective growth mask 135 may be removed by a suitable etching process so as to open the plurality of nuclei 140 of the nanostructure after the formation of the plurality of nanowires.

FIG. 3 shows how a plurality of nanowires 145 can be formed by continuing to grow nuclei 140 of the nanostructure by, for example, stopping the selective growth mode and using the pulsed growth mode, before the plurality of nuclei 140 of the nanostructure begin to protrude above the upper surface of the mask 135 for selective growth . A plurality of nanowires 145 may be formed from the same material as the nuclei 140 of the nanostructure, for example, GaN, AlN, InN, InGaN, AlnGaN or AlGaN. In various embodiments, heterostructures can be formed on each of the plurality of nanowires 145. In various embodiments, n-type and / or p-type dopants can be incorporated into the plurality of nanowires 145, depending on the application.

By switching to a pulsed growth mode, before the plurality of nuclei 140 of the nanostructure begin to protrude from the upper surface of the mask 135 for selective growth, the parameters of each of the plurality of nanowires 145, for example, the cross-sectional shape and dimensions, can be saved until a predetermined value is reached length. In other words, the cross-sectional parameters of the nanowires 145, for example, the shape and / or dimensions, can remain substantially unchanged, the same or similar to the shape and size of the holes 138. In various embodiments, the length of each nanowire can be of the order of microns, for example, about 20 microns or more.

In various embodiments, an intermediate layer may be formed in nanowire devices. FIG. 4 shows a semiconductor device 200 based on a nanowire, used as a second embodiment, including an intermediate layer of the present invention. It is seen that the nanowire device 200 may include an intermediate layer 220 located between the substrate, for example, the substrate 110, and a mask for selective growth, for example, a mask 135 for selective growth (see FIGS. 1-3). In various embodiments, the intermediate layer 220 may be a planar semiconductor film formed from, for example, GaN, AlN, InN, InGaN, AlnGaN or AlGaN, for example, standard MOCVD technology. In various embodiments, the thickness of the intermediate layer 220 may be, for example, from 100 nm to 10 μm. In various embodiments, the intermediate layer 220 may be doped with either n-type or p-type additives to provide electrical connection to the lower end of each of the multiple nanowires 140. Various dopants known to those skilled in the art can be used.

In various embodiments, the orientation of the plurality of cores 140 of the nanostructure can be set in one direction, which, in turn, is achieved by the special orientation of the plurality of holes 138 arranged in a specific order along a single crystallographic axis. For example, a plurality of holes 138 arranged in a specific order may be specifically oriented along a single direction of the intermediate layer 220, as shown in FIG. 4. In the exemplary embodiment, during interferometric lithography marking, the holes in the mask 135 for selective growth can be specifically oriented along the direction <1100> of the GaN intermediate layer. In another embodiment, used as an example, in the process of growing an intermediate layer of GaN on a sapphire substrate, the axis c between the GaN intermediate layer and sapphire unit cells can be rotated 30 °.

FIG. 5 shows an exemplary process for forming a plurality of nanowires and / or matrices of nanowires using the two-stage growth mode of the present invention. In particular, FIG. 5 shows the dependences of the source gas stream (including the first gas stream curve 302 and the second gas stream curve 306) during selective growth 310 and subsequent pulse growth 320 to form, for example, a plurality of nanowires 145, as described in Figure 1-4. It is seen that selective cultivation 310 can be stopped by starting pulse cultivation 320 (i.e., switching from one growing mode to another) at the switching time t ₁ . Pulse growth 320 may further include a series of pulse sequences, for example, a first sequence cycle 324, a second sequence cycle 328, and / or additional sequence cycles. In various embodiments, the first sequence loop 324 may be repeated as the second sequence loop 328.

In the embodiment used as an example of the formation of nanowires and / or matrices of nanowires from GaN, the first gas flow dependence 302 can be constructed for the first group III feed gas, for example, tri-methyl gallium (TMGa), and the second gas flow dependence 306 can be built for a second gaseous starting material of group V, for example, ammonia (NH ₃ ). In selective growth 310, exemplary GaN nanowires and / or nanowire arrays can be formed in a MOCVD reactor, including using a first group III feed gas TMGa with a constant flow of about 10 standard cm ³ / min, and a second source group V NH gas ₃ with a constant flow of approximately 1,500 standard cm ³ / min. This means that in the process of selective growth of 310, the source gases (i.e., TMGa and NH ₃ ) can be supplied non-pulsedly, continuously (i.e., the source gases of both group III and group V are fed to the substrate simultaneously, in continuous, non-pulse mode). Moreover, the gaseous starting material of group III (for example, TMGa) and group V (for example, NH ₃ ) can be introduced simultaneously, and the ratio between the flow rates of gases of group V and group III can be maintained equal, for example, in the range of about 100 to 500. In the embodiment used as an example, the ratio of group V / group III can be maintained at about 150. In addition, other operating conditions of the selective growing reactor 310 may include, for example, an initial reaction temperature of about 1015 ° C. to 1060 ° C, d phenomenon in the reactor of about 100 mm Hg, and a hydrogen-nitrogen mixture carrier gas supplied laminar flow at a rate of 4000 standard cm ³ / min. Any suitable MOCVD reactor can be used, for example, a Veeco TurboDisk P75 MOCVD reactor model in which the substrates rotate at high speed during application.

In the process of pulse growing 320, the first group III feed gas, for example TMGa, and the second group V feed gas, for example NH ₃ , can be introduced alternately into the growth reactor in a predetermined sequence, for example, as the first cycle of 324 sequences shown. In various embodiments, the growth of nanowires and / or matrices of nanowires may depend on the duration of each alternating step within the pulse sequence, which can be further optimized for a particular reactor geometry. For example, in the first cycle of 324 pulse sequences, TMGa can be injected at a rate of about 10 standard cm ³ / min for a certain time, for example, about 20 seconds (not shown), followed by, for example, a 10-second carrier gas purge (for example, with a mixture of hydrogen with nitrogen), during which no feed of gas occurs, after which NH ₃ is introduced with a flow rate of about 1500 standard cm ³ / min for, for example, about 30 seconds (not shown), then, for example, 10 second carrier gas purge (e.g. imer, a mixture of hydrogen with nitrogen) with the cessation of the supply of source gases. Also, depending on the characteristics of the reactor, other pulse durations can be used, for example, 15-40 seconds for reagents of group III, 15-40 seconds for reagents of group V and 5-15 seconds to supply purge gases between each step of the introduction of reagents. In various embodiments, the pulse sequences, for example, the first sequence cycle 324, may be repeated until a specific length of GaN nanowires is reached. For example, a sequence loop 324 may be repeated as a second sequence loop 328, a third sequence loop (not shown), etc. In each cycle of the sequences, the starting gases of group III (for example, TMGa) and the starting gases of group V (for example, NH ₃ ) can have an effective V / III ratio in the range of, for example, from 60 to 300. In various embodiments, such mode parameters how the temperature, pressure in the reactor and the carrier gas stream for pulsed growth 320 may remain the same as selective growth 310. It will be understood by those skilled in the art that the indicated growth parameters are provided for illustration and may vary I depending on the particular reactor used.

In various embodiments, the switching time (t ₁ ) may be determined by the duration of selective cultivation 310. The switching time (t ₁ ) may depend on the growth rate inside each hole, for example, each of the plurality of holes 138 arranged in a specific order shown in FIG. 1 -four. The growth rate inside each hole may, in turn, depend on gas flows (for example, as shown by gas flow diagrams 302 and 304) of each feed gas and the geometry of each hole from a plurality of holes 138 arranged in a specific order. Depending on the geometry, the reagents necessary for growth, for example, those formed from TMGa and / or NH ₃ , can be deposited both on the mask for selective growth and in open holes. During selective growth 310, the reagent deposited on the selective growth mask can have high surface mobility and can either leave the surface of the mask or, with sufficient proximity to the open hole, diffuse to this hole and increase the growth rate in this hole. This addition to the growth rate can thus be highly dependent on the size of the hole and the distance between the holes. In the embodiment shown as an example of the formation of a plurality of GaN nanowires and / or matrices of nanowires, switching of the growth mode can occur after 1 minute of selective growth (i.e., t ₁ = 1 min), which can be experimentally determined by the growth rate of GaN inside holes arranged in a specific order. For example, a GaN growth rate may be about 0.6 μm / h, and holes arranged in a specific order having a diameter of about 200 nm and a pitch of about 1 μm can form a hexagonal matrix.

In various embodiments, the growth of a plurality of nanowires and / or matrices of nanowires can be influenced by when exactly the switching of the growth mode occurs. For example, the growth mode switch may be performed after a plurality of growing nuclei 140 of nanostructures begin to protrude above the mask for selective growth (for example, mask 135 shown in FIGS. 1-4). In various embodiments, different configurations / sizes can be obtained on nanowires and / or matrices of nanowires, depending on whether the growth mode is switched “before” before (for example, as shown in FIGS. 1-4) or “after” as the nanowire cores grew so much that they began to protrude above the mask for selective growth.

Figures 6-8 show a third nanowire-based semiconductor device 400 used to illustrate the invention, formed by switching the growth mode "after" after the cores have grown so much that they begin to protrude above the mask for selective growth. It will be apparent to one skilled in the art that the nanowire device 400 shown in FIGS. 6-8 is a generalized schematic illustration, and that other layers / nanowires can be added, or existing layers / nanowires can be removed or modified.

The device 400 shown in FIG. 6 can include a structure and can be formed by a process that is similar to those presented in FIG. 3 for the device 100. It can be seen that the device 400 can include a substrate 410, a mask 435 for selective growth and many cores 440 nanostructures. A selective growth mask 435 and a plurality of nanostructure cores 440 may be formed on the substrate 410, and a plurality of nanostructure cores 440 may be distributed over and pass through the selective growth mask 435.

As the substrate 410, any substrate similar to the substrate 110 of the device 100 can be used on which material of group III-N can be grown. For the substrate 410, for example, sapphire, silicon carbide or silicon can be used. Similarly, a plurality of cores 440 of a nanostructure can be formed by analogy with how a plurality of cores 140 of a nanostructure of the apparatus 100 shown in FIG. 2 were formed. For example, a plurality of nanostructure cores 440 can be formed during a process where a plurality of holes are first formed, arranged in a specific order (not shown) defined above the substrate 410 by a selective growth mask 435. Each of the plurality of holes arranged in a specific order can then be filled by growing a semiconductor material (e.g., GaN) therein, for example, using standard MOCVD technology. A plurality of nanostructure cores 440 may have a thickness equal to the thickness of a selective growth mask 435, for example, about 30 nm, and a cross-sectional size, for example, a thickness or diameter, of about 10 nm to 200 nm. As an additional example, dimensions in cross section from about 10 nm to 100 nm can be given.

The device 400 shown in FIG. 7 may include a plurality of nanostructures 442 grown both in the transverse direction and vertically from the nuclei 440 of the nanostructure, and the growth mode was switched “after” after the plurality of nuclei 440 of the nanostructure extended beyond the upper surface of the mask 435 for selective cultivation. For example, each of the plurality of nanostructures 442 can grow in the transverse direction, expanding to the sides and, in part, along the surface of the mask 435 for selective growth. In various embodiments, the plurality of nanostructures 442 may include pyramidal structures containing an upper crystal face. For example, a plurality of pyramidal GaN nanostructures can include an upper face (0001), and the size of this upper face can be controlled by changing the duration of growth of each nanostructure. In particular, at an early stage of growth, when many nanostructures 442 grow in the transverse direction and, partially, on the surface of the selective growth mask 435, the sizes of the upper face can be increased and its size can be larger than the cross-sectional sizes of many nuclei 440 of the nanostructure. With continued growth, the dimensions of the upper face can decrease so that the extreme upper size of the face can be smaller than the size of the plurality of nuclei 440 of the nanostructure. Therefore, the sizes of the upper faces of each pyramid can be controlled, for example, by stopping the selective growth mode (i.e., by switching the growing mode) to stop the growth of many pyramidal nanostructures. In various embodiments, the upper faces of the pyramidal nanostructures used as an example can be truncated, and the size of each truncated upper face can then be saved for subsequent growth of nanowires and / or matrices of nanowires using a pulsed growth mode. In various embodiments, the diameter of the truncated upper face of each of the plurality of nanostructures 442 can be made smaller than the diameter of each of the plurality of cores 440 of the nanostructures. In various embodiments used as an example, the upper face of each of the plurality of nanostructures 442 may have a cross section, for example, square, polygonal, rectangular, oval and round.

The device 400 shown in FIG. 7 can be used as a carrier substrate for nanowires and / or matrices of nanowires, which may also include a plurality of selected surface portions (i.e., the surface of each upper face of the plurality of nanostructures 442). Then, a plurality of nanowires and / or matrices of nanowires can be grown from the plurality of selected surface areas while maintaining the cross-sectional properties (for example, sizes and shapes) of each of the plurality of selected surface areas.

FIG. 8 shows how a plurality of nanowires 445 can be formed by continuing to grow a semiconductor material (eg, GaN) from a plurality of selected surface portions of the device 400 (i.e., from each upper face of the plurality of nanostructures 442) using a pulsed growth mode. As a result, many nanowires can be arranged at predetermined intervals, and their diameter, for example, can be from about 20 to 500 nm, and the cross section can be, for example, square, polygonal, rectangular, oval and round.

By using the pulsed “after” growth mode, when, as a result of the growth of the semiconductor material, he began to protrude above the mask 435 for selective growth, many nanowires 445 can be formed on the upper faces of the pyramidal structures of the many nanostructures 442, given as an example. Properties of each of multiple nanowires 445, for example, cross-sectional shape and dimensions, can remain the same as the truncated upper faces until the desired length is reached. In various embodiments, the implementation of the length of each nanowire can be formed on the order of micrometers, for example, approximately 20 microns or more.

Figure 9 shows another, by way of example, a semiconductor device 500 based on nanowires, in which an intermediate layer is used, in accordance with the present invention. It is shown that the device 500 based on nanowires may include an intermediate layer 520 located between the substrate, for example, the substrate 410, and a mask for selective growth, for example, a mask 435 for selective growth. The intermediate layer 520 may be similar to the intermediate layer 220 shown in FIG. The intermediate layer may be a planar film formed from GaN, AlN, InN or AlGaN using, for example, standard MOCVD technology. In various embodiments, the thickness of the intermediate layer 520 may be from about 10 nm to 10 microns. In various embodiments, the intermediate layer 520 can be doped with either an n-type additive or a p-type additive to provide electrical contact with the lower end of each nanowire.

Figure 10 (AD) shows examples of ordered nanowires and / or matrices of nanowires grown through multi-stage growth conditions without using a catalyst in accordance with the present invention (both the nuclei 140, 440 of the nanostructure and the nanowires 145, 445 are grown without using a metal catalyst applied to the substrate). As shown in FIG. 10 (A-D), a plurality of GaN 610 nanowires can be grown with large-scale uniformity in terms of location, orientation, length, cross-sectional parameters (e.g., size and / or shape) and crystalline properties. According to the present description, in some embodiments, the location and dimensions of each nanowire may correspond to the location and dimensions of each hole of the plurality of holes 138 arranged in a specific order shown in FIGS. 1-4. In other embodiments, the location and size of each nanowire may correspond to the location and size of each upper face of the plurality of nanostructures 442 shown in FIGS. 6-9.

Figure 10 (A) presents a large-scale scanning electron micrograph (SEM - from the English. Scanning electron micrograph) obtained for the GaN nanowires 610 used as an example, and Figure 10 (B) presents SEM obtained for the long-range order GaN nanowires 610. In various embodiments, each GaN nanowire may have a nanocrystal structure.

Figure 10 (C) shows that GaN nanowires 610 can be oriented along a single crystallographic direction, for example, crystallographic direction (0001) of GaN nanowires 610, used as an example. In addition, the small central upper face of each nanowire with the (0001) direction can border on the inclined faces {1102} in the upper part of each nanowire.

10 (D) is a top view of GaN nanowires 610 used as an example, showing hexagonal symmetry of the side faces of each GaN nanowires. Lateral faces having crystallographic directions of the {1100} family may be perpendicular to the orientation of the selective growth mask 620. In various embodiments, the diameter of the GaN nanowires 610 used as an example may be about 1000 nm or less.

The invariable geometry of the nanowire in the transverse direction (for example, cross-sectional parameters), illustrated in FIG. 10 (AD), indicates that the growth rate of GaN can be non-zero only in the vertical direction, that is, on the upper faces with crystallographic directions (0001) and {1102}. For example, the vertical growth rate of a plurality of GaN nanowires 610 in a pulsed growth mode may be, for example, about 2 μm / h or more. On the other hand, the growth rate of GaN on lateral faces (ie, in transverse directions) having a crystallographic direction of {1100} can be essentially negligible, despite their significantly large area. In an exemplary embodiment, the GaN nanowires 610 can be grown of the same length of about 20 microns or more, keeping the diameter of about 250 nm or less unchanged using a 30 nm selective growth mask. In various embodiments, the presence of hydrogen in the carrier gas mixture can control the geometry of the nanowire.

In addition, the exemplary homogeneous GaN nanowires 610 shown in FIG. 10 (A-D) can be of high quality, that is, substantially without piercing dislocations (TD - from English threading dislocations). For example, piercing dislocations may not be observed in the GaN nanowires 145 and / or 445 shown in FIGS. 4 and 9, even if piercing dislocations are present in the intermediate GaN layer 220 and / or 520 under mask 135 and / or 435 for selective growth, since it is believed that these dislocations deviate from the nanowires and end on the surface under the mask for growth. Moreover, GaN-free nanowires 610 can be grown on various substrates, for example, a sapphire, silicon carbide, for example 6H-SiC, or silicon, for example, Si (111) face.

In various embodiments, uniform and high quality GaN nanowires and / or nanowire arrays can be used to fabricate high quality GaN substrate structures. It is desirable to have commercially viable GaN substrates, since the use of such substrates can greatly simplify the manufacture of visible light emitting diodes and lasers for developing solid-state source technologies for lighting and UV sensitive elements. Moreover, GaN substrates can also be used in related fields, such as radio frequency circuits and high power devices.

In various embodiments, GaN substrate structures can be formed by stopping the growth and splicing of a plurality of GaN nanowires, such as those shown in FIGS. 1-10, using, for example, nanoheteroepitaxy technology. 11-14, four semiconductor devices are used as an example, including structures of 712, 714, 715 and 717 GaN substrates formed from a plurality of GaN nanowires of the device 100 (see FIG. 3), the device 200 (see FIG. .4), devices 400 (see Fig. 8), and devices 500 (see Fig. 9), respectively.

For example, the conditions for growing GaN can be changed so as to ensure that the formed set of nanowires (for example, 145 or 445) is fused after they have grown to a suitable height, and then the structure (for example, 712, 714, 715 or 717) of the GaN substrate is formed . The structure of the GaN substrate can be a continuous, epitaxial and fully fused planar film. An “appropriate height” can be determined for each combination of a nanowire (eg, GaN) and a substrate (eg, SiC or Si), and can be a height at which a significant reduction in defect density in the upper fused GaN film (i.e., structure GaN substrate). In addition, a “suitable height” may be a height at which a mechanically rigid structure is provided for the resulting semiconductor devices, such as those shown in FIGS. 11-14. In various embodiments, due to the absence of penetrating defects in a plurality of GaN nanowires (e.g., 145 or 445), a GaN structure of a substrate (e.g., a substrate 712, 714, 715 or 717) may coalesce over this multiple nanowires to form a GaN structure having exclusively low defect density, for example, approximately 107 / cm ² or lower.

In accordance with various embodiments of a method for manufacturing a nanowire, the steps of the method (e.g., coating, patterning, and etching a mask for selective growth, selective growth of nanowire cores, pulsed growth of nanowires, and formation of GaN substrate structures described by way of example) can be scaled to use on substrates of a large area. They can also be successfully adapted to the requirements of production, including the automation of the processes for manufacturing the substrates of semiconductor devices, and extended to large plates to achieve high efficiency crystals for photoelectronics used to emit light in visible and near ultraviolet LEDs.

15-21, as an embodiment, examples of active devices based on nanowires, including LEDs based on nanowires and lasers based on nanowires, and examples of scalable manufacturing processes of such devices are presented. In various embodiments, the described nanowires and matrices of group III-N nanowires, for example, GaN nanowires and / or nanowire matrices, can provide unique properties to active devices based on them. This is achieved due to the fact that each GaN nanowire grown in a pulsed mode can have side walls in the form of faces of the {1100} family and the normal to each of these side surfaces can represent a non-polar direction for materials of group III-N. Therefore, on such lateral faces of each GaN nanowires, high-quality III-N quantum wells can be formed, for example, InGaN / GaN quantum wells, AlGaN / GaN quantum wells or other quantum wells of III-N materials.

For example, the nanowire growth parameters can be substantially changed when another source gas is added to the gas phase of the MOCVD process during the example pulsed growth regime, for example, trimethylaluminium (source Al) or trimethylindium (source In). In this case, even a large molecular fraction (for example, about 1%) of aluminum or indium added to GaN nanowires and / or matrices of nanowires can lead to the growth of each GaN nanowires in the transverse direction, with a constant increase in its cross section (for example, the width or diameter). This transverse growth property makes it possible to create “core-shell” heterostructures, that is, enveloping quantum wells can be grown on the GaN core of the nanowire, including example materials, for example, InGaN and AlGaN alloys. As a result of growing shells around the core, an active structure based on a core-shell / MGW nanowire can be created for light-emitting devices.

In various embodiments, an additional third growth condition can be created for growing the core-shell structure of exemplary InGaN and AlGaN alloys after a GaN nanowire has been grown using the disclosed two-stage growth mode. This third growing mode may be a continuous growing mode similar to that used in the selective growing mode, for example, step 310 in FIG. 5. In various other embodiments, a pulsed growth regime can be used for the third growth condition.

In various embodiments, an active core-sheath / MQW nanowire structure can be used to create highly efficient nanoscale optoelectronic devices, for example, nanowire LEDs and / or nanowire lasers. For example, the resulting active structure with a core-sheath / MQW nanowire (for example, having an MQW active sheath on the side walls of the core of each nanowire) may be free of piezoelectric fields and also not have the quantum confinement effect related to it (QCSE - from the English quantum-confined stark effect), since the core of each nanowire has non-polar side walls. Eliminating QCSE can increase the quantum efficiency of radiation in the active region, which improves the performance of LEDs and lasers. In addition, in the absence of QCSE, quantum wells of a larger width can be used, due to which the overlap integral and the gain of the resonator of nanowire lasers can be improved. An additional advantage with respect to the efficiency of using active structures with a core-shell nanowire / MQW is that the area of the active region can be significantly increased due to the unique core-shell structure.

15 is a cross-sectional view of a layered structure of an exemplary apparatus 800 with an active core-sheath / MQW nanowire structure of the present invention. It should be apparent to one skilled in the art that the device 800 shown in FIG. 15 is a generalized schematic illustration, and that other materials / layers / shells may be added, or existing materials / layers / shells may be removed or modified.

It is shown that device 800 can include a substrate 810, a doped intermediate layer 820, a selective growth mask 825, a doped nanowire core 830, and a sheath structure 835 including a first doped sheath 840, an MQW sheath 850, a second doped sheath 860, and a third doped sheath 870.

A selective growth mask 825 may be formed on top of the intermediate layer 820 located on the substrate 810. The doped nanowire core 830 can be connected to and grow from the doped intermediate layer through the selective growth mask 825, while the doped nanowire core 830 can be isolated by the 825 mask for selective cultivation. The sheath structure 835 may be formed to surround the doped nanowire core 830 with a sheath while having an active core-sheath structure, and the sheath structure 835 may also be located on the selective growth mask 825. In addition, the shell structure 835 may be formed by depositing a third alloy shell 870 on top of the second alloy shell 860, which may be formed over the MQW of the shell structure 850 over the first alloy shell 840.

Structure 810 may be a substrate similar to substrates 110 and 410 (see FIGS. 1-4 and FIGS. 6-9), including sapphire, silicon carbide, silicon, and substrates of materials of groups III-V, for example, GaAs or GaN.

A doped intermediate layer 820 may be formed on top of the substrate 810. The doped intermediate layer may be similar to the intermediate layers 220 and / or 520 (see FIG. 4 and FIG. 9). The doped intermediate layer 820 can be formed from, for example, GaN, AlN, InN, AlGaN, InGaN or AlnGaN by various crystal growth methods known to those skilled in the art. In various embodiments, the conductivity of the same type as the conductivity of the core 830 of the nanowire can be imparted to the intermediate layer 820 by doping. In some embodiments, implementation, the doped intermediate layer 820 may be excluded from the device 800.

As a mask 825 for selective cultivation, a mask for selective cultivation can be used, similar to masks 135 and / or 435 for selective cultivation (see Figs. 1-4 and Figs. 6-9) formed on an intermediate layer 820. In various embodiments, the implementation a selective growth mask 825 can be formed directly on the substrate 810. Selective growth of a plurality of nanowires and / or nanowire arrays can be determined by a selective growth mask 825. The selective growing mask 825 may be formed from any dielectric material or other growing mask material known to those skilled in the art.

As the doped core 830 of the nanowire, any nanowire of the plurality of nanowires shown in FIGS. 1-4 and 6-14 formed using a two-stage growth mode can be used. The doped core 830 can be formed from, for example, GaN, AlN, InN, AlGaN, InGaN or AlnGaN, which can be made with n-type conductivity by doping with various impurities, for example, silicon, germanium, selenium, sulfur and tellurium. In various embodiments, the doped 830 nanowire core can be made with p-type conductivity by incorporating beryllium, strontium, barium, zinc or magnesium. Other dopants known to those skilled in the art may be used. In various embodiments, the height of the doped nanowire core 830 may be approximately determined by the height of the active structure device 800. For example, the doped core 830 of a nanowire may have a height of about 1 μm to 1000 μm.

The doped nanowire core 830 may have non-polar faces of the {1100} family side walls (that is, the m-plane faces) if GaN material is used to dope the nanowire core 830. The shell structure 835, including the MQW shell structure 850, can be obtained by growing on these faces of the core-shell structure, and therefore, piezoelectric fields and the related QCSE Stark Effect (QCSE) may not be present in device 800.

The first doped sheath 840 can be formed from the non-polar faces of the side walls of the doped core 830 of the nanowire and applied to them by growing an example of a core-sheath structure using a pulsed growth mode. For example, the first doped sheath 840 can be formed by adding a small amount of A1 during the pulsed growth of the doped core 830 of the nanowire, resulting in the formation of a core-shell heterostructure. The conductivity type of the first doped sheath 840 and the doped core 830 of the nanowire can be made the same, for example, n-type. In various embodiments, the first alloy shell 840 may include Al _x Ga _1-x N material, where x may be any number less than 1, for example, 0.05 or 0.10.

An MQW shell structure 850 may be formed on the first doped shell 840 by growing a core-shell structure using a pulsed growth regime. In particular, the MQW shell structure 850 can be formed by adding a small amount of Al or In during the pulsed growth of the first doped shell 840 to continue the formation of a core-shell heterostructure. In various MQW embodiments, the shell structure 850 may include, for example, alternating Al _x Ga _1-x N and GaN layers, where x may, for example, be 0.05 or any other number less than 1.00. The MQW shell structure 850 may also include alternating layers, for example, In _x Ga _1-x N and GaN, where x may be any number less than 1.00, for example, any number in the range of about 0.20 to 0.45 .

A second alloy shell 860 may be formed on the MQW shell structure 850. The second doped cladding 860 can be used as the depletion layer for the MQW structure 850 cladding with a sufficient thickness, comprising, for example, from about 500 nm to 2000 nm. The second alloy shell 860 may be formed from, for example, Al _x Ga _1-x N, where x may be any number less than 1.00, for example, 0.20 or 0.30. The second doped sheath 860 may be doped so that the resulting conductivity type matches the conductivity type of the third doped sheath 870.

The third alloy shell 870 may be formed by continuing to grow the core-shell structure from the second alloy shell 860 so as to close the active structure device 800. The third doped sheath 870 can be formed, for example, from GaN and doped to obtain n-type or p-type conductivity. In various embodiments, if the first doped sheath 830 is an n-type conductivity sheath, then the second doped sheath 860 and / or the third doped sheath 870 may be p-type sheaths, and vice versa. In various embodiments, the third doped sheath 870 may have a thickness of from about 50 to 500 nm.

In various embodiments, shown in FIG. 15, devices 800 on an active core-shell structure may be electrically isolated from each other if multiple devices 800 are located on a large area, such as a semiconductor wafer. FIG. 16 shows an active structure device 900 including a dielectric material 910 disposed to insulate each core-sheath / MQW active structure shown in FIG. 15 according to the present invention.

As shown in FIG. 16, a dielectric material 910 can be applied to a mask for selective growth and connected at the edges with the side walls of the sheath structure 835, in particular with the side walls of the third doped sheath 870. In various embodiments, the dielectric material 910 can be any dielectric material providing electrical insulation, for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON) or other insulating material. In some embodiments, the dielectric material 910 may be a curable dielectric. The dielectric material can be applied, for example, by chemical vapor deposition (CVD - from the English chemical vapor deposition) or by centrifugation, until the desired height or thickness is achieved. In various embodiments, the height / thickness of the dielectric material 910 can be further adjusted by removing part of the dielectric material from the upper surface of the deposited dielectric material, using, for example, etching or reverse lithography techniques known to those skilled in the art. The thickness of the dielectric material 910 can be adapted to the specific requirements of a device that uses an active structure with a core-sheath / MQW nanowire.

In various embodiments, various nanowire LEDs and lasers can be fabricated with growing the core-sheath structure illustrated in Figs. . For example, if the nanowires are arranged in a hexagonal matrix with a step equal to λ / 2, where λ is the radiation wavelength of an LED or laser used as an example, the matrix of nanowires can create optical feedback to stimulate light emission. On Fig-21 presents used as an example nanoscale active devices formed on the basis of the structures shown in Fig-16, in accordance with the present invention.

17-19 depict exemplary nanowire LED devices 1000 using an active core-sheath / MQW nanowire structure depicted in FIGS. 15-16, in accordance with the present disclosure.

In various embodiments, a nanowire LED device 1000 can be made by adding electrical contacts, for example to device 900. Electrical contacts can include conductive structures formed from metals, such as titanium (Ti), aluminum (Al), platinum (Pt ), nickel (Ni) or gold (Au), in various multilayer combinations, for example, Al / Ti / Pt / Au, Ni / Au, Ti / Al, Ti / Au, Ti / Al / Ti / Au, Ti / Al / Au, Al or Au using techniques known to those skilled in the art.

As shown in FIG. 17, device 1000 may include a conductive structure 1040 formed on the surface of device 900, i.e. on each surface of the material 910 and the third alloy shell 870 of the shell structure 835. The conductive structure 1040 may be a transparent layer used as the p-type electrode of the LED device 1000 to be manufactured. In the exemplary embodiment, the conductive structure 1040 (or p-type electrode) may be a metal combination of Ti / Au metals.

In various embodiments, device 1000 may further include a dielectric layer 1010 whose thickness (or height) is selected. By selecting the thickness of the dielectric layer 1010, the length (for example, thickness or height) of the conductive structure 1040 (p-type electrode) formed on the side wall of the sheath structure 835 and along it, in accordance with the requirements for use in an active device based on nanowires, can also be controlled. For example, a thick dielectric layer 1010 may limit the placement of the conductive structure 1040 (or p-type electrode) to the top of active core-clad devices, for example, for nanowire LEDs and / or nanowire lasers. In contrast, reducing the thickness of the dielectric layer 1010 allows the conductive structure 1040 (or p-type electrode) to be thicker or taller (i.e., larger) to reduce the electrical resistance of the active devices. In various embodiments, the large thickness of the conductive structure 1040 (or p-type electrode) may, however, increase the loss of an active device, such as a laser resonator. The specialist should be clear that the optimal operating parameters of the conductive structure 1040 (or p-type electrode) are obtained as a result of a compromise between a decrease in the resistance of active devices and an increase in resonator losses.

In various embodiments, the thickness of the conductive structure 1040 (or p-type electrode) along the side walls of the shell structure 835 of the exemplary LED device 1000 may be in the range of about 1 μm to about 9 μm to provide high performance. In various embodiments, the LED device 1000 may have a full height, for example, about 10 microns.

The device 1000 shown in FIG. 18 may further include a p-type electrode 1045, a dielectric 1015, and a selective contact mask 1025 having grooves 1035 etched in the selective growth mask 825 (see FIG. 17).

The p-type electrode 1045 and the dielectric 1015 below it can be formed by drawing a pattern on the conductive structure 1040 and the dielectric layer 1010, and etching them (see FIG. 17). As a result, portions (not shown) of the surface of the selective growth mask 825 can be exposed and separated by a dielectric 1015 on both sides of each core-shell structure. After drawing and etching, a mask 1025 for selective contact can be formed by creating grooves 1035 on the exposed areas of the surface of the mask 825 for selective growth, with at least one groove 1035 on each side of the active core-shell structure. As a result, the sections the surface of the underlying intermediate layer 820 can be used as the bottom of the grooves 1035.

In various embodiments, the thickness of the selective contact mask 1025 may be critical in terms of the functioning of the LED device 1000. For example, a silicon nitride selective growth mask having a thickness of 30 nm may be thick enough to withstand voltages of about 20 V or higher to breakdown of the LED device 1000. In various embodiments, the selective contact mask 1025 may have a thickness of about 30 nm or less. The specialist, however, should be clear that in the technology of manufacturing nanowires and active devices based on nanowires, a thicker mask for selective growth may well be used.

As shown in FIG. 19, device 1000 may include n-type electrodes 1080 formed to provide a connection between the electron side contact and the central conductive region, including the doped intermediate layer 820 and the nanowire core 830. The central conducting region may be, for example, a heavily doped n ⁺ GaN region. In various embodiments, n-type electrodes 1080 may include conductive structures formed by depositing electrode materials on each surface of the mask 1025 for selective contact and the bottom of the grooves 1035. In an exemplary embodiment, n-type electrodes 1080 may be formed, for example , from a multilayer metal composition, for example, Al / Ti / Pt / Au.

As shown in FIG. 19, generated light 1099 can be output from the nanowire LED device 1000 through the substrate 820, which can be transparent to the wavelengths of the green and blue portions of the spectrum. In various embodiments, more scattered radiation may occur from the upper side of the device 1000 (not shown), since the nanowire LED device is small enough to exhibit diffraction. This diffuse radiation may be useful for solid state lighting applications.

Thus, the disclosed nanowire-based LED device 1000 may have unique properties compared to conventional LED devices. Firstly, it can have a higher brightness due to the fact that the area of the active region of the grown core-shell structure (i.e., the area of the active MQW shell) can be increased by about 10 times compared to conventional planar LED structures. Secondly, light output can be improved, which increases the output efficiency of the LED. This is due to the geometry of the LED device, which makes maximum use of the area of the active region, oriented normal to the surface of the semiconductor wafer, that is, to the surface of the substrate. Closed areas on the sides of the active MQW area help guide the LED radiation in the vertical direction. Thirdly, due to the high accuracy of the location and size of each of the many nanowires and / or matrices of nanowires, photonic crystals can be formed from the resulting matrices of LED devices 1000 in which the power take-off efficiency can be further increased. Fourth, the electrical resistance of a nanowire-based LED can be significantly reduced by increasing the area of electrical contact, for example, the contact area of a p-type electrode 1045. Finally, since the LED device 1000 can provide a certain luminous power with a higher brightness, more devices can be located on a certain semiconductor wafer, which will reduce the cost of production and increase its profitability. For example, to accommodate metal contacts, the LED devices 1000 may be spaced (i.e., the distance between two adjacent nanowire devices) of, for example, approximately 100 μm. A 4-inch wafer may result in approximately 0.78 million or more nanowire LED devices 1000 that will be fabricated simultaneously. In various embodiments, the placement step can be further reduced so that, for example, more than a million LED devices 1000 can accommodate on a 4-inch blank plate.

FIGS. 20-21 show exemplary nanowire-based laser devices using an active core-sheath / MQW nanowire structure shown in FIGS. 15-19, in accordance with the present disclosure. Since the faces of the side walls of nanowires and / or matrices of nanowires are exact {1100} faces whose planarity is determined by the thickness of the atomic layer, high-quality active MQW regions for laser devices can be formed on the surface of these superplane “side wall substrates”. In addition, the vertical orientation of the side faces and the strict periodicity of the arrangement and the uniformity of the length of the nanowires can provide a high-performance method of etching or cleaving faces to form an optical resonator. Strict periodicity can directly provide the creation of an optical resonator of a photonic crystal.

As shown in FIG. 20, a nanowire laser device 1100 can be manufactured using the processes described in FIGS. 15-19 by growing an active structure with a core-sheath / MQW nanowire as an active laser structure. The nanowire laser device 1100 may include a polished sheath structure 1135, a polished p-type electrode 1145, and a passivation layer 1195 that can be formed on each surface of the polished sheath structure 1135 and the polished p-type electrode 1145, covering the active laser structure.

A polished sheath structure 1135 and a polished p-type electrode 1145 can be formed by polishing (i.e. stripping the material) the upper end (with respect to the substrate 810 as the lower end) of the core-sheath / MQW active nanowire (i.e. active laser structure), for example, shown in Fig.19. Various polishing technologies can be used, for example, chemical-mechanical polishing, while the etched dielectric 1015 acts as a mechanical support.

The polishing step can be used to polish several faces of the laser without reducing, while the manufacturability of laser devices 1100 based on nanowires. For example, a number of nanowire-based laser devices 1100, such as 0.78 million or more, can be formed on a 4-inch semiconductor wafer to provide high processability. In various embodiments, the placement step can be further reduced in order to accommodate, for example, more than one million laser devices on a 4-inch plate.

In various embodiments, the extent (eg, thickness or height) of the p-type polished electrode 1145 formed along the side walls of the polished sheath structure 1135 can be adjusted by adjusting the thickness of the etched underlying dielectric 1015 to obtain optimal performance of the laser device 1100. In various embodiments the implementation of the thickness of the polished p-type electrode 1145 along the side wall of the polished shell structure 1135 shown in FIG. 20 may be an example in the range from about 1 micron to about 5 microns, wherein the total height is about 10 microns.

A passivation layer 1195 can be formed at the upper polished end of the active structure of each laser, i.e. on each surface of a polished p-type electrode 1145 and a polished sheath structure 1135. The configuration of the passivating layer can be chosen so that no harmful non-radiation recombination or leakage occurs through the transition in the nanowire laser device 1100. In various embodiments, the passivation layer can be made of, for example, any dielectric material known in the art, with a thickness of from about 10 to 100 nm.

In some embodiments, the composition and refractive index of the materials used for the polished sheath structure 1135 surrounding the resonator in the nanowire (i.e., the nanowire core 830) can affect the process of generating optical radiation 1199. For example, when the diameter of the nanowires given as an example, is approximately 200 nm; a portion of the generated optical wave may exist outside the cavity. Therefore, the laser may be more sensitive to the composition and refractive index of the materials surrounding the cavity, that is, the materials used for each layer of the polished shell structure 1135.

In other embodiments, since the bottom face is physically absent on the laser optical resonator (i.e., the nanowire core 830), there may be a change in the effective refractive index in the region of the selective growth mask 1025. This change in the refractive index can actually be ensured (i.e., increased) due to the fact that part of the generated optical wave can exist outside the cavity. In an exemplary embodiment, the optical tuning of a nanowire laser device 1100 (see FIG. 20) can be performed by adjusting the thickness of the mask 1025 for selective contact to obtain maximum reflection. For example, the optical thickness of the selective contact mask 1025 in the laser device 1100 may be from about 220 nm to 230 nm if the device emits blue light at a wavelength of 450 nm.

On Fig shows another laser device 1200, used as an example, in which between the layers of the substrate 810 and mask 1025 for selective growth is a mirrored foot 1220 Bragg reflectors (DBR - from the English distributed Bragg reflector) instead of the doped intermediate layer 820 located between the two layers of the laser device 1100 shown in FIG.

Mirrored foot 1220 DBR mirrors may represent an epitaxial DBR mirrored foot. The DBR mirror foot 1220 may include, for example, alternating quarter-wave layers of, for example, GaN and AlGaN. In various embodiments, the implementation of the DBR mirror foot 1220 can be configured to improve reflection and increase the quality factor of the laser cavity 1299.

In various embodiments, all active nanowire devices shown in FIGS. 19-21 may have a low resistance, since more p-type electrodes (e.g., 1045 and / or 1145 p- electrodes can be located over a larger area) type) heterostructures, since this is the area of the outer periphery of each active structure with a core-shell nanowire / MQW. For example, for the LED device 1000 (shown in FIG. 19), the configuration of the p-type electrode 1045 may be such that it completely covers the upper part of the device 1000, which will further reduce the resistance of the device.

Although a single nanowire has been shown in Figs. .1-10) for nanoscale active devices can be implemented simultaneously over a large area (for example, a whole semiconductor wafer blank).

For specialists who have become acquainted with the description and method of carrying out the invention proposed herein, other advantages of the present invention will be apparent. It is believed that the description and examples of implementation are given for illustration only, and the true scope of the claims and the essence of the invention are determined by the following claims.

Claims (25)

1. A method of manufacturing nanowires, comprising the step of forming a mask for selective growth on a substrate,
containing a group of holes arranged in a certain order and opening a group of sections of the substrate,
the stage of selective non-pulse growth, in which at each of these sites through these holes grow nuclei of nanowires using the growing mode, including
the simultaneous supply of the source of gaseous substances forming the core of the nanowires, in the reactor for growing crystals (non-pulse mode),
a switching stage in which, after the formation of the cores of the nanowires with the specified characteristics, the growth mode is switched from the non-pulsed mode to the mode in which the initial gaseous substances forming the filamentous part of the nanowires are alternately fed into the crystal growing reactor (pulsed mode), and
the stage of pulsed growth, in which they continue to grow the filamentary parts of the nanowires in a pulsed mode with the formation of many semiconductor nanowires. 2. The method according to claim 1, in which the substrate includes an intermediate layer over the bearing surface of the substrate, and the cores of nanowires are selectively grown on the intermediate layer through a group of holes arranged in a specific order. 3. The method according to claim 1 or 2, in which the composition of the substrate include at least one material selected from the group comprising Si, SiC, sapphire, GaN and GaAs. 4. The method according to claim 1 or 2, in which at least one purification process is additionally carried out before the selective non-pulse growing stage. 5. The method according to claim 1 or 2, in which the specific order of the group of holes is a hexagonal matrix, wherein the diameter of the holes is from about 10 nm to 1000 nm and the pitch of the holes is from about 50 nm to 10 μm. 6. The method according to claim 1 or 2, in which the cross-sections of each semiconductor nanowire from the group of semiconductor nanowires and each hole from the group of holes arranged in a certain order essentially coincide. 7. The method according to claim 6, in which the cross-sectional shape is selected from the group comprising a polygon, rectangle, square, oval and circle. 8. The method according to claim 6, in which the switching of the growing mode from non-pulsed to pulsed is carried out before the release of the core of the nanowire over the mask for selective growth. 9. The method according to claim 1 or 2, in which at least one material selected from the group comprising GaN, AlN, InN, InGaN, AlInGaN and AlGaN is used as a semiconductor material. 10. The method according to claim 1 or 2, in which at the stage of selective cultivation the introduction of gaseous starting materials of group III and group V of the Periodic table, the ratio of V / III in which is from about 100 to 500. 11. The method according to claim 1 or 2, in which at the stage of pulsed growth in a reactor for growing in at least one of successive cycles, alternately introducing the source of gaseous substances of group III and group V of the Periodic table, in which the ratio V / III is approximately from 60 to 100. 12. The method according to claim 1 or 2, in which at the stage of pulsed growth, the vertical growth rate is adjusted to approximately 2 μm / h or more. 13. The method according to claim 1 or 2, in which each nanowire from the group of nanowires has a length of from about 10 nm to 100 microns. 14. The method according to claim 1 or 2, in which the growth mode is switched from non-pulsed to pulsed when the growing core of the nanowire protrudes above the mask for selective growth, with the formation of a group of truncated pyramidal nanostructures partially located on the surface of the mask for selective growth, then each pyramidal nanostructure from the group of said pyramidal nanostructures is formed into a filamentous part of the nanowire by continuing the pulsed growth of nanowires, the cross sections of the nanowires and the upper side of each of the pyramidal nanostructures essentially coincide. 15. The method according to 14, in which the filamentary part of the semiconductor nanowire has a cross-sectional size smaller than the cross-sectional size of each hole from the group of holes arranged in a specific order. 16. The matrix of nanowires, including a substrate with a group of selective surface sections and nanowires of nitrides of group III elements, obtained by the method according to claim 1 or 2, each connected to and leaving the corresponding section from the group of these selective sections, wherein said nanowire is oriented along a single directions, and its cross section remains the same as that of the corresponding section from the group of selective surface sections. 17. The matrix according to clause 16, in which the nanowires are composed of GaN and oriented along the crystallographic direction (0001). 18. The matrix according to clause 16, in which each nanowire includes at least one material selected from the group consisting of GaN, AlN, InN, InGaN, AlGaN and AlInGaN. 19. The matrix according to clause 16, in which the cross-sectional shape of each nanowire is selected from the group comprising a polygon, rectangle, square, oval and circle. 20. The matrix according to clause 16, in which each nanowire additionally has a size ratio of approximately 100 or more, and the size of its cross section is approximately 250 nm or less. 21. The matrix according to clause 16, in which the substrate includes a group of nanowires of nitrides of elements of group III of the Periodic table, wherein the whisker of each nanowire is located on the surface of the corresponding core of the nanowire, the surface of the whisker of the nanowire is the surface of a truncated pyramidal structure formed in as a result of the growth of a nanowire core on top of a mask for selective growth at the initial non-pulse growth stage. 22. The matrix according to item 21, in which the substrate further includes a pyramidal nanostructure of nitrides of elements of group III of the Periodic table, formed from nuclei of a nanowire of nitrides of elements of III and partially located on a mask for selective growth, the upper face of the nanostructure includes itself is one region from a group of selective regions of the substrate surface. 23. A matrix of nanowires of nitrides of elements of group III of the Periodic table, including a substrate, a mask for selective growth, located on top of the specified substrate, a group of holes arranged in a certain order in which a group of selective surface portions of the aforementioned substrate are exposed, and a group of III-N nanowires, each of which is connected to and leaves the corresponding section from the group of these selective sections, while each of these nanowires are oriented along a single direction, and its cross section remains the same as that of the corresponding region from the group of selective regions of the substrate surface. 24. A semiconductor device made of gallium nitride, including:
a matrix of nanowires containing a group of GaN nanowires, each of which is free from defects, and
a GaN film obtained by splicing a group of GaN nanowires, which is characterized by a defect density of approximately 10 ⁷ / cm ^-2 or less,
moreover, these GaN nanowires obtained by the method according to claim 1 or 2. 25. A substrate comprising a group of nanowires obtained by the method according to claim 1 or 2.

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