RU2422985C1 - Structure of filter of control circuit for phase automatic frequency control device - Google Patents

Abstract

FIELD: radio engineering. ^ SUBSTANCE: resistor (R3) and controlled switching element (K1) are introduced to control circuit filter (CCF) diagram containing operating amplifier OA (1), capacitor (C1) and resistors (R1) and (R2). When switching element (K1) is closed, multiple increase in recharge current flowing through capacitor (C 1) occurs, and thus, increase in speed of voltage turning to CCF is provided. Due to the fact that some portion of resistance (R1) and (R2) is transferred to R3 the total value of resistors and CCF surface area occupied on the microcircuit chip is proportionally decreased. ^ EFFECT: reducing the time of transient process in circuit of phase automatic frequency control owing to quick voltage tuning on control circuit filter, and reduction of surface area occupied with control circuit filter on microcircuit chip in case of fully integral implementation. ^ 4 dwg

Description

The present invention relates to integrated electronic technology and can be used in phase-locked loop (PLL) devices and, more specifically, when implementing a control loop filter (PCF) with a high control voltage tuning speed and, in the case of a fully integrated implementation, a small area occupied PKU on a chip chip.

PLL devices are widely used in frequency grid synthesizers (SSNs), digital clock generation and distribution schemes, and clock information recovery schemes from a data stream. With the advent of technologies that allow the creation of high-density integrated circuits, the tendency to minimize the use of components external to the microcircuit is becoming more apparent. This tendency has fully affected the design of PLL integrated devices, all of whose elements should be placed on the chip chip.

A typical block diagram of a pulsed PLL system is shown in FIG. It includes: a pulse frequency-phase detector 1 (ICHFD), a charge sustaining current source 2 (IITF), a control loop filter 3 (FCU), a low-pass filter 4 (LPF), a voltage-controlled generator 5 (VCO) and a divider frequency 6 (PM). PLL system synchronism is ensured by eliminating the phase error between the pulse edges of the reference frequency signals Fop and the feedback frequency Fcos. For this purpose, ICPD generates the corresponding pulse signals of phase mismatch Up or Down. Under the influence of these signals, the IETF either gives off or receives current from the PCF circuit, thereby forming a control voltage Uupr for automatic adjustment of the frequency and phase of the VCO. The low-pass filter suppresses ripple in the voltage Uupr caused by the pulsed nature of the control. The multiplication of the input reference frequency is provided by the inclusion of the PM in the feedback circuit. The output frequency signal Fout is removed from the output of the VCO.

A typical block diagram of a PCF consists of a capacitor Cn providing a pole point in the transfer function of the system and an isodromic link Req, Seq, providing a zero point. To ensure stability and acceptable oscillation of the frequency auto-tuning process, the zero point is located before the pole point. In this case, the system should have a sufficient phase margin. To implement the appropriate frequency correction of the control loop, the capacitance of the capacitor SECV is usually at least ten times greater than the capacitance of the capacitor Cn. For a given current of IETF, the minimum value of Cn is limited by the requirements for reducing the ripple of the control voltage Uupr already at the input of the low-pass filter. The value of the minimum current of the IEPR is limited by the level of interference from other blocks in the chip substrate. As a result, the SEC capacitor has a large capacitance and, accordingly, occupies a large area on the chip chip, which is a significant drawback of this structure of the integral PKU.

The description of the invention is known to US patent No. 7567133 "Phase-Locked Loop Filter Capacitance With A Drag Current", IPC H03L 7/00 [1]. This invention relates to methods for reducing the value of the capacitor of the PKU isodromic link and presents a circuit based on the use of an operational amplifier (op amp). This scheme is selected as an analogue of the prototype of the claimed invention and is shown in figure 2.

The circuit of the PKU of FIG. 2 includes: an operational amplifier ОУ1, a capacitor С1, and first and second resistors R1 and R2; the first terminal of the resistor R1 and the first terminal of the resistor R2 are connected to the control voltage line Uupr; the second terminal of the resistor R1, the first terminal of the capacitor C1 and the non-inverting input of the operational amplifier OU1 are interconnected; the second output of the resistor R2, inverting the input of the operational amplifier and the output of the operational amplifier are interconnected; the second terminal of capacitor C1 is connected to the ground line.

We assume that the input bias voltage and input leakage currents of the operational amplifier are zero. In this case, the voltages at the non-inverting input and output of OS1 are equal and the currents I ₁ and I ₂ flowing through the resistors R1 and R2 are inversely proportional to the values of their resistances

.

.

By a suitable choice of the ratio of the resistance of the resistor R1 to the resistance of the resistor R2, the current I _C1 flowing into the capacitor C1, compared with the current I from flowing into the isodromic link, can be reduced by a factor of M

,

,

.Where

.

As a result, a lower capacitance C1 can be used to replace a larger equivalent capacitance SECV of FIG. 1

With _ECV = M × C ₁ .

In this case, Req

R _ECV = R ₁ || R ₂ .

However, this scheme has disadvantages. The first drawback is a significant increase in the total value of R _{Σ of the} resistances of the resistors R1 and R2 compared with the equivalent resistance Req of the replaced isodromic link of figure 1. Moreover, with a large coefficient M, the value C1 replaces the value of C _equiv , the more R _Σ increases

.

.

The second disadvantage is the impossibility of quickly adjusting the voltage across the capacitor C1 to reduce the time of the transient process of automatic tuning of the frequency at the stage when the PLL circuit develops large phase mismatch.

The technical result of the present invention is the creation of an integrated PKU structure, which occupies a smaller area on the chip chip by reducing the total value of the resistors, and reducing the transient time in the PLL by increasing the speed of the voltage tuning across the capacitor of the PKU isodromic link.

The specified result is achieved by the fact that in the PKU, which includes: the first and second resistors, an operational amplifier and a capacitor; the first terminal of the first resistor and the first terminal of the second resistor are interconnected; the second terminal of the first resistor, the first terminal of the capacitor and the non-inverting input of the operational amplifier are interconnected; the second output of the second resistor inverting the input of the operational amplifier and the output of the operational amplifier are interconnected; the second terminal of the capacitor is connected to the ground line; It is proposed to introduce a third resistor and a controlled switching element; the first terminal of the third resistor and the first terminal of the switching element are connected to the control voltage line; the second terminal of the third resistor is connected to the first terminal of the first resistor; the second terminal of the switching element is connected to the second terminal of the first resistor; the control element of the switching element receives a control signal of the switching element.

As a result, due to the implementation of a part of the resistance R _{equiv by the} third resistor, the total value of R _{Σ of the} resistance of the resistors is reduced compared to R _{Σ of the} invention [1]. An increase in the speed of tuning the voltage across the capacitor is ensured by the fact that when the switching element is closed, almost all the current flowing into the isodromic link flows into this capacitor. As a result, the rate of charge of the capacitor increases almost M times compared with the invention [1]. At the same time, C _equiv decreases approximately to the value of the given capacitor, and R _equiv decreases approximately to the value of the resistance of the switching element in the closed state.

The invention is illustrated by the following graphic materials:

Figure 1 is a typical block diagram of a pulsed PLL system.

Figure 2 - scheme PKU presented in the invention [1] and selected as an analogue of the prototype of the claimed invention.

Figure 3 - scheme PKU claimed in this invention.

Figure 4 is a structural diagram of a practical integrated implementation of the claimed circuit PKU and low-pass filter.

The inventive circuit PKU is presented in figure 3. The PKU includes: the first, second, and third resistors R1, R2, and R3, an operational amplifier ОУ1, a capacitor C1, and a controlled switching element K1; the first terminal of the first resistor R1, the first terminal of the second resistor R2 and the second terminal of the third resistor R3 are interconnected; the first output of the switching element K1 and the first output of the third resistor R3 are connected to the control voltage line Uupr; the second output of the switching element K1, the second output of the first resistor R1, the first output of the capacitor C1 and the non-inverting input of the operational amplifier OU1 are interconnected; the second output of the second resistor R2, inverting the input of the operational amplifier and the output of the operational amplifier OU1 are interconnected; the second terminal of capacitor C1 is connected to a ground line; to the control input of the switching element K1, a signal S of controlling the switching element is supplied.

The switching element K1 can be performed on an N-channel or P-channel transistor or on a complementary pair of such transistors, when the sources of P and N-channel transistors are connected and form the 1st output of the switching element, the drains of P and N-channel transistors are connected and form 2nd output of the switching element, the corresponding control signals are supplied to the gates of the transistors.

For the scheme presented in figure 3, the formula for calculating the value of C _equiv coincides with the formula for calculating the value of C _{equiv of figure} 2. Moreover, R _equiv

R _ECV = R _K || (R ₃ + (R ₁ || R ₂ )),

where R _K is the value of the resistance of the switching element K1. If the condition of the switching element is open, the condition

R _K >> R ₃ + (R ₁ || R ₂ ),

then R _ECV = R ₃ + (R ₁ || R ₂ ).

The technical result of the claimed invention is the reduction of R _Σ value of the total resistance of the resistors R1, R2 and R3 is provided in proportion to the implementation of part of the resistance Rekv resistor R3

,

,

.Where

.

Thus, the closer the coefficient P to unity, the closer R _Σ to Req. The values of the resistors R1, R2 and R3 are chosen so as to guarantee the required accuracy of installation of R _equiv and coefficient M, taking into account technological variations in the production of the chip chip.

The technical result of the claimed invention is the reduction of the transient time in the PLL by increasing the speed of the voltage tuning on the capacitor C1 of the isodromic link is provided as follows. The current I _C1 flowing through the capacitor C1 is equal to

,

,

where I ₃ is the current through the resistor R3 equal to

,

,

where I _to is the current through the switching element K1.

From here

For the closed state of the switching element, it is not difficult to implement the following condition:

R _K <0.1 × (R ₃ + (R ₁ || R ₂ )).

Thus, when the switching element K1 is closed, almost the entire current I _from flowing into the isodromic link flows into the capacitor C1. As a result, the charge rate of the capacitor C1 increases by almost M times compared to the invention [1]. Wherein

With _ECV ≈C ₁ ,

R _ECV ≈R _K.

Figure 4 presents a structural diagram of a practical integrated implementation of the claimed circuit 3 PKU and circuit 4 low-pass filter of the third order. As well as in the PCF, in this low-pass filter, switching elements K2 and K3, controlled by the same signal S, are used to quickly adjust the control voltage Ufnch at the output of the low-pass filter. The operational amplifier ОУ1 and elements С1, R1, R2 and R3 are an isodromic link providing a zero point in the transfer function of the system. Capacitor C2 provides a pole point in the transfer function of the system. The operational amplifier OU2 and the elements R4, R5, C3 and C4 are an active second-order filter implemented according to the voltage-controlled voltage source circuit. The first-order passive filter R6, C5 is designed to reduce the magnitude of the resonant peak in the passband of the active filter and enhance filtering in the suppression band. The achievement of high dynamic accuracy by the PLL during the transient process of automatic tuning of the frequency is ensured due to the rapid tuning of the voltage across the capacitors of the PCF and low-pass filter. In steady state, the necessary suppression of interference caused by the pulsed nature of the control is provided by the characteristics of the low-pass filter. In this inclusion, both operational amplifiers use unipolar power, which is an essential requirement for most practical integrated applications.

However, the scope of the PKU circuit shown in FIG. 3 is not limited to integral applications only. According to the principle of its operation, an increase in the speed of voltage tuning on the capacitor C1 of the isodromic link is carried out without increasing the output current of the IITF, which is an additional advantage and makes this circuit convenient not only with a fully integrated implementation of the PLL, but also when implemented on individual components.

Claims (1)

A control loop filter (PCF) for a phase locked loop (PLL) device comprising: first and second resistors, an operational amplifier and a capacitor; the first terminal of the first resistor and the first terminal of the second resistor are interconnected; the second terminal of the first resistor, the first terminal of the capacitor and the non-inverting input of the operational amplifier are interconnected; the second output of the second resistor inverting the input of the operational amplifier and the output of the operational amplifier are interconnected; the second terminal of the capacitor is connected to the ground line, characterized in that a third resistor and a controlled switching element are introduced; the first terminal of the third resistor and the first terminal of the switching element are connected to the control voltage line; the second terminal of the third resistor is connected to the first terminal of the first resistor; the second terminal of the switching element is connected to the second terminal of the first resistor; the control element of the switching element receives a control signal of the switching element.

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