RU2312456C1 - Circuit for controlling serial key on metal-dielectric-semiconductor transistor - Google Patents

Abstract

FIELD: electric engineering, possible use in impulse secondary electric power supplies.

SUBSTANCE: control circuit contains power metal-dielectric-semiconductor transistor (1), load (2), coupled between source (1) and negative bus (14) of power supply, controlling transistor (13), serially connected diode (10) and resistive divider (11,12), capacitor (5). Introduced additionally are two transistors (6,7), two diodes (8,9) and two resistors (3,4), where collector-base transition of transistor (6) is coupled in parallel to resistor (11) of divider, base-emitter transition of transistor (6) is bridged by a contra-directionally coupled first diode (8), emitter of transistor (6) is connected to collector of transistor (7) and to one contact of capacitor (5), other contact of which is connected to source of transistor (1), base-emitter transition of transistor (7) is bridged by a contra-directionally coupled diode (9), where base of transistor (7) and cathode of diode (9) are connected to collector of controlling transistor (13) and to contact of resistor (12) of divider, and emitter of transistor (7) through resistor (4) is connected to gate of transistor (1), resistor (3) is installed in parallel to gate-source transition of transistor (1).

EFFECT: increased efficiency and increased speed of operation of key on metal-dielectric-semiconductor transistor.

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Description

The invention relates to electrical engineering and can be used in pulsed secondary power sources. The technical result is to increase the efficiency and performance of the MOS transistor switch.

The technical solution adopted for the prototype is a MOS transistor control circuit containing a key power MOS transistor, the drain of which is connected to the positive bus of the power source, the source is connected to the first output terminal, the second terminal of which is connected to the negative bus of the power source, the transistor gate is connected with the collector of the control npn transistor, two resistors and a diode connected in series, the anode of the diode connected to the positive bus of the power supply, the cathode connected to the first resistor, common point the first and second resistors are connected to the first output of the capacitor, the second output of the capacitor is connected to the source of the MOS transistor, the second output of the second resistor is connected to the collector of the control npn transistor, the emitter of which is connected to the negative bus of the power supply (Oxner E.S. Powerful field-effect transistors and their application. - M.: Radio and communications, 1985, p.137, 138).

The disadvantage of the prototype is its low speed, because when you turn on the MOS transistor, the pulse gate current is limited by the high resistance value of the second resistor, and when you turn off the MIS transistor, the capacitor charge current is limited by the resistance value of the first resistor. A decrease in the resistance value of the second resistor will lead to an increase in power consumption, and, given that the value of the gate-source voltage Uzi is determined by the ratio of the first and second resistors, it is necessary to simultaneously decrease the value of the first resistor. This will predetermine an even more significant decrease in efficiency. The technical result of the claimed invention is an increase in efficiency and increase the speed of the key on the MOS transistor.

The technical result is achieved by the fact that in the control circuit of the serial key on the MOS transistor containing the power MOS transistor, the load connected between the source of the MOS transistor and the negative bus of the power source, the control transistor, the diode and the resistive divider, the capacitor connected in series, are additionally introduced two transistors, two diodes and two resistors.

The drawing shows the proposed control circuit serial key on the MOS transistor, where the following notation:

1 - power MOS transistor operating in key mode;

2 - load;

3, 4 - resistors;

11, 12 - resistive divider;

5 - capacitor;

6, 7 - transistors;

13 - control transistor;

8, 9, 10 - diodes;

14 - negative bus power supply;

15 - positive bus power source.

The serial key control circuit on the MOS transistor contains a power transistor 1 operating in key mode, the drain of transistor 1 is connected to the positive bus 15 of the power source, the source of the transistor 1 is connected to the first output terminal of the load 2, the second terminal of which is connected to the negative bus 14 of the power source, a resistor 3 is installed between the gate and the source of transistor 1, the gate of transistor 1 is connected to the first output of resistor 4, the second output of resistor 4 is connected to the emitter of transistor 7 and the anode of diode 9, the cathode of diode 9 and the base of the transistor Ora 7 are interconnected and connected to the collector of transistor 13, the emitter of which is connected to the negative bus 14 of the power source, the anode of the diode 10 is connected to the positive bus 15 of the power source, the cathode of the diode 10 is connected to the collector of the transistor 6 and to the first output of the resistor 11, the second output the resistor 11 is connected to the first terminal of the resistor 12, the second terminal of which is connected to the collector of the transistor 13, the cathode of the diode 8 and the base of the transistor 6 are connected to the common point of the resistors 11, its emitter is connected to the anode of the diode 8, with the collector of the transistor and 7 and to a first terminal of the capacitor 5, the second terminal of which is connected to the source of transistor 1.

The device operates as follows.

Consider the static mode - the time intervals during which the transistors are in saturation or cutoff mode.

Let the control transistor 13 is open and saturated. The gate of the transistor 1 through the resistor 4, the diode 9 and the open transistor 13 is connected to the negative bus 14 of the power source. Since the transistor 1 is connected according to the source follower circuit, the load 2 is connected between the source of the transistor 1 and the negative bus 14 of the power source, which is connected to the emitter of the transistor 13, the gate-source voltage of the transistor 1 is close to zero and the transistor 1 is closed.

In this mode, a voltage is formed on the capacitor 5 that is necessary and sufficient to turn on the transistor 1.

Transistor 6 and diodes 9, 10 are open, and transistor 7 and diode 8 are closed.

If the control transistor 13 is closed, the current through the diode 10 and the transistor 6 does not flow. In this mode, the capacitor 5 is the voltage source for turning on the transistor 1. The current flows from the plus plate of the capacitor 5 through the diode 8, transistor 7 and resistors 3, 4, charging the input capacitance of transistor 1, opens and holds it open. Transistor 1 is open.

Transistor 7 and diode 8 are open, and transistor 6 and diodes 9, 10 are closed.

Thus, the key transistor 1 and the control transistor 13 operate in antiphase.

Consider the dynamic mode - the time intervals during which the transistors during the transition from saturation to the cutoff and vice versa operate in linear mode.

Suppose that in the initial state, the control transistor 13 is closed, and the transistor 1 is open.

At the time of formation of the base current front of the transistor 13, the latter goes from the cutoff mode to the saturation mode.

The consequence of this is the simultaneously occurring transients in the circuit:

- discharge capacitance Szy transistor 1;

- inclusion of a transistor 6 and diodes 9, 10;

- charge capacitor capacitance 5.

The discharge of the Szi capacitance of transistor 1 occurs by the current flowing through the gate circuit of transistor 1 - resistor 4 - diode 9 - transistor 13 - negative bus 14 - load 2 - source of transistor 1. Since transistor 13 and diode 9 in the conduction mode have a low dynamic resistance, then the Szi capacitance discharge current is limited only by the low-resistance value of the resistor 4.

In the circuit, a positive bus 15 — diode 10 — resistor 11 — resistor 12 — transistor 13 — negative bus 14 forms a current front, part of which includes transistor 6.

The inclusion of the transistor 6, operating in linear mode, leads to the charge of the capacitor 5 by the current flowing through the circuit positive bus 15 - diode 10 - transistor 6 - capacitor 5 - load 2 - negative bus 14.

If the transistor 13 is open, and the transistor 1 is closed, at the time of the formation of the recession of the base current of the transistor 13, the latter goes from saturation to the cutoff mode.

The consequence of this is the simultaneously occurring transients in the circuit:

- the inclusion of the transistor 7 and the diode 8;

- charge capacitance Szy transistor 1;

- discharge of the capacitor 5.

There is a current flowing through the circuit of the capacitor 5 - diode 8 - resistor 12 - the base-emitter junction of the transistor 7 - resistor 4 - resistor 3 - capacitor 5. This current turns on the transistor 7. The capacitance of the Szi transistor 1 is charged by the current flowing through the circuit of the capacitor 5 - transistor 7 - resistor 4 - gate of transistor 1 - source of transistor 1.

Since the transistor 1 operating in linear mode has a low dynamic resistance, the charge current of the Szi capacitance of the transistor 1 is limited only by the low-resistance value of the resistance of the resistor 4.

The charge current of the capacitance Szy of the transistor 1 is the discharge current of the capacitor 5.

Thus, the inclusion of two transistors and two diodes in the circuit allows you to create current loops for:

- fast charge and discharge capacitance Szy power transistor 1 when it is switched;

- fast charge and discharge of the capacitor 5 when switching the control transistor 13.

The consequence of this is a reduction in power consumption in dynamic mode.

In addition, the circuit allows you to install resistors with a large resistance value in the collector circuit of the control transistor, which reduces power consumption in static mode.

The consequence of these modes of operation of the circuit is to reduce static and dynamic power losses, and therefore, increase the efficiency and increase the speed of the key on the MOS transistor.

Claims (1)

A serial key control circuit on an MOS transistor, comprising a power MOS transistor, a load connected between the source of the MOS transistor and the negative bus of the power supply, a control transistor, a diode and a resistive divider connected in series, a capacitor, characterized in that two transistors are inserted into it , two diodes and two resistors, and the collector-base junction of the first transistor is connected in parallel with one divider resistor, the base-emitter junction of the first transistor is shunted by the first on a diode, while the base of the first transistor and the cathode of the first diode are connected to a common point of the divider resistors, the emitter of the first transistor is connected to the collector of the second transistor and to one output of the capacitor, the other terminal of which is connected to the source of the MOS transistor, the base-emitter junction of the second transistor is counter-shunted the second diode turned on, while the base of the second transistor and the cathode of the second diode are connected to the collector of the control transistor and to the output of another divider resistor, and the emitter of the second transistor is black Without the first resistor connected to the gate of the MOS transistor, the second resistor is installed parallel to the gate-source transition of the MOS transistor.